mirror of
https://github.com/a52xq-dev/kernel.git
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* this imports the latest version of SM-A526B kernel from https://opensource.samsung.com/uploadSearch?searchValue=SM-A526B |
34794f4cb2
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[ Upstream commit 89d29997f103d08264b0685796b420d911658b96 ] eznps driver is supposed to be platform independent however it ends up including stuff from inside arch/arc headers leading to rand config build errors. The quick hack to fix this (proper fix is too much chrun for non active user-base) is to add following to nps platform agnostic header. - copy AUX_IENABLE from arch/arc header - move CTOP_AUX_IACK from arch/arc/plat-eznps/*/** Reported-by: kernel test robot <lkp@intel.com> Reported-by: Sebastian Andrzej Siewior <bigeasy@linutronix.de> Link: https://lkml.kernel.org/r/20200824095831.5lpkmkafelnvlpi2@linutronix.de Signed-off-by: Vineet Gupta <vgupta@synopsys.com> Signed-off-by: Sasha Levin <sashal@kernel.org> 
Vineet Gupta
authored and
 Greg Kroah-Hartman
commited |
10d4f8d200 | |
[ Upstream commit 13136a47a061c01c91df78b37f7708dd5ce7035f ] Implement support for the PMC_IMPL_E_33V_PWR register which replaces PMC_PWR_DET register interface of the SoC generations preceding Tegra186. Also add the voltage bit offsets to the tegra186_io_pads[] table and the AO_HV pad. Signed-off-by: Aapo Vienamo <avienamo@nvidia.com> Acked-by: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Sasha Levin <sashal@kernel.org> 
Aapo Vienamo
authored and
Greg Kroah-Hartman
commited |
a124e7f2fe | |
Add a couple of new APIs to check the probing status of qman and bman: 'int bman_is_probed()' and 'int qman_is_probed()'. They return the following values. * 1 if qman/bman were probed correctly * 0 if qman/bman were not yet probed * -1 if probing of qman/bman failed Drivers that use qman/bman driver services are required to use these APIs before calling any functions exported by qman or bman drivers or otherwise they will crash the kernel. The APIs will be used in the following couple of qbman portal patches and later in the series in the dpaa1 ethernet driver. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Signed-off-by: Li Yang <leoyang.li@nxp.com> 
Laurentiu Tudor
authored and
 Li Yang
commited |
853dc104e6 | |
Moves DPAA2 DPIO driver from staging to fsl/soc Adds multiple-pin support to QE gpio driver -----BEGIN PGP SIGNATURE----- Version: GnuPG v1 iQIcBAABAgAGBQJbV51GAAoJEIbcUA77rBVUzB0P/1l1XZ14jlyIc4PI8eiEKx2i Emet7qvEaeeoRYI06Dqtm+VkNYjO2Ev4n+XQYPTZGP3/b+cPh7CEI1N/L+ULFGop HtD0FsOikvfql7BMHvGCCRLzFYHYjDNpg8JCB/3q+aOhI3/8HQyVIAEyggh1Ztam NSmMQXHwdB8d1qAGcSYGttiJCIxLcDUtVEGcF6ZN6Lg3orpDHEbCceeQ10f1yayQ PZuM+F1YFM4Lp17gt92caMSKENsN0Kyk/7lEVPHq0ANGMvVsHIVtZGJML+/ulaeI v7FZrEicYJVu8LDkFAPeg3qK+O6WirOa9bQEctH7jia43QWZAZ9EROCkFOzlEwx6 +AmOB5BsqMTQsz7HppNOqB6v3zgK898UIYavGeud0c/SaIqAW3uVkKvHLKxXd/uY K2eyvxcBs9ttK+qLopLWO1QzwWAvedIZFjSDCYpGcWDlhZR1lOqoC1u6wSApX/ZC h7SGOOhjmzZBLtS89hHn7LnzN7RI6teNmC9uhdFtY+55IVfcRAzX3m2ym/TWPRc8 dQNA/vNMuXK2Hv8rtElqIEVUvWil3p86+640m1fnbkljmSqgzp8vAIAopUbhq2Qj QytaQBwWPcIoAgKQjLMOypjyCTyNs1oFhKycGlwL4Jq5BwxWq27714fl+dSk4JMz itj5Fz0+82WeDts7CBjM =9CHI -----END PGP SIGNATURE----- Merge tag 'soc-fsl-for-4.19' of git://git.kernel.org/pub/scm/linux/kernel/git/leo/linux into next/drivers Various updates to soc/fsl for 4.19 Moves DPAA2 DPIO driver from staging to fsl/soc Adds multiple-pin support to QE gpio driver * tag 'soc-fsl-for-4.19' of git://git.kernel.org/pub/scm/linux/kernel/git/leo/linux: soc: fsl: cleanup Kconfig menu soc: fsl: dpio: Convert DPIO documentation to .rst staging: fsl-mc: Remove remaining files staging: fsl-mc: Move DPIO from staging to drivers/soc/fsl staging: fsl-dpaa2: eth: move generic FD defines to DPIO soc: fsl: qe: gpio: Add qe_gpio_set_multiple Signed-off-by: Olof Johansson <olof@lixom.net> 
Olof Johansson
commited |
1ca8c0a763 | |
* Add Qualcomm LLCC driver * Add Qualcomm RPMH controller * Fix memleak in Qualcomm RMTFS * Add dummy qcom_scm_assign_mem() * Fix check for global partition in SMEM -----BEGIN PGP SIGNATURE----- Version: GnuPG v1 iQIcBAABAgAGBQJbU6fmAAoJEFKiBbHx2RXV7XQQAIu/F5xLNdwaTl0ZRMOKgCEt Ry6ggc6IdldP/B3O92texnQYmqybBsraSTdrCtYFTbsScuQYNR8kcMDVsaeAKAIx f0cF5c0hwco1BRbSzfxszoCf/L0bCm9HMhlzgIsMxPzyQxfi6JLTGC2Dy83TBWfp 3NtetOjzwGQZm4dqm5itxbGZNHUjkx15jcNau1cPztMAZouWqoVjbcdZkFGPyP7i Qa/K6/s8eUXkD4fxJZYD5OMO/P8NrMP4QQteYRdXzTteVtwxlCgOxkPHlrMRaIqm xeza4LW19AImKPyoodTaGQuTYzaJOa2t0it6VCo80SmRB0xXhix64+t+XFR4kQXR txddfdAz5EGBTClyqw8FQGFVPnvxoVz8FkjUEH/xrgDDCvG6zjNHSkoimEMDSfV0 8DbQQI0elMD2vUttDieLNjrSGNmDIVbz5QNWHF8E0VoAVNgL+EX2sNQQe8TUq5GG W2l7VsAQdwi5eTsaVzZpkcwRan1kkPu39Rt8CY36E5wCj4sALOszIG4OVW1PJohi nP7xajCocFgf408Se/u4ApV5IcCLki/UQqC5ppFM5XlyTtNfzdBnvWVVylJtpwFU 1m4D+soWyCqeTtACCkvQQyu+ztV4VAqyPZc/heK8/ANJRMwMlPTZSH6kIHFC4obF K5sFkqYOkflmuSjczH/E =t3C0 -----END PGP SIGNATURE----- Merge tag 'qcom-drivers-for-4.19' of git://git.kernel.org/pub/scm/linux/kernel/git/agross/linux into next/drivers Qualcomm ARM Based Driver Updates for v4.19 * Add Qualcomm LLCC driver * Add Qualcomm RPMH controller * Fix memleak in Qualcomm RMTFS * Add dummy qcom_scm_assign_mem() * Fix check for global partition in SMEM * tag 'qcom-drivers-for-4.19' of git://git.kernel.org/pub/scm/linux/kernel/git/agross/linux: soc: qcom: rmtfs-mem: fix memleak in probe error paths soc: qcom: llc-slice: Add missing MODULE_LICENSE() drivers: qcom: rpmh: fix unwanted error check for get_tcs_of_type() drivers: qcom: rpmh-rsc: fix the loop index check in get_req_from_tcs firmware: qcom: scm: add a dummy qcom_scm_assign_mem() drivers: qcom: rpmh-rsc: Check cmd_db_ready() to help children drivers: qcom: rpmh-rsc: allow active requests from wake TCS drivers: qcom: rpmh: add support for batch RPMH request drivers: qcom: rpmh: allow requests to be sent asynchronously drivers: qcom: rpmh: cache sleep/wake state requests drivers: qcom: rpmh-rsc: allow invalidation of sleep/wake TCS drivers: qcom: rpmh-rsc: write sleep/wake requests to TCS drivers: qcom: rpmh: add RPMH helper functions drivers: qcom: rpmh-rsc: log RPMH requests in FTRACE dt-bindings: introduce RPMH RSC bindings for Qualcomm SoCs drivers: qcom: rpmh-rsc: add RPMH controller for QCOM SoCs drivers: soc: Add LLCC driver dt-bindings: Documentation for qcom, llcc soc: qcom: smem: Correct check for global partition Signed-off-by: Olof Johansson <olof@lixom.net>
Olof Johansson
commited |
d7e8323043 | |
Move the NXP DPIO (Datapath I/O Driver) out of the drivers/staging directory and into the drivers/soc/fsl directory. The DPIO driver enables access to Queue and Buffer Manager (QBMAN) hardware on NXP DPAA2 devices. This is a prerequisite to moving the DPAA2 Ethernet driver out of staging. Signed-off-by: Roy Pledge <roy.pledge@nxp.com> Reviewed-by: Horia Geantă <horia.geanta@nxp.com> Reviewed-by: Ioana Radulescu <ruxandra.radulescu@nxp.com> Signed-off-by: Li Yang <leoyang.li@nxp.com> 
Roy Pledge
authored and
Li Yang
commited |
c89105c9b3 | |
Platform drivers need make a lot of resource state requests at the same time, say, at the start or end of an usecase. It can be quite inefficient to send each request separately. Instead they can give the RPMH library a batch of requests to be sent and wait on the whole transaction to be complete. rpmh_write_batch() is a blocking call that can be used to send multiple RPMH command sets. Each RPMH command set is set asynchronously and the API blocks until all the command sets are complete and receive their tx_done callbacks. Signed-off-by: Lina Iyer <ilina@codeaurora.org> Signed-off-by: Raju P.L.S.S.S.N <rplsssn@codeaurora.org> Reviewed-by: Matthias Kaehlcke <mka@chromium.org> Signed-off-by: Andy Gross <andy.gross@linaro.org> 
Lina Iyer
authored and
 Andy Gross
commited |
c8790cb6da | |
Platform drivers that want to send a request but do not want to block until the RPMH request completes have now a new API - rpmh_write_async(). The API allocates memory and send the requests and returns the control back to the platform driver. The tx_done callback from the controller is handled in the context of the controller's thread and frees the allocated memory. This API allows RPMH requests from atomic contexts as well. Signed-off-by: Lina Iyer <ilina@codeaurora.org> Signed-off-by: Raju P.L.S.S.S.N <rplsssn@codeaurora.org> Signed-off-by: Andy Gross <andy.gross@linaro.org>
Lina Iyer
authored and
Andy Gross
commited |
564b5e24cc | |
Active state requests are sent immediately to the RSC controller, while sleep and wake state requests are cached in this driver to avoid taxing the RSC controller repeatedly. The cached values will be sent to the controller when the rpmh_flush() is called. Generally, flushing is a system PM activity and may be called from the system PM drivers when the system is entering suspend or deeper sleep modes during cpuidle. Also allow invalidating the cached requests, so they may be re-populated again. Signed-off-by: Lina Iyer <ilina@codeaurora.org> [rplsssn: remove unneeded semicolon, address line over 80chars error] Signed-off-by: Raju P.L.S.S.S.N <rplsssn@codeaurora.org> Reviewed-by: Evan Green <evgreen@chromium.org> Reviewed-by: Matthias Kaehlcke <mka@chromium.org> Signed-off-by: Andy Gross <andy.gross@linaro.org>
Lina Iyer
authored and
Andy Gross
commited |
600513dfee | |
Sending RPMH requests and waiting for response from the controller through a callback is common functionality across all platform drivers. To simplify drivers, add a library functions to create RPMH client and send resource state requests. rpmh_write() is a synchronous blocking call that can be used to send active state requests. Signed-off-by: Lina Iyer <ilina@codeaurora.org> Signed-off-by: Raju P.L.S.S.S.N <rplsssn@codeaurora.org> Signed-off-by: Andy Gross <andy.gross@linaro.org>
Lina Iyer
authored and
Andy Gross
commited |
c1038456b0 | |
Add controller driver for QCOM SoCs that have hardware based shared resource management. The hardware IP known as RSC (Resource State Coordinator) houses multiple Direct Resource Voter (DRV) for different execution levels. A DRV is a unique voter on the state of a shared resource. A Trigger Control Set (TCS) is a bunch of slots that can house multiple resource state requests, that when triggered will issue those requests through an internal bus to the Resource Power Manager Hardened (RPMH) blocks. These hardware blocks are capable of adjusting clocks, voltages, etc. The resource state request from a DRV are aggregated along with state requests from other processors in the SoC and the aggregate value is applied on the resource. Some important aspects of the RPMH communication - - Requests are <addr, value> with some header information - Multiple requests (upto 16) may be sent through a TCS, at a time - Requests in a TCS are sent in sequence - Requests may be fire-n-forget or completion (response expected) - Multiple TCS from the same DRV may be triggered simultaneously - Cannot send a request if another request for the same addr is in progress from the same DRV - When all the requests from a TCS are complete, an IRQ is raised - The IRQ handler needs to clear the TCS before it is available for reuse - TCS configuration is specific to a DRV - Platform drivers may use DRV from different RSCs to make requests Resource state requests made when CPUs are active are called 'active' state requests. Requests made when all the CPUs are powered down (idle state) are called 'sleep' state requests. They are matched by a corresponding 'wake' state requests which puts the resources back in to previously requested active state before resuming any CPU. TCSes are dedicated for each type of requests. Active mode TCSes (AMC) are used to send requests immediately to the resource, while control TCS are used to provide specific information to the controller. Sleep and Wake TCS send sleep and wake requests, after and before the system halt respectively. Signed-off-by: Lina Iyer <ilina@codeaurora.org> Signed-off-by: Raju P.L.S.S.S.N <rplsssn@codeaurora.org> Signed-off-by: Andy Gross <andy.gross@linaro.org>
Lina Iyer
authored and
Andy Gross
commited |
658628e7ef | |
Recent Raspberry Pi firmware provides a mailbox property to detect under-voltage conditions. Here is the current definition. The u32 value returned by the firmware is divided into 2 parts: - lower 16-bits are the live value - upper 16-bits are the history or sticky value Bits: 0: undervoltage 1: arm frequency capped 2: currently throttled 16: undervoltage has occurred 17: arm frequency capped has occurred 18: throttling has occurred Signed-off-by: Stefan Wahren <stefan.wahren@i2se.com> Signed-off-by: Eric Anholt <eric@anholt.net> Reviewed-by: Eric Anholt <eric@anholt.net> 
Stefan Wahren
authored and
 Eric Anholt
commited |
be3035e362 | |
This is a branch with a few merge requests that either came in late, or took a while longer for us to review and merge than usual and thus cut it a bit close to the merge window. We stage them in a separate branch and if things look good, we still send them up -- and that's the case here. This is mostly DT additions for Renesas platforms, adding IP block descriptions for existing and new SoCs. There are also some driver updates for Qualcomm platforms for SMEM/QMI and GENI, which is their generalized serial protocol interface. -----BEGIN PGP SIGNATURE----- iQJDBAABCAAtFiEElf+HevZ4QCAJmMQ+jBrnPN6EHHcFAlsfCVIPHG9sb2ZAbGl4 b20ubmV0AAoJEIwa5zzehBx3KOcP/3O2+igstXt5rhemITdyi8rHkrIHPgetf25e ISBQzYrQOHV21SqT4le/Gk2CCQ6iX5Nv2DYoIrCzFWi/4DoDxXvryczQLla02Nru i8fcuxae7aFGW7/97G1+cATGPwuBLPiKXs6Wj01sKHeLBja5Det7eoXuHag7Y/Lo 4ls9wNZybMdlCcGm6+ULdj+XUdRyYUhOQQYvnPm2Q8hEkM+AiwLOBJTFwef9P5ad mX37kPDfwCxYwQXgZB1RkK/oJu0G2mTZXmGH5o+s+9yAyAupCQhmHGOrt3mlOf7j tLRlSgarJlO/QGIpJmDuCcxt3msD3OMd2dPbdgwojdpvycOU8EVWYLmCRpyIWQXv DCv9A9Gp4KlJnwxheVegBtilRA1aKsGuarWq6yeyOFt8N23Bgg/IjYKI9JF5+hPD M4q1oVAbUlfWb79rEc+TB0d7euREBkNn4TzzKMSOyP3eGUrXR0WUlq2A2VLxgIJo cx/ufY7CwvRgV+VxfhRbca+FmwDnu7uqzwLe73Ys2hnsuv8hXEtc+vSybqKqxVeU nHpWAqwaWhijlJiGq722vPo8avrLwjsxRwimogvijtesz9ZlTqrGtjkg61+eN2h8 eeuyRAsMUfVRiKuL3W+q4s0rzIauormnKsvRScKVyNFuiJfrfYb1odLoDGaOV/9G dQ7hA7TW =RUL0 -----END PGP SIGNATURE----- Merge tag 'armsoc-late' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc Pull ARM SoC late updates from Olof Johansson: "This is a branch with a few merge requests that either came in late, or took a while longer for us to review and merge than usual and thus cut it a bit close to the merge window. We stage them in a separate branch and if things look good, we still send them up -- and that's the case here. This is mostly DT additions for Renesas platforms, adding IP block descriptions for existing and new SoCs. There are also some driver updates for Qualcomm platforms for SMEM/QMI and GENI, which is their generalized serial protocol interface" * tag 'armsoc-late' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (186 commits) soc: qcom: smem: introduce qcom_smem_virt_to_phys() soc: qcom: qmi: fix a buffer sizing bug MAINTAINERS: Update pattern for qcom_scm soc: Unconditionally include qcom Makefile soc: qcom: smem: check sooner in qcom_smem_set_global_partition() soc: qcom: smem: fix qcom_smem_set_global_partition() soc: qcom: smem: fix off-by-one error in qcom_smem_alloc_private() soc: qcom: smem: byte swap values properly soc: qcom: smem: return proper type for cached entry functions soc: qcom: smem: fix first cache entry calculation soc: qcom: cmd-db: Make endian-agnostic drivers: qcom: add command DB driver arm64: dts: renesas: salvator-common: Add ADV7482 support ARM: dts: r8a7740: Add CEU1 ARM: dts: r8a7740: Add CEU0 arm64: dts: renesas: salvator-common: enable VIN arm64: dts: renesas: r8a77970: add VIN and CSI-2 nodes arm64: dts: renesas: r8a77965: add VIN and CSI-2 nodes arm64: dts: renesas: r8a7796: add VIN and CSI-2 nodes arm64: dts: renesas: r8a7795-es1: add CSI-2 node ... 
Linus Torvalds
commited |
8efcf34a26 | |
The tegra_cpuidle_pcie_irqs_in_use() function is stubbed out for non-ARM
builds, but now we can compile-test the Tegra pci driver on non-Tegra
ARM platforms as well, which results in a new link error:
drivers/pci/host/pci-tegra.o: In function `tegra_pcie_map_irq':
pci-tegra.c:(.text+0x288): undefined reference to `tegra_cpuidle_pcie_irqs_in_use'
drivers/pci/host/pci-tegra.o: In function `tegra_msi_map':
pci-tegra.c:(.text+0xba0): undefined reference to `tegra_cpuidle_pcie_irqs_in_use'
This adapts the #ifdef statement to match the exact condition under which
the function can be called.
Fixes:
Arnd Bergmann
authored and
Olof Johansson
commited |
32561354b1 | |
* Various SMEM updates/fixes * Add qcom_smem_virt_to_phys SMEM API * Update MAINTAINERS to include qcom_scm pattern * Add Qualcomm Command DB driver * Add Qualcomm SCM compatible for IPQ4019 * Add MSM8998 to smd-rpm compatible list * Add Qualcomm GENI based QUP wrapper * Fix Qualcomm QMI buffer sizing bug -----BEGIN PGP SIGNATURE----- Version: GnuPG v1 iQIcBAABAgAGBQJbCHgwAAoJEFKiBbHx2RXVUHEP+wWnlsXvaoT50PRavwcW2Gbk OLWpWWeh90TRtuW9IZ+VXUhClVSvSBi+M46xKqO2M/0WumNRRE4dZDL3DjSqOBVZ 2MQP+uhfviv5GqpEuPq18luedV6S0orsQY+FLmqD4+/vHW8oXUvC1m2iqsYkst27 gtPYSiuVZkJDc0pvPzsFDFL5WBQ84W4ki2Jsc2xuf0clUxASoOfT8/RFyZ1M3suV R9hzOUCWY1+c+YZbvYyPTLu1Y20ksHcnfnhAc/ZUxGyzIWLX30XWjc26pJbF8eRU EJiI0pyPkzue4GokrWI1H9AOgmSoJjdMFg0uvz3Y6opreKJi5+GSiVZeojU7/e5a yNhrdF6R9jp5n/jwvql7yiMHwxiv8dzuSvvlQCJfEMVZBD2maPAojiXXOFs06pNg WdhKFO5x4XH+kkiUnDs7sXpT/Szd1Eqr9wsIxLj9pbH++0Z5TYpOjFkE948fiLa9 QUywzT4TLD5/N4z4iIsE8Xd4Zm+jxlQ/1AEouegntkav0UgCeJsHlijGl2T5xrPC NDRSUpABI6Ypf+mDlxsVI+9WZm7o7PTAVUVnOrKF7FRZRNdGOLsrV0f5awJuyBgf XfhsOUm6IB3vzON2TrvVno7Fa4vdOFFGZsTbn8hdW2YSDpgLmebHZg20hAjXrImd 8VB7e4tK0yPtweUfIg9U =hFnt -----END PGP SIGNATURE----- Merge tag 'qcom-drivers-for-4.18' of git://git.kernel.org/pub/scm/linux/kernel/git/agross/linux into next/late Qualcomm ARM Based Driver Updates for v4.18 * Various SMEM updates/fixes * Add qcom_smem_virt_to_phys SMEM API * Update MAINTAINERS to include qcom_scm pattern * Add Qualcomm Command DB driver * Add Qualcomm SCM compatible for IPQ4019 * Add MSM8998 to smd-rpm compatible list * Add Qualcomm GENI based QUP wrapper * Fix Qualcomm QMI buffer sizing bug * tag 'qcom-drivers-for-4.18' of git://git.kernel.org/pub/scm/linux/kernel/git/agross/linux: soc: qcom: smem: introduce qcom_smem_virt_to_phys() soc: qcom: qmi: fix a buffer sizing bug MAINTAINERS: Update pattern for qcom_scm soc: Unconditionally include qcom Makefile soc: qcom: smem: check sooner in qcom_smem_set_global_partition() soc: qcom: smem: fix qcom_smem_set_global_partition() soc: qcom: smem: fix off-by-one error in qcom_smem_alloc_private() soc: qcom: smem: byte swap values properly soc: qcom: smem: return proper type for cached entry functions soc: qcom: smem: fix first cache entry calculation soc: qcom: cmd-db: Make endian-agnostic drivers: qcom: add command DB driver soc: qcom: Add GENI based QUP Wrapper driver soc: qcom: smd-rpm: Add msm8998 compatible firmware: qcom: scm: Add ipq4019 soc compatible Signed-off-by: Olof Johansson <olof@lixom.net>
Olof Johansson
commited |
ae709bf8ad | |
Command DB is a simple database in the shared memory of QCOM SoCs, that provides information regarding shared resources. Some shared resources in the SoC have properties that are probed dynamically at boot by the remote processor. The information pertaining to the SoC and the platform are made available in the shared memory. Drivers can query this information using predefined strings. Signed-off-by: Mahesh Sivasubramanian <msivasub@codeaurora.org> Signed-off-by: Lina Iyer <ilina@codeaurora.org> Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Reviewed-by: Stephen Boyd <swboyd@chromium.org> Signed-off-by: Andy Gross <andy.gross@linaro.org> 
Mahesh Sivasubramanian
authored and
Andy Gross
commited |
312416d917 | |
This contains some cleanup of the memory controller driver as well as unification work to share more code between Tegra20 and later SoC generations. Also included are an implementation for the hot resets functionality by the memory controller which is required to properly reset busy hardware. -----BEGIN PGP SIGNATURE----- iQJHBAABCAAxFiEEiOrDCAFJzPfAjcif3SOs138+s6EFAlr/O5kTHHRyZWRpbmdA bnZpZGlhLmNvbQAKCRDdI6zXfz6zoYBuD/0StspIEG9GK8xOdf93unbziinCZ2DG e+xae7l5VfC2VsG5MgyYCr0ugOThdHHzqqsit3uHBXe9cUlNaL6YKyAiTIT7HFNM a0lnE+I++p0bL0GqMa/9l9jWnheR5iKnZYratyKJjtmEd9ljDcgo4Xn0lUonf3NS 9gmI/2qiqkry+pLRafN65H6mbK6JyQ07xZAqd322S8aVkKx10L+GwzMjj6K342zu KPJd5B2mpCkaAc9maFOY5zcljaRBNU5mFGJEzhdzrq6KXcfDnZxyufVX80RhP9vO 9RQJyFVsFiBgH59YPBc72X8Nu0Cc/14jTH1rE55R4239y96cJ/LuniYtHcWqumuL OQgsMfslO8RJ9/XBy/0UEznx1hnDJGfT7s2SRfgCsGnKegvcSw1IASI7xA+49DIR ZpVLEIB3Htq5DGymQrDG99z6tccMV5PJNEOjDhrh74DSXy9S/6Hl9UAoX3455/7Y zP2B5yUfaCnipwWXSowzmkXRKfCrHus1o//YfyarhmRVeDNeMkdbPcxGFZL7Y+MC PPorRu+WdKKzcY+8xmQig+UY2K3thpYSNG1D8vZLC6Dv3r06qGAk2vy9pV2bYG86 4FG9Ory36XK/5fnfLTvTPnbguRNI1y/hbQ7XTTJcnxCvUqNkT7bAgspPfn0gkY+1 Uh8Jm57WooiwHQ== =uVPT -----END PGP SIGNATURE----- Merge tag 'tegra-for-4.18-memory-v2' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into next/drivers memory: tegra: Changes for v4.18-rc1 This contains some cleanup of the memory controller driver as well as unification work to share more code between Tegra20 and later SoC generations. Also included are an implementation for the hot resets functionality by the memory controller which is required to properly reset busy hardware. * tag 'tegra-for-4.18-memory-v2' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux: dt-bindings: memory: tegra: Remove Tegra114 SATA and AFI reset definitions memory: tegra: Remove Tegra114 SATA and AFI reset definitions memory: tegra: Register SMMU after MC driver became ready memory: tegra: Add Tegra210 memory controller hot resets memory: tegra: Add Tegra124 memory controller hot resets memory: tegra: Add Tegra114 memory controller hot resets memory: tegra: Add Tegra30 memory controller hot resets memory: tegra: Add Tegra20 memory controller hot resets memory: tegra: Introduce memory client hot reset memory: tegra: Squash tegra20-mc into common tegra-mc driver memory: tegra: Remove unused headers inclusions memory: tegra: Apply interrupts mask per SoC memory: tegra: Setup interrupts mask before requesting IRQ memory: tegra: Do not handle spurious interrupts dt-bindings: memory: tegra: Add hot resets definitions Signed-off-by: Olof Johansson <olof@lixom.net>
Olof Johansson
commited |
6874f9de65 | |
In order to reset busy HW properly, memory controller needs to be involved, otherwise it is possible to get corrupted memory or hang machine if HW was reset during DMA. Introduce memory client 'hot reset' that will be used for resetting of busy HW. Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Signed-off-by: Thierry Reding <treding@nvidia.com> 
Dmitry Osipenko
authored and
 Thierry Reding
commited |
20e92462cd | |
Tegra30+ has some minor differences in registers / bits layout compared to Tegra20. Let's squash Tegra20 driver into the common tegra-mc driver in a preparation for the upcoming MC hot reset controls implementation, avoiding code duplication. Note that this currently doesn't report the value of MC_GART_ERROR_REQ because it is located within the GART register area and cannot be safely accessed from the MC driver (this happens to work only by accident). The proper solution is to integrate the GART driver with the MC driver, much like is done for the Tegra SMMU, but that is an invasive change and will be part of a separate patch series. Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
Dmitry Osipenko
authored and
Thierry Reding
commited |
a8d502fd33 | |
Currently we are enabling handling of interrupts specific to Tegra124+ which happen to overlap with previous generations. Let's specify interrupts mask per SoC generation for consistency and in a preparation of squashing of Tegra20 driver into the common one that will enable handling of GART faults which may be undesirable by newer generations. Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
Dmitry Osipenko
authored and
Thierry Reding
commited |
1c74d5c0de | |
If CONFIG_RASPBERRYPI_FIRMWARE=n:
drivers/gpio/gpio-raspberrypi-exp.c: In function ‘rpi_exp_gpio_get_polarity’:
drivers/gpio/gpio-raspberrypi-exp.c:71: warning: ‘get.polarity’ is used uninitialized in this function
drivers/gpio/gpio-raspberrypi-exp.c: In function ‘rpi_exp_gpio_get_direction’:
drivers/gpio/gpio-raspberrypi-exp.c:150: warning: ‘get.direction’ is used uninitialized in this function
The dummy firmware interface functions return 0, which means success,
causing subsequent code to make use of the never initialized output
parameter.
Fix this by making the dummy functions return an error code (-ENOSYS)
instead.
Note that this assumes the firmware always fills in the requested data
in the CONFIG_RASPBERRYPI_FIRMWARE=y case.
Fixes:
Geert Uytterhoeven
authored and
 Florian Fainelli
commited |
144345a4a8 | |
The main addition this time around is the new ARM "SCMI" framework,
which is the latest in a series of standards coming from ARM to do power
management in a platform independent way. This has been through many
review cycles, and it relies on a rather interesting way of using the
mailbox subsystem, but in the end I agreed that Sudeep's version was
the best we could do after all.
Other changes include:
- the ARM CCN driver is moved out of drivers/bus into drivers/perf,
which makes more sense. Similarly, the performance monitoring
portion of the CCI driver are moved the same way and cleaned up
a little more.
- a series of updates to the SCPI framework
- support for the Mediatek mt7623a SoC in drivers/soc
- support for additional NVIDIA Tegra hardware in drivers/soc
- a new reset driver for Socionext Uniphier
- lesser bug fixes in drivers/soc, drivers/tee, drivers/memory, and
drivers/firmware and drivers/reset across platforms
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1
iQIcBAABAgAGBQJaxiNzAAoJEGCrR//JCVInYhYP/2kPhc5t/kszA1bcklcbO9dY
eX37Ra/RR4yQ5yeQZVIZ4UkUovxk9PmG2tM4K5oJaTDsz5pPEgavVOOr3sbfj6vb
4O9auTeysEQlHcbVdNFum0YS2gUY2YD7D12DTRorotLxCqod184ccWXq0XGfIWaY
l3YRrcL/lPlqmyS3z/GNx9oNygOMUzEfXfIQYICyzHuYiLBUGnkKC1vIb+Hx1TDq
Cxk++AUqH13Mss24O2A2QQh+oBHj2BybDLLqwcC5PSpsUbFrVCfzG54l43mig32T
NOxV0Qnml2wAtU4H0QcgtSgwRimHD0YOiX8ssquvDDiqTqM5G+llSTGkEbYe+AUW
4GIZYoBOwGkfEXS+tyymHe9yfc5h1OLYAeFU1jRm723c7phanuu67rPn35YC8UMK
zSql10JpkAGNzMikrxxb6wnis951w2UFlzhgZQ6ItA/nRq3l+oEQA0Qiljv965nz
DVLsD5+gdhK6GBctkzlsD5HFn6GjM8JilnsOVPHD765nKnVBSxKiXRLV228XVug2
rChF1FhQqLnM54jCMqHZX5fS9SbSgtYswHqIXpVw6GmJkqq/Ly10yGR0vuWD+uyn
BV7q5AKpGrwm6wZkMM2uZ1VdUtWzn856AbkqrvX/QhmJcX4McuqaLUrC8bSOj1ty
KeVil0akq3nU+xHl5Ojs
=Pmsx
-----END PGP SIGNATURE-----
Merge tag 'armsoc-drivers' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull ARM SoC driver updates from Arnd Bergmann:
"The main addition this time around is the new ARM "SCMI" framework,
which is the latest in a series of standards coming from ARM to do
power management in a platform independent way.
This has been through many review cycles, and it relies on a rather
interesting way of using the mailbox subsystem, but in the end I
agreed that Sudeep's version was the best we could do after all.
Other changes include:
- the ARM CCN driver is moved out of drivers/bus into drivers/perf,
which makes more sense. Similarly, the performance monitoring
portion of the CCI driver are moved the same way and cleaned up a
little more.
- a series of updates to the SCPI framework
- support for the Mediatek mt7623a SoC in drivers/soc
- support for additional NVIDIA Tegra hardware in drivers/soc
- a new reset driver for Socionext Uniphier
- lesser bug fixes in drivers/soc, drivers/tee, drivers/memory, and
drivers/firmware and drivers/reset across platforms"
* tag 'armsoc-drivers' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (87 commits)
reset: uniphier: add ethernet reset control support for PXs3
reset: stm32mp1: Enable stm32mp1 reset driver
dt-bindings: reset: add STM32MP1 resets
reset: uniphier: add Pro4/Pro5/PXs2 audio systems reset control
reset: imx7: add 'depends on HAS_IOMEM' to fix unmet dependency
reset: modify the way reset lookup works for board files
reset: add support for non-DT systems
clk: scmi: use devm_of_clk_add_hw_provider() API and drop scmi_clocks_remove
firmware: arm_scmi: prevent accessing rate_discrete uninitialized
hwmon: (scmi) return -EINVAL when sensor information is unavailable
amlogic: meson-gx-socinfo: Update soc ids
soc/tegra: pmc: Use the new reset APIs to manage reset controllers
soc: mediatek: update power domain data of MT2712
dt-bindings: soc: update MT2712 power dt-bindings
cpufreq: scmi: add thermal dependency
soc: mediatek: fix the mistaken pointer accessed when subdomains are added
soc: mediatek: add SCPSYS power domain driver for MediaTek MT7623A SoC
soc: mediatek: avoid hardcoded value with bus_prot_mask
dt-bindings: soc: add header files required for MT7623A SCPSYS dt-binding
dt-bindings: soc: add SCPSYS binding for MT7623 and MT7623A SoC
...
Linus Torvalds
commited |
38c23685b2 | |
These changes are rather small, with just a fix for a return value check and some preparatory work for Tegra194 BPMP support. -----BEGIN PGP SIGNATURE----- iQJHBAABCAAxFiEEiOrDCAFJzPfAjcif3SOs138+s6EFAlqrz+cTHHRyZWRpbmdA bnZpZGlhLmNvbQAKCRDdI6zXfz6zoeYLEACtgcGVUSA/gsqdskhIHVE9zVmFgQes sivqoXAsMKvuHnBpJ3QG0BLXF0FWFmXwpRtCmblWwsp+OredeXv+Kv7Zki4/hvBD IsuXaerTxTcI8PgD94TwiPNqSX8HrqAvQs5402QxShSkQO0eGXUcFo3I1nzKAerm kHX2GNBqg2qDaAGA7jUcmAs/XNV4hxdm3tPWntqgB89jyuM2Qhyg0/v/XVnYjZJr gc8oClIpXZMdM1dRLbHWMVYUBLeSIHdAGVp9mfx53cCALoW9aGmwceO0I7ZWU2F0 07YHSnoRZO6Ma2+yzoDFNeaOzA3yuX2dfGYQ+kHHUXdWvO61uArs5eBrOinPNPSb +ohQtkxcU29NZ5YkIaS1C36sKrPDJMYFm/6aKB8bp+I+cy16g/P6I3XE5yFu/r55 7uWmfEiu9oNvllHEEPSlsslwaFZds9l8ticQ5D+DUm6duPsInrk4hNrqXRlM9daK kHw5dq/+gAZJOUhhjMqhTthyqpqKHJlR6hUX9clEB8H2LMkGbcQZQGJ669nNJBL1 FxROPfSm1cPsU6YdXePY0OGHoGN0U2jVgDgqwNdZW1I8QZSH1YDAG1I7YvCEyGdf 4egRaOPcE7JGhaOExVxDEI8Z1Nk1HAoSLEwVKeIeJEcrzknzCmAtnJ4L9tSlwYFp Ea8cQ9BWAcqX0w== =oigm -----END PGP SIGNATURE----- Merge tag 'tegra-for-4.17-firmware' of ssh://gitolite.kernel.org/pub/scm/linux/kernel/git/tegra/linux into next/drivers Pull "firmware: Changes for v4.17-rc1" from Thierry Reding: These changes are rather small, with just a fix for a return value check and some preparatory work for Tegra194 BPMP support. * tag 'tegra-for-4.17-firmware' of ssh://gitolite.kernel.org/pub/scm/linux/kernel/git/tegra/linux: firmware: tegra: adjust tested variable firmware: tegra: Simplify channel management
Arnd Bergmann
commited |
d0994465d0 | |
-----BEGIN PGP SIGNATURE----- iQFSBAABCAA8FiEEq68RxlopcLEwq+PEeb4+QwBBGIYFAlqlyPEeHHRvcnZhbGRz QGxpbnV4LWZvdW5kYXRpb24ub3JnAAoJEHm+PkMAQRiGNa0H/RIa/StQuYu/SBwa JRqQFmkIsx+gG+FyamJrqGzRfyjounES8PbfyaN3cCrzYgeRwMp1U/bZW6/l5tkb OjTtrCJ6CJaa21fC/7aqn3rhejHciKyk83EinMu5WjDpsQcaF2xKr3SaPa62Ja24 fhawKq3CnUa+OUuAbicVX8yn4viUB6x8FjSN/IWfp3Cs4IBR7SGxxD7A4MET9FbQ 5OOu0al8ly9QeCggTtJyk+cApeLfexEBTbUur9gm7GcH9jhUtJSyZCZsDJx6M2yb CwdgF4fyk58c1fuHvTFb0AdUns55ba3nicybRHHMVbDpZIG9v4/M1yJETHHf5cD7 t3rFjrY= =+Ldf -----END PGP SIGNATURE----- Merge tag 'v4.16-rc5' into devel Linux 4.16-rc5 merged into the GPIO devel branch to resolve a nasty conflict between fixes and devel in the RCAR driver. Signed-off-by: Linus Walleij <linus.walleij@linaro.org> 
Linus Walleij
commited |
95260c17b2 | |
The Tegra194 BPMP only implements 5 channels (4 to BPMP, 1 to CCPLEX), and they are not placed contiguously in memory. The current channel management in the BPMP driver does not support this. Simplify and refactor the channel management such that only one atomic transmit channel and one receive channel are supported, and channels are not required to be placed contiguously in memory. The same configuration also works on T186 so we end up with less code. Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com> 
Mikko Perttunen
authored and
Thierry Reding
commited |
1abb081e41 | |
- MCIP aka ARconnect fixes for SMP builds [Euginey] - Preventive fix for SLC (L2 cache) flushing [Euginey] - Kconfig default fix [Ulf Magnusson] - trailing semicolon fixes [Luis de Bethencourt] - other assorted minor fixes -----BEGIN PGP SIGNATURE----- Version: GnuPG v1 iQIcBAABAgAGBQJamHh7AAoJEGnX8d3iisJeM+MQAL+cIkdRd9NJoPPL66IOgwmi 68jUkVQ8PSgR2P/sWvwIRTionOG9siu58Q1ygXpPR9SNnSJlyIYIW4Onuoajs+Ii TmTwWm8jnKtuPtKMBep8XpYQQ+FRL6sDNn0QLjCnnvqAeE7rTFODSlpBR+jL6ur4 t2h1wHQem6oas1YRwnKrxxMnfV3KP3TkCS2a/lvmeAAt8xi+ll+9OnzVcSCj7pCJ ZToenfH3UAbhAd5T7gWkJv2v00zbHNzKtpdluSW6WBybP1Ib2IxOxEiUlAvxQgpl NctvS8Q1uveOPQZHO+fNXsJvf+imP2RdWh5RaOcmm8a4tp8jsR51BScX55usjr/z ybg4bzHBV3x9YbZkkW9DKyF9eeZ7hWST8nNoebcHNVjboUeD+wgtV8e3Fvc6bIoo /Xkw28y/mZwCs7mBfu1fNOIIiiZDSgz7YeeqzOPBzEYVcHE4VGINwX+9cLXPOsgz rmI/Md3buSjrfXPnXTuk1R4fl0WKM5FT/2BJ+IbNU2w6VO1/iKqiBQREH5lBfYAI BUikxKNwrJ9+zG8EXFUAEi6gn4dxosxMKJ04CTviwGFc1y6yNsmMgizevFpPUyx7 9o3z19hHUZLx94QsGHLI7QJe3Kawamu0tmdJvQBgB/eZ9lj6OdkzY48I2lgGezSw 00e+JPSy6EDi8YrlMki5 =+Bmc -----END PGP SIGNATURE----- Merge tag 'arc-4.15-rc4' of git://git.kernel.org/pub/scm/linux/kernel/git/vgupta/arc Pull ARC fixes from Vineet Gupta: - MCIP aka ARconnect fixes for SMP builds [Euginey] - preventive fix for SLC (L2 cache) flushing [Euginey] - Kconfig default fix [Ulf Magnusson] - trailing semicolon fixes [Luis de Bethencourt] - other assorted minor fixes * tag 'arc-4.15-rc4' of git://git.kernel.org/pub/scm/linux/kernel/git/vgupta/arc: ARC: setup cpu possible mask according to possible-cpus dts property ARC: mcip: update MCIP debug mask when the new cpu came online ARC: mcip: halt GFRC counter when ARC cores halt ARCv2: boot log: fix HS48 release number arc: dts: use 'atmel' as manufacturer for at24 in axs10x_mb ARC: Fix malformed ARC_EMUL_UNALIGNED default ARC: boot log: Fix trailing semicolon ARC: dw2 unwind: Fix trailing semicolon ARC: Enable fatal signals on boot for dev platforms ARCv2: Don't pretend we may set L-bit in STATUS32 with kflag instruction ARCv2: cache: fix slc_entire_op: flush only instead of flush-n-inv
Linus Torvalds
commited |
2120447b5d | |
As of today we use hardcoded MCIP debug mask, so if we launch kernel via debugger and kick fever cores than HW has all cpus hang at the momemt of setup MCIP debug mask. So update MCIP debug mask when the new cpu came online, instead of use hardcoded MCIP debug mask. Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com> Signed-off-by: Vineet Gupta <vgupta@synopsys.com> 
Eugeniy Paltsev
authored and
Vineet Gupta
commited |
f3205de98d | |
In SMP systems, GFRC is used for clocksource. However by default the counter keeps running even when core is halted (say when debugging via a JTAG debugger). This confuses Linux timekeeping and triggers flase RCU stall splat such as below: | [ARCLinux]# while true; do ./shm_open_23-1.run-test ; done | Running with 1000 processes for 1000 objects | hrtimer: interrupt took 485060 ns | | create_cnt: 1000 | Running with 1000 processes for 1000 objects | [ARCLinux]# INFO: rcu_preempt self-detected stall on CPU | 2-...: (1 GPs behind) idle=a01/1/0 softirq=135770/135773 fqs=0 | INFO: rcu_preempt detected stalls on CPUs/tasks: | 0-...: (1 GPs behind) idle=71e/0/0 softirq=135264/135264 fqs=0 | 2-...: (1 GPs behind) idle=a01/1/0 softirq=135770/135773 fqs=0 | 3-...: (1 GPs behind) idle=4e0/0/0 softirq=134304/134304 fqs=0 | (detected by 1, t=13648 jiffies, g=31493, c=31492, q=1) Starting from ARC HS v3.0 it's possible to tie GFRC to state of up-to 4 ARC cores with help of GFRC's CORE register where we set a mask for cores which state we need to rely on. We update cpu mask every time new cpu came online instead of using hardcoded one or using mask generated from "possible_cpus" as we want it set correctly even if we run kernel on HW which has fewer cores than expected (or we launch kernel via debugger and kick fever cores than HW has) Note that GFRC halts when all cores have halted and thus relies on programming of Inter-Core-dEbug register to halt all cores when one halts. Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com> Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com> Signed-off-by: Vineet Gupta <vgupta@synopsys.com> [vgupta: rewrote changelog]
Eugeniy Paltsev
authored and
Vineet Gupta
commited |
07423d00a2 | |
Add latest firmware property tags from the latest Raspberry Pi downstream kernel. This is needed for the GPIO tags, so we can control the GPIO multiplexor lines. Acked-by: Stefan Wahren <stefan.wahren@i2se.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Linus Walleij <linus.walleij@linaro.org> 
Baruch Siach
authored and
Linus Walleij
commited |
08af112e79 | |
A number of new drivers get added this time, along with many low-priority
bugfixes. The most interesting changes by subsystem are:
bus drivers:
- Updates to the Broadcom bus interface driver to support newer SoC types
- The TI OMAP sysc driver now supports updated DT bindings
memory controllers:
- A new driver for Tegra186 gets added
- A new driver for the ti-emif sram, to allow relocating
suspend/resume handlers there
SoC specific:
- A new driver for Qualcomm QMI, the interface to the modem on MSM SoCs
- A new driver for power domains on the actions S700 SoC
- A driver for the Xilinx Zynq VCU logicoreIP
reset controllers:
- A new driver for Amlogic Meson-AGX
- various bug fixes
tee subsystem:
- A new user interface got added to enable asynchronous communication
with the TEE supplicant.
- A new method of using user space memory for communication with
the TEE is added
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1
iQIcBAABAgAGBQJac0fQAAoJEGCrR//JCVIntjEQALc6kflEGJc/FPundbx9V3F/
b+3+EX/uMnBnKsgZprz9ACPhx5eBH9QWja3A1zmIarb5c+q7zbBZDwhzUb8J8Yg8
xEb0im7Wx/GcKjUYZVKYBxtz9KjkXDzhrq8IAvPg6ShNcIy/8hq7ZO3iOkGsTDcy
/PyioWKC5g0dhJgtp91X1kgog5tuTaWOg39uUOqyEzwVu1vYVa4w+eeCzjEd6I//
68R/zDQ52+hWw6WZGoYOsNYzuriOflnJRnNpwuGhMhLNULBJfWnd4hkqGm4E+hFa
5dzW6vVAdIqjemFqPzCBT2WB4UG871aZX8DJ9HgnfX+g970nlsm1JY8Ck9MJNJum
aDkqZG41ArUYzDFWu8vJ2SKsue5lEZp6TEO2mLEVYrdOjOgedj0Zxqmq2DYeigxd
+ccOVgKJ9SsYw9ft1LkQ5BHCgOh3C7y9Kcg7oBnaEI5OTVvtf5PwEkT2cwbvgxYl
EVKLhlJ0Af+QXOW8E5JbNQETpYw52DMm6UKHiYn/JCGxB/8J0bgJzImDJI4Dtu2h
zqJITKJeTepqbfA5pmNfKa+20RhmsktdRCw2NN/QynY7EEtGjHAUVnlpZT2mrDco
0m62b7Erek/776vJN5ECzE5e6XCs2N0MDE6Anp121C5zEmig/SMBrUosMzP7Jnis
IDVC/QWkb3u85wK20Vc1
=yz0k
-----END PGP SIGNATURE-----
Merge tag 'armsoc-drivers' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull ARM SoC driver updates from Arnd Bergmann:
"A number of new drivers get added this time, along with many
low-priority bugfixes. The most interesting changes by subsystem are:
bus drivers:
- Updates to the Broadcom bus interface driver to support newer SoC
types
- The TI OMAP sysc driver now supports updated DT bindings
memory controllers:
- A new driver for Tegra186 gets added
- A new driver for the ti-emif sram, to allow relocating
suspend/resume handlers there
SoC specific:
- A new driver for Qualcomm QMI, the interface to the modem on MSM
SoCs
- A new driver for power domains on the actions S700 SoC
- A driver for the Xilinx Zynq VCU logicoreIP
reset controllers:
- A new driver for Amlogic Meson-AGX
- various bug fixes
tee subsystem:
- A new user interface got added to enable asynchronous communication
with the TEE supplicant.
- A new method of using user space memory for communication with the
TEE is added"
* tag 'armsoc-drivers' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (84 commits)
of: platform: fix OF node refcount leak
soc: fsl: guts: Add a NULL check for devm_kasprintf()
bus: ti-sysc: Fix smartreflex sysc mask
psci: add CPU_IDLE dependency
soc: xilinx: Fix Kconfig alignment
soc: xilinx: xlnx_vcu: Use bitwise & rather than logical && on clkoutdiv
soc: xilinx: xlnx_vcu: Depends on HAS_IOMEM for xlnx_vcu
soc: bcm: brcmstb: Be multi-platform compatible
soc: brcmstb: biuctrl: exit without warning on non brcmstb platforms
Revert "soc: brcmstb: Only register SoC device on STB platforms"
bus: omap: add MODULE_LICENSE tags
soc: brcmstb: Only register SoC device on STB platforms
tee: shm: Potential NULL dereference calling tee_shm_register()
soc: xilinx: xlnx_vcu: Add Xilinx ZYNQMP VCU logicoreIP init driver
dt-bindings: soc: xilinx: Add DT bindings to xlnx_vcu driver
soc: xilinx: Create folder structure for soc specific drivers
of: platform: populate /firmware/ node from of_platform_default_populate_init()
soc: samsung: Add SPDX license identifiers
soc: qcom: smp2p: Use common error handling code in qcom_smp2p_probe()
tee: shm: don't put_page on null shm->pages
...
Linus Torvalds
commited |
fe53d1443a | |
Create SMMU display groups for Tegra30, Tegra114, Tegra124 and Tegra210. This allows the display controllers on these devices to share the same IOMMU domain using the standard IOMMU group mechanism. Signed-off-by: Thierry Reding <treding@nvidia.com>
Thierry Reding
commited |
2a8102dfe0 | |
Move Tegra186 support to the consolidated PMC driver to reduce some of the duplication and also gain I/O pad functionality on the new SoC as a side-effect. Signed-off-by: Thierry Reding <treding@nvidia.com>
Thierry Reding
commited |
c641ec6eab | |
large change that introduces runtime PM support to the clk framework. Now we properly call runtime PM operations on the device providing a clk when the clk is in use. This helps on SoCs where the clks provided by a device need something to be powered on before using the clks, like power domains or regulators. It also helps power those things down when clks aren't in use. The other core change is a devm API addition for clk providers so we can get rid of a bunch of clk driver remove functions that are just doing of_clk_del_provider(). Outside of the core, we have the usual addition of clk drivers and smattering of non-critical fixes to existing drivers. The biggest diff is support for Mediatek MT2712 and MT7622 SoCs, but those patches really just add a bunch of data. By the way, we're trying something new here where we build the tree up with topic branches. We plan to work this into our workflow so that we don't step on each other's toes, and so the fixes branch can be merged on an as-needed basis. Core: - Runtime PM support for clk providers - devm API for of_clk_add_hw_provider() New Drivers: - Mediatek MT2712 and MT7622 - Renesas R-Car V3M SoC Updates: - Runtime PM support for Samsung exynos5433/exynos4412 providers - Removal of clkdev aliases on Samsung SoCs - Convert clk-gpio to use gpio descriptors - Various driver cleanups to match kernel coding style - Amlogic Video Processing Unit VPU and VAPB clks - Sigma-delta modulation for Allwinner audio PLLs - Allwinner A83t Display clks - Support for the second display unit clock on Renesas RZ/G1E - Suspend/resume support for Renesas R-Car Gen3 CPG/MSSR - New clock ids for Rockchip rk3188 and rk3368 SoCs - Various 'const' markings on clk_ops structures - RPM clk support on Qualcomm MSM8996/MSM8660 SoCs -----BEGIN PGP SIGNATURE----- Version: GnuPG v2.0.22 (GNU/Linux) iQIcBAABCAAGBQJaD3qRAAoJEK0CiJfG5JUlOLgQAKWekgG/IYgcPzPWDYfg8Hwr sVVUK7+q7TVfbHsbYVikJuUaxutKZ0onnrYmOalTTyyxqL2E1/rYScnxdYHfcwX8 cyfHebRHsbh/Xg45ktwjzBkO49nwuppkpXd/V80GSBUZ+lsIVl5DUrrFAZdRUEdr CEsAsF9tEWIl+0gqXYNuiKBV7QAYv5BUPrbJQf0PwL6jX0OAhLv+ukfN8BdmYsOb rdoqhdgmyHkTuIMqsC/H2yP59aAKBse7wxIYebDiTdbPWfTkC9q927fTs4A02F6L sHfLvCpfuB4rOjXy6LSd1gMGWIcjotZai+idHBqtNLLVz6exF1QpUCp+pZjEULbA /Sx9lk8A3cYoa8pTu1NrrZbZX17iHkFswqMF3T20nhUN9+Ti597ZEbRcWDcoEZtw v2NznOTJ7Mm2SrNHOvDklstggNIGcwiAEePGMo7rJNEQZChpDjQj/gJWKzn0UwL4 zfk+0EzoejPdvZ5FJUfmlr8Tqk53uw+y7/0xQ6gf8lDviTrzzoeXtJUyumGBiuGx RxFywf8n02oLYRJm5hu+0NkC+/bX0Lxg/kwiR6FLBFbBFgkWyp7FGcxhlm6ZiBfe 0KkPciWslNavn5KhljIkZDbXymbvhhSr9uBEFsyeJueA5q7sSghWloL8Ag1cac3W e6swD1ngXtM/t5gjOLhR =hC7z -----END PGP SIGNATURE----- Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux Pull clk updates from Stephen Boyd: "We have two changes to the core framework this time around. The first being a large change that introduces runtime PM support to the clk framework. Now we properly call runtime PM operations on the device providing a clk when the clk is in use. This helps on SoCs where the clks provided by a device need something to be powered on before using the clks, like power domains or regulators. It also helps power those things down when clks aren't in use. The other core change is a devm API addition for clk providers so we can get rid of a bunch of clk driver remove functions that are just doing of_clk_del_provider(). Outside of the core, we have the usual addition of clk drivers and smattering of non-critical fixes to existing drivers. The biggest diff is support for Mediatek MT2712 and MT7622 SoCs, but those patches really just add a bunch of data. By the way, we're trying something new here where we build the tree up with topic branches. We plan to work this into our workflow so that we don't step on each other's toes, and so the fixes branch can be merged on an as-needed basis. Summary: Core: - runtime PM support for clk providers - devm API for of_clk_add_hw_provider() New Drivers: - Mediatek MT2712 and MT7622 - Renesas R-Car V3M SoC Updates: - runtime PM support for Samsung exynos5433/exynos4412 providers - removal of clkdev aliases on Samsung SoCs - convert clk-gpio to use gpio descriptors - various driver cleanups to match kernel coding style - Amlogic Video Processing Unit VPU and VAPB clks - sigma-delta modulation for Allwinner audio PLLs - Allwinner A83t Display clks - support for the second display unit clock on Renesas RZ/G1E - suspend/resume support for Renesas R-Car Gen3 CPG/MSSR - new clock ids for Rockchip rk3188 and rk3368 SoCs - various 'const' markings on clk_ops structures - RPM clk support on Qualcomm MSM8996/MSM8660 SoCs" * tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: (137 commits) clk: stm32h7: fix test of clock config clk: pxa: fix building on older compilers clk: sunxi-ng: a83t: Fix i2c buses bits clk: ti: dra7-atl-clock: fix child-node lookups clk: qcom: common: fix legacy board-clock registration clk: uniphier: fix DAPLL2 clock rate of Pro5 clk: uniphier: fix parent of miodmac clock data clk: hi3798cv200: correct parent mux clock for 'clk_sdio0_ciu' clk: hisilicon: Delete an error message for a failed memory allocation in hisi_register_clkgate_sep() clk: hi3660: fix incorrect uart3 clock freqency clk: kona-setup: Delete error messages for failed memory allocations ARC: clk: fix spelling mistake: "configurarion" -> "configuration" clk: cdce925: remove redundant check for non-null parent_name clk: versatile: Improve sizeof() usage clk: versatile: Delete error messages for failed memory allocations clk: ux500: Improve sizeof() usage clk: ux500: Delete error messages for failed memory allocations clk: spear: Delete error messages for failed memory allocations clk: ti: Delete error messages for failed memory allocations clk: mmp: Adjust checks for NULL pointers ...
Linus Torvalds
commited |
fc35c1966e | |
* clk-at91: clk: at91: utmi: set the mainck rate 
Stephen Boyd
commited |
7a103f0225 | |
By default, it is assumed that the UTMI clock is generated from a 12 MHz reference clock (MAINCK). If it's not the case, the FREQ field of the SFR_UTMICKTRIM has to be updated to generate the UTMI clock in the proper way. The UTMI clock has a fixed rate of 480 MHz. In fact, there is no multiplier we can configure. The multiplier is managed internally, depending on the reference clock frequency, to achieve the target of 480 MHz. Signed-off-by: Ludovic Desroches <ludovic.desroches@microchip.com> Acked-by: Ingo van Lil <inguin@gmx.de> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> 
Ludovic Desroches
authored and
Stephen Boyd
commited |
92041a9ff0 | |
Tegra power management firmware running on the co-processor (BPMP) implements a simple pseudo file system akin to debugfs. The file system can be used for debugging purposes to examine and change the status of selected resources controlled by the firmware (such as clocks, resets, voltages, powergates, ...). Add support to "mirror" the firmware's file system to debugfs. At boot, query firmware for a list of all possible files and create corresponding debugfs entries. Read/write of individual files is implemented by sending a Message ReQuest (MRQ) that passes the full file path name and data to firmware via DRAM. Signed-off-by: Timo Alho <talho@nvidia.com> Reviewed-by: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com> 
Timo Alho
authored and
Thierry Reding
commited |
f2381f6522 | |
Add static inline stubs to bpmp.h when CONFIG_BPMP is not enabled. This allows building BPMP-related drivers with COMPILE_TEST. Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
Mikko Perttunen
authored and
Thierry Reding
commited |
80d47a91e5 | |
Expose and export the tegra_bpmp_mrq_return() function for use by drivers outside the core BPMP driver. This function is used to reply to messages originating from the BPMP, which is required in the thermal driver. Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
Mikko Perttunen
authored and
Thierry Reding
commited |
2e1e09ed42 | |
Response messages from Tegra BPMP firmware contain an error return code as the first word of payload. The error code is used to indicate incorrectly formatted request message or use of non-existing resource (clk, reset, powergate) identifier. Current implementation of tegra_bpmp_transfer() ignores this code and does not pass it to caller. Fix this by adding an extra struct member to tegra_bpmp_message and populate that with return code. Signed-off-by: Timo Alho <talho@nvidia.com> Acked-by: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
Timo Alho
authored and
Thierry Reding
commited |
370d010f0e | |
This branch contains platform-related driver updates for ARM and ARM64.
Among them:
- Reset driver updates:
+ New API for dealing with arrays of resets
+ Make unimplemented {de,}assert return success on shared resets
+ MSDKv1 driver
+ Removal of obsolete Gemini reset driver
+ Misc updates for sunxi and Uniphier
- SoC drivers:
+ Platform SoC driver registration on Tegra
+ Shuffle of Qualcomm drivers into a submenu
+ Allwinner A64 support for SRAM
+ Renesas R-Car R3 support
+ Power domains for Rockchip RK3366
- Misc updates and smaller fixes for TEE and memory driver subsystems
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1
iQIcBAABAgAGBQJZtdt7AAoJEIwa5zzehBx3EboP/jR2T9lrMavXR1zL48L14yJb
S+fiJlrX1Kr42UF4PQvsfs+uTqOLmycrPVFkMb6IwoUPzQ9UCOSoiMzYm2b7ZPvt
uIesHhdM3/xun6wKfieN8GmNA1yDVynTxo0TTYDw5ha7I6s2GHgw0GSFzy3wm0Qg
KzerAO3gzf3L5XsKR0cai3IXNjHO9ubpFG1ReR09da28nPElP8ggWg0KnqdO76Ch
BGpFj78EC875ZNqwHgnspUqgGDJnBjig3m/uA4FWA0G9Jl38tCyKTZfUR7cEraoV
kyCgBlR/UrI8eXVTyEy5k5iTsQ3A1VhX4rGjyH+5NZHTs1yWr4+RDND/qeGl9tSo
VASuOtH6Rc3vdUDpHPBNAFNQH8fwwDoKf96dvN1tiffsx6LSKb//NyOfkXzKOtR6
CP5raYfX4YktLtHq0XVTZ/6r3XmLcTHzElR/dCFpQOFcTOYii0pWtfcWouahbZ1w
dhoBX/dbNq37MfzrxtHN2VTIEHpn2GU7u+ZGkp2ArokD58BAft/M3Xee1cDnF75g
ZDwe5eNFT8aBZKaY7zwG8cdxiw9kACAivDRwW+zgpfUr39c+d0+QmVfnfJh4EGXK
Ri6yr2EfBWK6jw3cwkdSyyt7iSzIkB+RiuuD1MjpYhWzAvoDpzqkXYukFGbpXnuy
vUFHNuP1ocUsRtCs8mm1
=yBzS
-----END PGP SIGNATURE-----
Merge tag 'armsoc-drivers' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull ARM SoC driver updates from Olof Johansson:
"This branch contains platform-related driver updates for ARM and ARM64.
Among them:
- Reset driver updates:
+ New API for dealing with arrays of resets
+ Make unimplemented {de,}assert return success on shared resets
+ MSDKv1 driver
+ Removal of obsolete Gemini reset driver
+ Misc updates for sunxi and Uniphier
- SoC drivers:
+ Platform SoC driver registration on Tegra
+ Shuffle of Qualcomm drivers into a submenu
+ Allwinner A64 support for SRAM
+ Renesas R-Car R3 support
+ Power domains for Rockchip RK3366
- Misc updates and smaller fixes for TEE and memory driver
subsystems"
* tag 'armsoc-drivers' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (54 commits)
firmware: arm_scpi: fix endianness of dev_id in struct dev_pstate_set
soc/tegra: fuse: Add missing semi-colon
soc/tegra: Restrict SoC device registration to Tegra
drivers: soc: sunxi: add support for A64 and its SRAM C
drivers: soc: sunxi: add support for remapping func value to reg value
drivers: soc: sunxi: fix error processing on base address when claiming
dt-bindings: add binding for Allwinner A64 SRAM controller and SRAM C
bus: sunxi-rsb: Enable by default for ARM64
soc/tegra: Register SoC device
firmware: tegra: set drvdata earlier
memory: Convert to using %pOF instead of full_name
soc: Convert to using %pOF instead of full_name
bus: Convert to using %pOF instead of full_name
firmware: Convert to using %pOF instead of full_name
soc: mediatek: add SCPSYS power domain driver for MediaTek MT7622 SoC
soc: mediatek: add header files required for MT7622 SCPSYS dt-binding
soc: mediatek: reduce code duplication of scpsys_probe across all SoCs
dt-bindings: soc: update the binding document for SCPSYS on MediaTek MT7622 SoC
reset: uniphier: add analog amplifiers reset control
reset: uniphier: add video input subsystem reset control
...
Linus Torvalds
commited |
ae46654bcf | |
The M4U IP blocks in mt2712 is MTK's generation2 M4U which use the ARM Short-descriptor like mt8173, and most of the HW registers are the same. The difference is that there are 2 M4U HWs in mt2712 while there's only one in mt8173. The purpose of 2 M4U HWs is for balance the bandwidth. Normally if there are 2 M4U HWs, there should be 2 iommu domains, each M4U has a iommu domain. Signed-off-by: Yong Wu <yong.wu@mediatek.com> Signed-off-by: Joerg Roedel <jroedel@suse.de> 
Yong Wu
authored and
 Joerg Roedel
commited |
e6dec92308 | |
Move this code from arch/arm/mach-tegra and make it common among 32-bit and 64-bit Tegra SoCs. This is slightly complicated by the fact that on 32-bit Tegra, the SoC device is used as the parent for all devices that are instantiated from device tree. Signed-off-by: Thierry Reding <treding@nvidia.com>
Thierry Reding
commited |
27a0342ac1 | |
Pull networking updates from David Miller:
"Reasonably busy this cycle, but perhaps not as busy as in the 4.12
merge window:
1) Several optimizations for UDP processing under high load from
Paolo Abeni.
2) Support pacing internally in TCP when using the sch_fq packet
scheduler for this is not practical. From Eric Dumazet.
3) Support mutliple filter chains per qdisc, from Jiri Pirko.
4) Move to 1ms TCP timestamp clock, from Eric Dumazet.
5) Add batch dequeueing to vhost_net, from Jason Wang.
6) Flesh out more completely SCTP checksum offload support, from
Davide Caratti.
7) More plumbing of extended netlink ACKs, from David Ahern, Pablo
Neira Ayuso, and Matthias Schiffer.
8) Add devlink support to nfp driver, from Simon Horman.
9) Add RTM_F_FIB_MATCH flag to RTM_GETROUTE queries, from Roopa
Prabhu.
10) Add stack depth tracking to BPF verifier and use this information
in the various eBPF JITs. From Alexei Starovoitov.
11) Support XDP on qed device VFs, from Yuval Mintz.
12) Introduce BPF PROG ID for better introspection of installed BPF
programs. From Martin KaFai Lau.
13) Add bpf_set_hash helper for TC bpf programs, from Daniel Borkmann.
14) For loads, allow narrower accesses in bpf verifier checking, from
Yonghong Song.
15) Support MIPS in the BPF selftests and samples infrastructure, the
MIPS eBPF JIT will be merged in via the MIPS GIT tree. From David
Daney.
16) Support kernel based TLS, from Dave Watson and others.
17) Remove completely DST garbage collection, from Wei Wang.
18) Allow installing TCP MD5 rules using prefixes, from Ivan
Delalande.
19) Add XDP support to Intel i40e driver, from Björn Töpel
20) Add support for TC flower offload in nfp driver, from Simon
Horman, Pieter Jansen van Vuuren, Benjamin LaHaise, Jakub
Kicinski, and Bert van Leeuwen.
21) IPSEC offloading support in mlx5, from Ilan Tayari.
22) Add HW PTP support to macb driver, from Rafal Ozieblo.
23) Networking refcount_t conversions, From Elena Reshetova.
24) Add sock_ops support to BPF, from Lawrence Brako. This is useful
for tuning the TCP sockopt settings of a group of applications,
currently via CGROUPs"
* git://git.kernel.org/pub/scm/linux/kernel/git/davem/net-next: (1899 commits)
net: phy: dp83867: add workaround for incorrect RX_CTRL pin strap
dt-bindings: phy: dp83867: provide a workaround for incorrect RX_CTRL pin strap
cxgb4: Support for get_ts_info ethtool method
cxgb4: Add PTP Hardware Clock (PHC) support
cxgb4: time stamping interface for PTP
nfp: default to chained metadata prepend format
nfp: remove legacy MAC address lookup
nfp: improve order of interfaces in breakout mode
net: macb: remove extraneous return when MACB_EXT_DESC is defined
bpf: add missing break in for the TCP_BPF_SNDCWND_CLAMP case
bpf: fix return in load_bpf_file
mpls: fix rtm policy in mpls_getroute
net, ax25: convert ax25_cb.refcount from atomic_t to refcount_t
net, ax25: convert ax25_route.refcount from atomic_t to refcount_t
net, ax25: convert ax25_uid_assoc.refcount from atomic_t to refcount_t
net, sctp: convert sctp_ep_common.refcnt from atomic_t to refcount_t
net, sctp: convert sctp_transport.refcnt from atomic_t to refcount_t
net, sctp: convert sctp_chunk.refcnt from atomic_t to refcount_t
net, sctp: convert sctp_datamsg.refcnt from atomic_t to refcount_t
net, sctp: convert sctp_auth_bytes.refcnt from atomic_t to refcount_t
...
Linus Torvalds
commited |
5518b69b76 | |
The BPMP firmware, found on Tegra186 and later, provides an ABI that can be used to enable and disable power to several power partitions in Tegra SoCs. The ABI allows for enumeration of the available power partitions, so the driver can be reused on future generations, provided the BPMP ABI remains stable. Based on work by Stefan Kristiansson <stefank@nvidia.com> and Mikko Perttunen <mperttunen@nvidia.com>. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Ulf Hansson <ulf.hansson@linaro.org> Signed-off-by: Thierry Reding <treding@nvidia.com>
Thierry Reding
commited |
e7149a7a3f | |
Update the BPMP ABI header to a more recent version. The new version adds support for a new powergating ABI as well as access to the ring buffer console, which allows debug messages to be output to the BPMP debug console. Some of the previously undocumented fields have been documented and missing bitmasks have been added. Furthermore the MRQ_RESET request now has a sub-command that allows to determine the maximum ID which in turn allows the resets to be enumerated, thereby allowing drivers to become agnostic of the Tegra generation. Signed-off-by: Thierry Reding <treding@nvidia.com>
Thierry Reding
commited |
52b8b80395 | |
This adds support for hdlc-bus mode to the fsl_ucc_hdlc driver. This can be enabled with the "fsl,hdlc-bus" property in the DTS node of the corresponding ucc. This aligns the configuration of the UPSMR and GUMR registers to what is done in our ucc_hdlc driver (that only support hdlc-bus mode) and with the QuickEngine's documentation for hdlc-bus mode. GUMR/SYNL is set to AUTO for the busmode as in this case the CD signal is ignored. The brkpt_support is enabled to set the HBM1 bit in the CMXUCR register to configure an open-drain connected HDLC bus. Signed-off-by: Holger Brunck <holger.brunck@keymile.com> Cc: Zhao Qiang <qiang.zhao@nxp.com> Signed-off-by: David S. Miller <davem@davemloft.net> 
Holger Brunck
authored and
 David S. Miller
commited |
067bb938da | |
Add the bitmask for the two bit SYNL register according to the QUICK Engine Reference Manual. Signed-off-by: Holger Brunck <holger.brunck@keymile.com> Cc: Zhao Qiang <qiang.zhao@nxp.com> Signed-off-by: David S. Miller <davem@davemloft.net>
Holger Brunck
authored and
David S. Miller
commited |
c7f235a7c2 | |
Highlights include:
- rework the Linux page table geometry to lower memory usage on 64-bit Book3S
(IBM chips) using the Hash MMU.
- support for a new device tree binding for discovering CPU features on future
firmwares.
- Freescale updates from Scott: "Includes a fix for a powerpc/next mm regression
on 64e, a fix for a kernel hang on 64e when using a debugger inside a
relocated kernel, a qman fix, and misc qe improvements."
Thanks to:
Christophe Leroy, Gavin Shan, Horia Geantă, LiuHailong, Nicholas Piggin, Roy
Pledge, Scott Wood, Valentin Longchamp.
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1
iQIcBAABAgAGBQJZFXjPAAoJEFHr6jzI4aWAgG4QAJoF7G5Txj0Du2I2/wQDkVq1
InJ+BNji0xnOrFpz2EcIIlbIwBeJbY9cSIbmKUEPQU4hxtQgI8Q5WNEl2btWq8xz
I0Ej3uc5obc9ltUdQoGxgXih/XDd8UN3fscSE2/SSuPY/A7JwAVZMsCEJ1tWdxpM
hx+R9wlaUT3I6jmQwj9gg6zuBdIOL5szvZXKh9ruPKNyZWbPmPSUwIqiyT0YHsiD
01OZsFYpdSH6Ka/eNHSNx5HC+kK8aDVaqd5E2fkHeH9+sxerpEzMo2PmK4T8vChh
mSD4nhfqRwC2WRpPF/MY+zGBeXrFkCkR+nYhaqVDXXACKzfHgU58NOfvrmtRj52X
vTW+cn92wqFTmi0TNUfhEFt8elcOO7/fKh1OVhsFx+bD+bgj8G1ZkLoBU/0QUzRf
R4hiKKuOMnDHriNPdlAOKjHpR+ewh8Q679INThEJzEQpn7VBY72hcQwapQ3MjMnd
E7LfsGwqGPkTc6gy1bFbWum5HMGOcmE0qkrnZo5VyFhNNwBs1Kx/B1GHjUOiucVu
km5GEVNTfCkZqeabdca7fwbGcMH7zchR1ootqH2m18PZJAzr85A+aTqfrdJ5fDBs
v/nznfcPVNEgvEW0im2jhpPoAlQE6/YvYa+kG4zjjxWA5FKVKdTzINexD82jlcqP
+fDtIDxNcFkzlt4gacjh
=YOQs
-----END PGP SIGNATURE-----
Merge tag 'powerpc-4.12-2' of git://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux
Pull more powerpc updates from Michael Ellerman:
"The change to the Linux page table geometry was delayed for more
testing with 16G pages, and there's the new CPU features stuff which
just needed one more polish before going in. Plus a few changes from
Scott which came in a bit late. And then various fixes, mostly minor.
Summary highlights:
- rework the Linux page table geometry to lower memory usage on
64-bit Book3S (IBM chips) using the Hash MMU.
- support for a new device tree binding for discovering CPU features
on future firmwares.
- Freescale updates from Scott:
"Includes a fix for a powerpc/next mm regression on 64e, a fix for
a kernel hang on 64e when using a debugger inside a relocated
kernel, a qman fix, and misc qe improvements."
Thanks to: Christophe Leroy, Gavin Shan, Horia Geantă, LiuHailong,
Nicholas Piggin, Roy Pledge, Scott Wood, Valentin Longchamp"
* tag 'powerpc-4.12-2' of git://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux:
powerpc/64s: Support new device tree binding for discovering CPU features
powerpc: Don't print cpu_spec->cpu_name if it's NULL
of/fdt: introduce of_scan_flat_dt_subnodes and of_get_flat_dt_phandle
powerpc/64s: Fix unnecessary machine check handler relocation branch
powerpc/mm/book3s/64: Rework page table geometry for lower memory usage
powerpc: Fix distclean with Makefile.postlink
powerpc/64e: Don't place the stack beyond TASK_SIZE
powerpc/powernv: Block PCI config access on BCM5718 during EEH recovery
powerpc/8xx: Adding support of IRQ in MPC8xx GPIO
soc/fsl/qbman: Disable IRQs for deferred QBMan work
soc/fsl/qe: add EXPORT_SYMBOL for the 2 qe_tdm functions
soc/fsl/qe: only apply QE_General4 workaround on affected SoCs
soc/fsl/qe: round brg_freq to 1kHz granularity
soc/fsl/qe: get rid of immrbar_virt_to_phys()
net: ethernet: ucc_geth: fix MEM_PART_MURAM mode
powerpc/64e: Fix hang when debugging programs with relocated kernel
Linus Torvalds
commited |
dc2a248166 | |
Driver updates for ARM SoCs. * Reset subsystem, merged through arm-soc by tradition: - Make bool drivers explicitly non-modular - New support for i.MX7 and Arria10 reset controllers * PATA driver for Palmchip BK371 (acked by Tejun) * Power domain drivers for i.MX (GPC, GPCv2) - Moved out of mach-imx for GPC - Bunch of tweaks, fixes, etc * PMC support for Tegra186 * SoC detection support for Renesas RZ/G1H and RZ/G1N * Move Tegra flow controller driver from mach directory to drivers/soc - (Power management / CPU power driver) * Misc smaller tweaks for other platforms -----BEGIN PGP SIGNATURE----- Version: GnuPG v1 iQIcBAABAgAGBQJZEAZuAAoJEIwa5zzehBx3jCEP/1dcXY746rQoOMUDPyWF5+SZ w0l8dHUQhu4WjNGryfb9DbyiE3d6xlvPVzr9AJeAg6c5I+iikgeogS0XHNpWCU96 FR1Ftb6zo8DIaGognBL9bK5HM7NXjd/EKBkMk0Ggs9/NRFUnakkbpdfivsl2BACx mCGo15+kbgQSQsMJtd5/KfsgY5h7lXJG0fZ8LV5E1E5BSa/AofZtKVgCKfhbd0zV gQqm7xfxtURHtucc7MYNEoKNk5rlrZhOlG6DdG0d6+rscCBrmL1I5giqm8y24+wW z+JJuk21+oVtltLz09JuX51xur3CGyJ+qNJdRPE1P1Udn7wj5zA+ew9qqJi1cgNf 63tBxooBpH6R8dGcOfjKECD6lBBqBr/Dd8ReWbMyn0XF1HMAxgpfPtExu9WcDzGu 9Fr/shUiEA3jqhbzSy6DCHugpnHPdHPyY64MqzisgOEVsituQ7MSefTIGSNusDlk K36I7j93mDAF5y2fTXqbjZKoRuu6KCySvGDXzBqGwhcNzUQk14iPwjtMDZ/l9Raj sQJCUxHntUovHs+VTCwS7ahqZyn0VRNx2bt1aJXNHKzuUovpA9/X5X9HCRZJDovB 0bCGQZ124+H/VsWvSjVtIh7oknU3vSQJPxS6KLKoi3rvywuqW562lGjCTqvjBJKD FMZ5NA8VoWXM2rgTDOyx =B43K -----END PGP SIGNATURE----- Merge tag 'armsoc-drivers' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc Pull ARM SoC driver updates from Olof Johansson: "Driver updates for ARM SoCs: Reset subsystem, merged through arm-soc by tradition: - Make bool drivers explicitly non-modular - New support for i.MX7 and Arria10 reset controllers PATA driver for Palmchip BK371 (acked by Tejun) Power domain drivers for i.MX (GPC, GPCv2) - Moved out of mach-imx for GPC - Bunch of tweaks, fixes, etc PMC support for Tegra186 SoC detection support for Renesas RZ/G1H and RZ/G1N Move Tegra flow controller driver from mach directory to drivers/soc - (Power management / CPU power driver) Misc smaller tweaks for other platforms" * tag 'armsoc-drivers' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (60 commits) soc: pm-domain: Fix the mangled urls soc: renesas: rcar-sysc: Add support for R-Car H3 ES2.0 soc: renesas: rcar-sysc: Add support for fixing up power area tables soc: renesas: Register SoC device early soc: imx: gpc: add workaround for i.MX6QP to the GPC PD driver dt-bindings: imx-gpc: add i.MX6 QuadPlus compatible soc: imx: gpc: add defines for domain index soc: imx: Add GPCv2 power gating driver dt-bindings: Add GPCv2 power gating driver ARM/clk: move the ICST library to drivers/clk ARM: plat-versatile: remove stale clock header ARM: keystone: Drop PM domain support for k2g soc: ti: Add ti_sci_pm_domains driver dt-bindings: Add TI SCI PM Domains PM / Domains: Do not check if simple providers have phandle cells PM / Domains: Add generic data pointer to genpd data struct soc/tegra: Add initial flowctrl support for Tegra132/210 soc/tegra: flowctrl: Add basic platform driver soc/tegra: Move Tegra flowctrl driver ARM: tegra: Remove unnecessary inclusion of flowctrl header ...
Linus Torvalds
commited |
0160e00ae8 |