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ARM: SoC: late updates

Browse source 
This is a branch with a few merge requests that either came in late, or
 took a while longer for us to review and merge than usual and thus cut
 it a bit close to the merge window. We stage them in a separate branch
 and if things look good, we still send them up -- and that's the case
 here.
 
 This is mostly DT additions for Renesas platforms, adding IP block
 descriptions for existing and new SoCs.
 
 There are also some driver updates for Qualcomm platforms for SMEM/QMI
 and GENI, which is their generalized serial protocol interface.
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Merge tag 'armsoc-late' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc

Pull ARM SoC late updates from Olof Johansson:
 "This is a branch with a few merge requests that either came in late,
  or took a while longer for us to review and merge than usual and thus
  cut it a bit close to the merge window. We stage them in a separate
  branch and if things look good, we still send them up -- and that's
  the case here.

  This is mostly DT additions for Renesas platforms, adding IP block
  descriptions for existing and new SoCs.

  There are also some driver updates for Qualcomm platforms for SMEM/QMI
  and GENI, which is their generalized serial protocol interface"

* tag 'armsoc-late' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (186 commits)
  soc: qcom: smem: introduce qcom_smem_virt_to_phys()
  soc: qcom: qmi: fix a buffer sizing bug
  MAINTAINERS: Update pattern for qcom_scm
  soc: Unconditionally include qcom Makefile
  soc: qcom: smem: check sooner in qcom_smem_set_global_partition()
  soc: qcom: smem: fix qcom_smem_set_global_partition()
  soc: qcom: smem: fix off-by-one error in qcom_smem_alloc_private()
  soc: qcom: smem: byte swap values properly
  soc: qcom: smem: return proper type for cached entry functions
  soc: qcom: smem: fix first cache entry calculation
  soc: qcom: cmd-db: Make endian-agnostic
  drivers: qcom: add command DB driver
  arm64: dts: renesas: salvator-common: Add ADV7482 support
  ARM: dts: r8a7740: Add CEU1
  ARM: dts: r8a7740: Add CEU0
  arm64: dts: renesas: salvator-common: enable VIN
  arm64: dts: renesas: r8a77970: add VIN and CSI-2 nodes
  arm64: dts: renesas: r8a77965: add VIN and CSI-2 nodes
  arm64: dts: renesas: r8a7796: add VIN and CSI-2 nodes
  arm64: dts: renesas: r8a7795-es1: add CSI-2 node
  ...
This commit is contained in:
Linus Torvalds 2018-06-11 18:19:45 -07:00
commit 8efcf34a26
68 changed files with 9184 additions and 3650 deletions
Download patch file Download diff file Expand all files Collapse all files

3
Documentation/devicetree/bindings/firmware/qcom,scm.txt
View file

@ -11,9 +11,10 @@ Required properties:
* "qcom,scm-msm8660" for MSM8660 platforms
* "qcom,scm-msm8690" for MSM8690 platforms
* "qcom,scm-msm8996" for MSM8996 platforms
* "qcom,scm-ipq4019" for IPQ4019 platforms
* "qcom,scm" for later processors (MSM8916, APQ8084, MSM8974, etc)
- clocks: One to three clocks may be required based on compatible.
* No clock required for "qcom,scm-msm8996"
* No clock required for "qcom,scm-msm8996", "qcom,scm-ipq4019"
* Only core clock required for "qcom,scm-apq8064", "qcom,scm-msm8660", and "qcom,scm-msm8960"
* Core, iface, and bus clocks required for "qcom,scm"
- clock-names: Must contain "core" for the core clock, "iface" for the interface

1
Documentation/devicetree/bindings/soc/qcom/qcom,smd-rpm.txt
View file

@ -22,6 +22,7 @@ resources.
"qcom,rpm-apq8084"
"qcom,rpm-msm8916"
"qcom,rpm-msm8974"
"qcom,rpm-msm8998"
- qcom,smd-channels:
Usage: required

2
MAINTAINERS
View file

@ -1830,7 +1830,7 @@ F: drivers/spi/spi-qup.c
F: drivers/tty/serial/msm_serial.c
F: drivers/*/pm8???-*
F: drivers/mfd/ssbi.c
F: drivers/firmware/qcom_scm.c
F: drivers/firmware/qcom_scm*
T: git git://git.kernel.org/pub/scm/linux/kernel/git/agross/linux.git
ARM/RADISYS ENP2611 MACHINE SUPPORT

1
arch/arm/boot/dts/Makefile
View file

@ -807,6 +807,7 @@ dtb-$(CONFIG_ARCH_RENESAS) += \
r8a7745-iwg22d-sodimm.dtb \
r8a7745-iwg22d-sodimm-dbhd-ca.dtb \
r8a7745-sk-rzg1e.dtb \
r8a77470-iwg23s-sbc.dtb \
r8a7778-bockw.dtb \
r8a7779-marzen.dtb \
r8a7790-lager.dtb \

3
arch/arm/boot/dts/emev2-kzm9d.dts
View file

@ -34,9 +34,6 @@
gpio_keys {
compatible = "gpio-keys";
#address-cells = <1>;
#size-cells = <0>;
one {
debounce-interval = <50>;
wakeup-source;

5
arch/arm/boot/dts/emev2.dtsi
View file

@ -31,13 +31,13 @@
#address-cells = <1>;
#size-cells = <0>;
cpu@0 {
cpu0: cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a9";
reg = <0>;
clock-frequency = <533000000>;
};
cpu@1 {
cpu1: cpu@1 {
device_type = "cpu";
compatible = "arm,cortex-a9";
reg = <1>;
@ -57,6 +57,7 @@
compatible = "arm,cortex-a9-pmu";
interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
interrupt-affinity = <&cpu0>, <&cpu1>;
};
clocks@e0110000 {

1068
arch/arm/boot/dts/r7s72100.dtsi
View file

File diff suppressed because it is too large Load diff

4
arch/arm/boot/dts/r8a73a4-ape6evm.dts
View file

@ -234,7 +234,7 @@
&sdhi0 {
vmmc-supply = <&vcc_sdhi0>;
bus-width = <4>;
toshiba,mmc-wrprotect-disable;
disable-wp;
pinctrl-names = "default";
pinctrl-0 = <&sdhi0_pins>;
status = "okay";
@ -244,7 +244,7 @@
vmmc-supply = <&ape6evm_fixed_3v3>;
bus-width = <4>;
broken-cd;
toshiba,mmc-wrprotect-disable;
disable-wp;
pinctrl-names = "default";
pinctrl-0 = <&sdhi1_pins>;
status = "okay";

10
arch/arm/boot/dts/r8a73a4.dtsi
View file

@ -57,10 +57,10 @@
timer {
compatible = "arm,armv7-timer";
interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
};
dbsc1: memory-controller@e6790000 {
@ -464,7 +464,7 @@
<0 0xf1002000 0 0x2000>,
<0 0xf1004000 0 0x2000>,
<0 0xf1006000 0 0x2000>;
interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
clocks = <&mstp4_clks R8A73A4_CLK_INTC_SYS>;
clock-names = "clk";
power-domains = <&pd_c4>;

18
arch/arm/boot/dts/r8a7740.dtsi
View file

@ -67,6 +67,24 @@
power-domains = <&pd_d4>;
};
ceu0: ceu@fe910000 {
reg = <0xfe910000 0x3000>;
compatible = "renesas,r8a7740-ceu";
interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp1_clks R8A7740_CLK_CEU20>;
power-domains = <&pd_a4r>;
status = "disabled";
};
ceu1: ceu@fe914000 {
reg = <0xfe914000 0x3000>;
compatible = "renesas,r8a7740-ceu";
interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp1_clks R8A7740_CLK_CEU21>;
power-domains = <&pd_a4r>;
status = "disabled";
};
cmt1: timer@e6138000 {
compatible = "renesas,cmt-48-r8a7740", "renesas,cmt-48";
reg = <0xe6138000 0x170>;

5
arch/arm/boot/dts/r8a7743-iwg20m.dtsi
View file

@ -91,6 +91,11 @@
};
};
&rwdt {
timeout-sec = <60>;
status = "okay";
};
&sdhi0 {
pinctrl-0 = <&sdhi0_pins>;
pinctrl-names = "default";

19
arch/arm/boot/dts/r8a7743.dtsi
View file

@ -125,6 +125,13 @@
clock-frequency = <0>;
};
pmu {
compatible = "arm,cortex-a15-pmu";
interrupts-extended = <&gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
<&gic GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
interrupt-affinity = <&cpu0>, <&cpu1>;
};
/* External SCIF clock */
scif_clk: scif {
compatible = "fixed-clock";
@ -297,6 +304,16 @@
reg = <0 0xe6160000 0 0x100>;
};
rwdt: watchdog@e6020000 {
compatible = "renesas,r8a7743-wdt",
"renesas,rcar-gen2-wdt";
reg = <0 0xe6020000 0 0x0c>;
clocks = <&cpg CPG_MOD 402>;
power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
resets = <&cpg 402>;
status = "disabled";
};
sysc: system-controller@e6180000 {
compatible = "renesas,r8a7743-sysc";
reg = <0 0xe6180000 0 0x200>;
@ -407,7 +424,7 @@
smp-sram@0 {
compatible = "renesas,smp-sram";
reg = <0 0x10>;
reg = <0 0x100>;
};
};

5
arch/arm/boot/dts/r8a7745-iwg22m.dtsi
View file

@ -91,6 +91,11 @@
};
};
&rwdt {
timeout-sec = <60>;
status = "okay";
};
&sdhi1 {
pinctrl-0 = <&sdhi1_pins>;
pinctrl-names = "default";

19
arch/arm/boot/dts/r8a7745.dtsi
View file

@ -105,6 +105,13 @@
clock-frequency = <0>;
};
pmu {
compatible = "arm,cortex-a7-pmu";
interrupts-extended = <&gic GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>,
<&gic GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
interrupt-affinity = <&cpu0>, <&cpu1>;
};
/* External SCIF clock */
scif_clk: scif {
compatible = "fixed-clock";
@ -262,6 +269,16 @@
reg = <0 0xe6160000 0 0x100>;
};
rwdt: watchdog@e6020000 {
compatible = "renesas,r8a7745-wdt",
"renesas,rcar-gen2-wdt";
reg = <0 0xe6020000 0 0x0c>;
clocks = <&cpg CPG_MOD 402>;
power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
resets = <&cpg 402>;
status = "disabled";
};
sysc: system-controller@e6180000 {
compatible = "renesas,r8a7745-sysc";
reg = <0 0xe6180000 0 0x200>;
@ -360,7 +377,7 @@
smp-sram@0 {
compatible = "renesas,smp-sram";
reg = <0 0x10>;
reg = <0 0x100>;
};
};

48
arch/arm/boot/dts/r8a77470-iwg23s-sbc.dts Normal file
View file

@ -0,0 +1,48 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Device Tree Source for the iWave-RZ/G1C single board computer
*
* Copyright (C) 2018 Renesas Electronics Corp.
*/
/dts-v1/;
#include "r8a77470.dtsi"
/ {
model = "iWave iW-RainboW-G23S single board computer based on RZ/G1C";
compatible = "iwave,g23s", "renesas,r8a77470";
aliases {
ethernet0 = &avb;
serial1 = &scif1;
};
chosen {
bootargs = "ignore_loglevel rw root=/dev/nfs ip=dhcp";
stdout-path = "serial1:115200n8";
};
memory@40000000 {
device_type = "memory";
reg = <0 0x40000000 0 0x20000000>;
};
};
&avb {
phy-handle = <&phy3>;
phy-mode = "gmii";
renesas,no-ether-link;
status = "okay";
phy3: ethernet-phy@3 {
reg = <3>;
micrel,led-mode = <1>;
};
};
&extal_clk {
clock-frequency = <20000000>;
};
&scif1 {
status = "okay";
};

336
arch/arm/boot/dts/r8a77470.dtsi Normal file
View file

@ -0,0 +1,336 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Device Tree Source for the r8a77470 SoC
*
* Copyright (C) 2018 Renesas Electronics Corp.
*/
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/clock/renesas-cpg-mssr.h>
/ {
compatible = "renesas,r8a77470";
#address-cells = <2>;
#size-cells = <2>;
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu0: cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a7";
reg = <0>;
clock-frequency = <1000000000>;
clocks = <&cpg CPG_CORE 0>;
power-domains = <&sysc 5>;
next-level-cache = <&L2_CA7>;
};
L2_CA7: cache-controller-0 {
compatible = "cache";
cache-unified;
cache-level = <2>;
power-domains = <&sysc 21>;
};
};
/* External root clock */
extal_clk: extal {
compatible = "fixed-clock";
#clock-cells = <0>;
/* This value must be overridden by the board. */
clock-frequency = <0>;
};
/* External SCIF clock */
scif_clk: scif {
compatible = "fixed-clock";
#clock-cells = <0>;
/* This value must be overridden by the board. */
clock-frequency = <0>;
};
soc {
compatible = "simple-bus";
interrupt-parent = <&gic>;
#address-cells = <2>;
#size-cells = <2>;
ranges;
cpg: clock-controller@e6150000 {
compatible = "renesas,r8a77470-cpg-mssr";
reg = <0 0xe6150000 0 0x1000>;
clocks = <&extal_clk>, <&usb_extal_clk>;
clock-names = "extal", "usb_extal";
#clock-cells = <2>;
#power-domain-cells = <0>;
#reset-cells = <1>;
};
rst: reset-controller@e6160000 {
compatible = "renesas,r8a77470-rst";
reg = <0 0xe6160000 0 0x100>;
};
sysc: system-controller@e6180000 {
compatible = "renesas,r8a77470-sysc";
reg = <0 0xe6180000 0 0x200>;
#power-domain-cells = <1>;
};
irqc: interrupt-controller@e61c0000 {
compatible = "renesas,irqc-r8a77470", "renesas,irqc";
#interrupt-cells = <2>;
interrupt-controller;
reg = <0 0xe61c0000 0 0x200>;
interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 407>;
power-domains = <&sysc 32>;
resets = <&cpg 407>;
};
icram0: sram@e63a0000 {
compatible = "mmio-sram";
reg = <0 0xe63a0000 0 0x12000>;
};
icram1: sram@e63c0000 {
compatible = "mmio-sram";
reg = <0 0xe63c0000 0 0x1000>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0 0xe63c0000 0x1000>;
smp-sram@0 {
compatible = "renesas,smp-sram";
reg = <0 0x100>;
};
};
icram2: sram@e6300000 {
compatible = "mmio-sram";
reg = <0 0xe6300000 0 0x20000>;
};
dmac0: dma-controller@e6700000 {
compatible = "renesas,dmac-r8a77470",
"renesas,rcar-dmac";
reg = <0 0xe6700000 0 0x20000>;
interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "error",
"ch0", "ch1", "ch2", "ch3",
"ch4", "ch5", "ch6", "ch7",
"ch8", "ch9", "ch10", "ch11",
"ch12", "ch13", "ch14";
clocks = <&cpg CPG_MOD 219>;
clock-names = "fck";
power-domains = <&sysc 32>;
resets = <&cpg 219>;
#dma-cells = <1>;
dma-channels = <15>;
};
dmac1: dma-controller@e6720000 {
compatible = "renesas,dmac-r8a77470",
"renesas,rcar-dmac";
reg = <0 0xe6720000 0 0x20000>;
interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "error",
"ch0", "ch1", "ch2", "ch3",
"ch4", "ch5", "ch6", "ch7",
"ch8", "ch9", "ch10", "ch11",
"ch12", "ch13", "ch14";
clocks = <&cpg CPG_MOD 218>;
clock-names = "fck";
power-domains = <&sysc 32>;
resets = <&cpg 218>;
#dma-cells = <1>;
dma-channels = <15>;
};
avb: ethernet@e6800000 {
compatible = "renesas,etheravb-r8a77470",
"renesas,etheravb-rcar-gen2";
reg = <0 0xe6800000 0 0x800>, <0 0xee0e8000 0 0x4000>;
interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 812>;
power-domains = <&sysc 32>;
resets = <&cpg 812>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
scif0: serial@e6e60000 {
compatible = "renesas,scif-r8a77470",
"renesas,rcar-gen2-scif", "renesas,scif";
reg = <0 0xe6e60000 0 0x40>;
interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 721>,
<&cpg CPG_CORE 5>, <&scif_clk>;
clock-names = "fck", "brg_int", "scif_clk";
dmas = <&dmac0 0x29>, <&dmac0 0x2a>,
<&dmac1 0x29>, <&dmac1 0x2a>;
dma-names = "tx", "rx", "tx", "rx";
power-domains = <&sysc 32>;
resets = <&cpg 721>;
status = "disabled";
};
scif1: serial@e6e68000 {
compatible = "renesas,scif-r8a77470",
"renesas,rcar-gen2-scif", "renesas,scif";
reg = <0 0xe6e68000 0 0x40>;
interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 720>,
<&cpg CPG_CORE 5>, <&scif_clk>;
clock-names = "fck", "brg_int", "scif_clk";
dmas = <&dmac0 0x2d>, <&dmac0 0x2e>,
<&dmac1 0x2d>, <&dmac1 0x2e>;
dma-names = "tx", "rx", "tx", "rx";
power-domains = <&sysc 32>;
resets = <&cpg 720>;
status = "disabled";
};
scif2: serial@e6e58000 {
compatible = "renesas,scif-r8a77470",
"renesas,rcar-gen2-scif", "renesas,scif";
reg = <0 0xe6e58000 0 0x40>;
interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 719>,
<&cpg CPG_CORE 5>, <&scif_clk>;
clock-names = "fck", "brg_int", "scif_clk";
dmas = <&dmac0 0x2b>, <&dmac0 0x2c>,
<&dmac1 0x2b>, <&dmac1 0x2c>;
dma-names = "tx", "rx", "tx", "rx";
power-domains = <&sysc 32>;
resets = <&cpg 719>;
status = "disabled";
};
scif3: serial@e6ea8000 {
compatible = "renesas,scif-r8a77470",
"renesas,rcar-gen2-scif", "renesas,scif";
reg = <0 0xe6ea8000 0 0x40>;
interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 718>,
<&cpg CPG_CORE 5>, <&scif_clk>;
clock-names = "fck", "brg_int", "scif_clk";
dmas = <&dmac0 0x2f>, <&dmac0 0x30>,
<&dmac1 0x2f>, <&dmac1 0x30>;
dma-names = "tx", "rx", "tx", "rx";
power-domains = <&sysc 32>;
resets = <&cpg 718>;
status = "disabled";
};
scif4: serial@e6ee0000 {
compatible = "renesas,scif-r8a77470",
"renesas,rcar-gen2-scif", "renesas,scif";
reg = <0 0xe6ee0000 0 0x40>;
interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 715>,
<&cpg CPG_CORE 5>, <&scif_clk>;
clock-names = "fck", "brg_int", "scif_clk";
dmas = <&dmac0 0xfb>, <&dmac0 0xfc>,
<&dmac1 0xfb>, <&dmac1 0xfc>;
dma-names = "tx", "rx", "tx", "rx";
power-domains = <&sysc 32>;
resets = <&cpg 715>;
status = "disabled";
};
scif5: serial@e6ee8000 {
compatible = "renesas,scif-r8a77470",
"renesas,rcar-gen2-scif", "renesas,scif";
reg = <0 0xe6ee8000 0 0x40>;
interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 714>,
<&cpg CPG_CORE 5>, <&scif_clk>;
clock-names = "fck", "brg_int", "scif_clk";
dmas = <&dmac0 0xfd>, <&dmac0 0xfe>,
<&dmac1 0xfd>, <&dmac1 0xfe>;
dma-names = "tx", "rx", "tx", "rx";
power-domains = <&sysc 32>;
resets = <&cpg 714>;
status = "disabled";
};
gic: interrupt-controller@f1001000 {
compatible = "arm,gic-400";
#interrupt-cells = <3>;
#address-cells = <0>;
interrupt-controller;
reg = <0 0xf1001000 0 0x1000>, <0 0xf1002000 0 0x2000>,
<0 0xf1004000 0 0x2000>, <0 0xf1006000 0 0x2000>;
interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
clocks = <&cpg CPG_MOD 408>;
clock-names = "clk";
power-domains = <&sysc 32>;
resets = <&cpg 408>;
};
prr: chipid@ff000044 {
compatible = "renesas,prr";
reg = <0 0xff000044 0 4>;
};
};
timer {
compatible = "arm,armv7-timer";
interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
<&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
<&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
<&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
};
/* External USB clock - can be overridden by the board */
usb_extal_clk: usb_extal {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <48000000>;
};
};

8
arch/arm/boot/dts/r8a7790-lager.dts
View file

@ -902,9 +902,6 @@
status = "okay";
port {
#address-cells = <1>;
#size-cells = <0>;
vin1ep0: endpoint {
remote-endpoint = <&adv7180>;
bus-width = <8>;
@ -929,6 +926,11 @@
};
};
&rwdt {
timeout-sec = <60>;
status = "okay";
};
&ssi1 {
shared-pin;
};

67
arch/arm/boot/dts/r8a7790.dtsi
View file

@ -202,6 +202,24 @@
clock-frequency = <0>;
};
pmu-0 {
compatible = "arm,cortex-a15-pmu";
interrupts-extended = <&gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
<&gic GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
<&gic GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>,
<&gic GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
};
pmu-1 {
compatible = "arm,cortex-a7-pmu";
interrupts-extended = <&gic GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>,
<&gic GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>,
<&gic GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>,
<&gic GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
interrupt-affinity = <&cpu4>, <&cpu5>, <&cpu6>, <&cpu7>;
};
/* External SCIF clock */
scif_clk: scif {
compatible = "fixed-clock";
@ -218,6 +236,16 @@
#size-cells = <2>;
ranges;
rwdt: watchdog@e6020000 {
compatible = "renesas,r8a7790-wdt",
"renesas,rcar-gen2-wdt";
reg = <0 0xe6020000 0 0x0c>;
clocks = <&cpg CPG_MOD 402>;
power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
resets = <&cpg 402>;
status = "disabled";
};
gpio0: gpio@e6050000 {
compatible = "renesas,gpio-r8a7790",
"renesas,rcar-gen2-gpio";
@ -443,7 +471,7 @@
smp-sram@0 {
compatible = "renesas,smp-sram";
reg = <0 0x10>;
reg = <0 0x100>;
};
};
@ -1544,7 +1572,7 @@
interrupt-controller;
reg = <0 0xf1001000 0 0x1000>, <0 0xf1002000 0 0x2000>,
<0 0xf1004000 0 0x2000>, <0 0xf1006000 0 0x2000>;
interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
clocks = <&cpg CPG_MOD 408>;
clock-names = "clk";
power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
@ -1615,6 +1643,33 @@
resets = <&cpg 127>;
};
fdp1@fe940000 {
compatible = "renesas,fdp1";
reg = <0 0xfe940000 0 0x2400>;
interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 119>;
power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
resets = <&cpg 119>;
};
fdp1@fe944000 {
compatible = "renesas,fdp1";
reg = <0 0xfe944000 0 0x2400>;
interrupts = <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 118>;
power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
resets = <&cpg 118>;
};
fdp1@fe948000 {
compatible = "renesas,fdp1";
reg = <0 0xfe948000 0 0x2400>;
interrupts = <GIC_SPI 264 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 117>;
power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
resets = <&cpg 117>;
};
jpu: jpeg-codec@fe980000 {
compatible = "renesas,jpu-r8a7790",
"renesas,rcar-gen2-jpu";
@ -1773,10 +1828,10 @@
timer {
compatible = "arm,armv7-timer";
interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
<&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
<&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
<&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
<&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
<&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
<&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
};
/* External USB clock - can be overridden by the board */

11
arch/arm/boot/dts/r8a7791-koelsch.dts
View file

@ -643,6 +643,11 @@
status = "okay";
};
&rwdt {
timeout-sec = <60>;
status = "okay";
};
&sata0 {
status = "okay";
};
@ -850,9 +855,6 @@
pinctrl-names = "default";
port {
#address-cells = <1>;
#size-cells = <0>;
vin0ep2: endpoint {
remote-endpoint = <&adv7612_out>;
bus-width = <24>;
@ -871,9 +873,6 @@
pinctrl-names = "default";
port {
#address-cells = <1>;
#size-cells = <0>;
vin1ep: endpoint {
remote-endpoint = <&adv7180>;
bus-width = <8>;

8
arch/arm/boot/dts/r8a7791-porter.dts
View file

@ -386,9 +386,6 @@
pinctrl-names = "default";
port {
#address-cells = <1>;
#size-cells = <0>;
vin0ep: endpoint {
remote-endpoint = <&adv7180>;
bus-width = <8>;
@ -481,6 +478,11 @@
};
};
&rwdt {
timeout-sec = <60>;
status = "okay";
};
&ssi1 {
shared-pin;
};

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