mirror of
https://github.com/a52xq-dev/kernel.git
synced 2026-10-18 21:58:11 +07:00
Merge branch 'for-linus' of git://ftp.arm.linux.org.uk/~rmk/linux-arm
Pull ARM development updates from Russell King:
"Included in this update:
- moving PSCI code from ARM64/ARM to drivers/
- removal of some architecture internals from global kernel view
- addition of software based "privileged no access" support using the
old domains register to turn off the ability for kernel
loads/stores to access userspace. Only the proper accessors will
be usable.
- addition of early fixup support for early console
- re-addition (and reimplementation) of OMAP special interconnect
barrier
- removal of finish_arch_switch()
- only expose cpuX/online in sysfs if hotpluggable
- a number of code cleanups"
* 'for-linus' of git://ftp.arm.linux.org.uk/~rmk/linux-arm: (41 commits)
ARM: software-based priviledged-no-access support
ARM: entry: provide uaccess assembly macro hooks
ARM: entry: get rid of multiple macro definitions
ARM: 8421/1: smp: Collapse arch_cpu_idle_dead() into cpu_die()
ARM: uaccess: provide uaccess_save_and_enable() and uaccess_restore()
ARM: mm: improve do_ldrd_abort macro
ARM: entry: ensure that IRQs are enabled when calling syscall_trace_exit()
ARM: entry: efficiency cleanups
ARM: entry: get rid of asm_trace_hardirqs_on_cond
ARM: uaccess: simplify user access assembly
ARM: domains: remove DOMAIN_TABLE
ARM: domains: keep vectors in separate domain
ARM: domains: get rid of manager mode for user domain
ARM: domains: move initial domain setting value to asm/domains.h
ARM: domains: provide domain_mask()
ARM: domains: switch to keeping domain value in register
ARM: 8419/1: dma-mapping: harmonize definition of DMA_ERROR_CODE
ARM: 8417/1: refactor bitops functions with BIT_MASK() and BIT_WORD()
ARM: 8416/1: Feroceon: use of_iomap() to map register base
ARM: 8415/1: early fixmap support for earlycon
...
This commit is contained in:
Linus Torvalds
commit
c706c7eb0d
96 changed files with 1457 additions and 1114 deletions
|
|
@ -67,6 +67,12 @@ Optional properties:
|
|||
disable if zero.
|
||||
- arm,prefetch-offset : Override prefetch offset value. Valid values are
|
||||
0-7, 15, 23, and 31.
|
||||
- arm,shared-override : The default behavior of the pl310 cache controller with
|
||||
respect to the shareable attribute is to transform "normal memory
|
||||
non-cacheable transactions" into "cacheable no allocate" (for reads) or
|
||||
"write through no write allocate" (for writes).
|
||||
On systems where this may cause DMA buffer corruption, this property must be
|
||||
specified to indicate that such transforms are precluded.
|
||||
- prefetch-data : Data prefetch. Value: <0> (forcibly disable), <1>
|
||||
(forcibly enable), property absent (retain settings set by firmware)
|
||||
- prefetch-instr : Instruction prefetch. Value: <0> (forcibly disable),
|
||||
|
|
|
|||
|
|
@ -26,13 +26,19 @@ Required properties:
|
|||
|
||||
Optional properties:
|
||||
|
||||
- interrupt-affinity : Valid only when using SPIs, specifies a list of phandles
|
||||
to CPU nodes corresponding directly to the affinity of
|
||||
- interrupt-affinity : When using SPIs, specifies a list of phandles to CPU
|
||||
nodes corresponding directly to the affinity of
|
||||
the SPIs listed in the interrupts property.
|
||||
|
||||
This property should be present when there is more than
|
||||
When using a PPI, specifies a list of phandles to CPU
|
||||
nodes corresponding to the set of CPUs which have
|
||||
a PMU of this type signalling the PPI listed in the
|
||||
interrupts property.
|
||||
|
||||
This property should be present when there is more than
|
||||
a single SPI.
|
||||
|
||||
|
||||
- qcom,no-pc-write : Indicates that this PMU doesn't support the 0xc and 0xd
|
||||
events.
|
||||
|
||||
|
|
|
|||
15
MAINTAINERS
15
MAINTAINERS
|
|
@ -806,11 +806,13 @@ F: arch/arm/include/asm/floppy.h
|
|||
ARM PMU PROFILING AND DEBUGGING
|
||||
M: Will Deacon <will.deacon@arm.com>
|
||||
S: Maintained
|
||||
F: arch/arm/kernel/perf_event*
|
||||
F: arch/arm/kernel/perf_*
|
||||
F: arch/arm/oprofile/common.c
|
||||
F: arch/arm/include/asm/pmu.h
|
||||
F: arch/arm/kernel/hw_breakpoint.c
|
||||
F: arch/arm/include/asm/hw_breakpoint.h
|
||||
F: arch/arm/include/asm/perf_event.h
|
||||
F: drivers/perf/arm_pmu.c
|
||||
F: include/linux/perf/arm_pmu.h
|
||||
|
||||
ARM PORT
|
||||
M: Russell King <linux@arm.linux.org.uk>
|
||||
|
|
@ -8120,6 +8122,15 @@ F: include/linux/power_supply.h
|
|||
F: drivers/power/
|
||||
X: drivers/power/avs/
|
||||
|
||||
POWER STATE COORDINATION INTERFACE (PSCI)
|
||||
M: Mark Rutland <mark.rutland@arm.com>
|
||||
M: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
|
||||
L: linux-arm-kernel@lists.infradead.org
|
||||
S: Maintained
|
||||
F: drivers/firmware/psci.c
|
||||
F: include/linux/psci.h
|
||||
F: include/uapi/linux/psci.h
|
||||
|
||||
PNP SUPPORT
|
||||
M: "Rafael J. Wysocki" <rafael.j.wysocki@intel.com>
|
||||
S: Maintained
|
||||
|
|
|
|||
|
|
@ -188,6 +188,9 @@ config ARCH_HAS_ILOG2_U64
|
|||
config ARCH_HAS_BANDGAP
|
||||
bool
|
||||
|
||||
config FIX_EARLYCON_MEM
|
||||
def_bool y if MMU
|
||||
|
||||
config GENERIC_HWEIGHT
|
||||
bool
|
||||
default y
|
||||
|
|
@ -1496,6 +1499,7 @@ config HOTPLUG_CPU
|
|||
config ARM_PSCI
|
||||
bool "Support for the ARM Power State Coordination Interface (PSCI)"
|
||||
depends on CPU_V7
|
||||
select ARM_PSCI_FW
|
||||
help
|
||||
Say Y here if you want Linux to communicate with system firmware
|
||||
implementing the PSCI specification for CPU-centric power
|
||||
|
|
@ -1700,13 +1704,24 @@ config HIGHPTE
|
|||
consumed by page tables. Setting this option will allow
|
||||
user-space 2nd level page tables to reside in high memory.
|
||||
|
||||
config HW_PERF_EVENTS
|
||||
bool "Enable hardware performance counter support for perf events"
|
||||
depends on PERF_EVENTS
|
||||
config CPU_SW_DOMAIN_PAN
|
||||
bool "Enable use of CPU domains to implement privileged no-access"
|
||||
depends on MMU && !ARM_LPAE
|
||||
default y
|
||||
help
|
||||
Enable hardware performance counter support for perf events. If
|
||||
disabled, perf events will use software events only.
|
||||
Increase kernel security by ensuring that normal kernel accesses
|
||||
are unable to access userspace addresses. This can help prevent
|
||||
use-after-free bugs becoming an exploitable privilege escalation
|
||||
by ensuring that magic values (such as LIST_POISON) will always
|
||||
fault when dereferenced.
|
||||
|
||||
CPUs with low-vector mappings use a best-efforts implementation.
|
||||
Their lower 1MB needs to remain accessible for the vectors, but
|
||||
the remainder of userspace will become appropriately inaccessible.
|
||||
|
||||
config HW_PERF_EVENTS
|
||||
def_bool y
|
||||
depends on ARM_PMU
|
||||
|
||||
config SYS_SUPPORTS_HUGETLBFS
|
||||
def_bool y
|
||||
|
|
|
|||
|
|
@ -65,14 +65,10 @@ static int mcpm_cpu_kill(unsigned int cpu)
|
|||
return !mcpm_wait_for_cpu_powerdown(pcpu, pcluster);
|
||||
}
|
||||
|
||||
static int mcpm_cpu_disable(unsigned int cpu)
|
||||
static bool mcpm_cpu_can_disable(unsigned int cpu)
|
||||
{
|
||||
/*
|
||||
* We assume all CPUs may be shut down.
|
||||
* This would be the hook to use for eventual Secure
|
||||
* OS migration requests as described in the PSCI spec.
|
||||
*/
|
||||
return 0;
|
||||
/* We assume all CPUs may be shut down. */
|
||||
return true;
|
||||
}
|
||||
|
||||
static void mcpm_cpu_die(unsigned int cpu)
|
||||
|
|
@ -92,7 +88,7 @@ static struct smp_operations __initdata mcpm_smp_ops = {
|
|||
.smp_secondary_init = mcpm_secondary_init,
|
||||
#ifdef CONFIG_HOTPLUG_CPU
|
||||
.cpu_kill = mcpm_cpu_kill,
|
||||
.cpu_disable = mcpm_cpu_disable,
|
||||
.cpu_can_disable = mcpm_cpu_can_disable,
|
||||
.cpu_die = mcpm_cpu_die,
|
||||
#endif
|
||||
};
|
||||
|
|
|
|||
|
|
@ -12,7 +12,6 @@ generic-y += irq_regs.h
|
|||
generic-y += kdebug.h
|
||||
generic-y += local.h
|
||||
generic-y += local64.h
|
||||
generic-y += mcs_spinlock.h
|
||||
generic-y += mm-arch-hooks.h
|
||||
generic-y += msgbuf.h
|
||||
generic-y += param.h
|
||||
|
|
|
|||
|
|
@ -108,33 +108,37 @@
|
|||
.endm
|
||||
#endif
|
||||
|
||||
.macro asm_trace_hardirqs_off
|
||||
.macro asm_trace_hardirqs_off, save=1
|
||||
#if defined(CONFIG_TRACE_IRQFLAGS)
|
||||
.if \save
|
||||
stmdb sp!, {r0-r3, ip, lr}
|
||||
.endif
|
||||
bl trace_hardirqs_off
|
||||
.if \save
|
||||
ldmia sp!, {r0-r3, ip, lr}
|
||||
.endif
|
||||
#endif
|
||||
.endm
|
||||
|
||||
.macro asm_trace_hardirqs_on_cond, cond
|
||||
.macro asm_trace_hardirqs_on, cond=al, save=1
|
||||
#if defined(CONFIG_TRACE_IRQFLAGS)
|
||||
/*
|
||||
* actually the registers should be pushed and pop'd conditionally, but
|
||||
* after bl the flags are certainly clobbered
|
||||
*/
|
||||
.if \save
|
||||
stmdb sp!, {r0-r3, ip, lr}
|
||||
.endif
|
||||
bl\cond trace_hardirqs_on
|
||||
.if \save
|
||||
ldmia sp!, {r0-r3, ip, lr}
|
||||
.endif
|
||||
#endif
|
||||
.endm
|
||||
|
||||
.macro asm_trace_hardirqs_on
|
||||
asm_trace_hardirqs_on_cond al
|
||||
.endm
|
||||
|
||||
.macro disable_irq
|
||||
.macro disable_irq, save=1
|
||||
disable_irq_notrace
|
||||
asm_trace_hardirqs_off
|
||||
asm_trace_hardirqs_off \save
|
||||
.endm
|
||||
|
||||
.macro enable_irq
|
||||
|
|
@ -173,7 +177,7 @@
|
|||
|
||||
.macro restore_irqs, oldcpsr
|
||||
tst \oldcpsr, #PSR_I_BIT
|
||||
asm_trace_hardirqs_on_cond eq
|
||||
asm_trace_hardirqs_on cond=eq
|
||||
restore_irqs_notrace \oldcpsr
|
||||
.endm
|
||||
|
||||
|
|
@ -445,6 +449,53 @@ THUMB( orr \reg , \reg , #PSR_T_BIT )
|
|||
#endif
|
||||
.endm
|
||||
|
||||
.macro uaccess_disable, tmp, isb=1
|
||||
#ifdef CONFIG_CPU_SW_DOMAIN_PAN
|
||||
/*
|
||||
* Whenever we re-enter userspace, the domains should always be
|
||||
* set appropriately.
|
||||
*/
|
||||
mov \tmp, #DACR_UACCESS_DISABLE
|
||||
mcr p15, 0, \tmp, c3, c0, 0 @ Set domain register
|
||||
.if \isb
|
||||
instr_sync
|
||||
.endif
|
||||
#endif
|
||||
.endm
|
||||
|
||||
.macro uaccess_enable, tmp, isb=1
|
||||
#ifdef CONFIG_CPU_SW_DOMAIN_PAN
|
||||
/*
|
||||
* Whenever we re-enter userspace, the domains should always be
|
||||
* set appropriately.
|
||||
*/
|
||||
mov \tmp, #DACR_UACCESS_ENABLE
|
||||
mcr p15, 0, \tmp, c3, c0, 0
|
||||
.if \isb
|
||||
instr_sync
|
||||
.endif
|
||||
#endif
|
||||
.endm
|
||||
|
||||
.macro uaccess_save, tmp
|
||||
#ifdef CONFIG_CPU_SW_DOMAIN_PAN
|
||||
mrc p15, 0, \tmp, c3, c0, 0
|
||||
str \tmp, [sp, #S_FRAME_SIZE]
|
||||
#endif
|
||||
.endm
|
||||
|
||||
.macro uaccess_restore
|
||||
#ifdef CONFIG_CPU_SW_DOMAIN_PAN
|
||||
ldr r0, [sp, #S_FRAME_SIZE]
|
||||
mcr p15, 0, r0, c3, c0, 0
|
||||
#endif
|
||||
.endm
|
||||
|
||||
.macro uaccess_save_and_disable, tmp
|
||||
uaccess_save \tmp
|
||||
uaccess_disable \tmp
|
||||
.endm
|
||||
|
||||
.irp c,,eq,ne,cs,cc,mi,pl,vs,vc,hi,ls,ge,lt,gt,le,hs,lo
|
||||
.macro ret\c, reg
|
||||
#if __LINUX_ARM_ARCH__ < 6
|
||||
|
|
|
|||
|
|
@ -2,7 +2,6 @@
|
|||
#define __ASM_BARRIER_H
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
#include <asm/outercache.h>
|
||||
|
||||
#define nop() __asm__ __volatile__("mov\tr0,r0\t@ nop\n\t");
|
||||
|
||||
|
|
@ -37,12 +36,20 @@
|
|||
#define dmb(x) __asm__ __volatile__ ("" : : : "memory")
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_ARM_HEAVY_MB
|
||||
extern void (*soc_mb)(void);
|
||||
extern void arm_heavy_mb(void);
|
||||
#define __arm_heavy_mb(x...) do { dsb(x); arm_heavy_mb(); } while (0)
|
||||
#else
|
||||
#define __arm_heavy_mb(x...) dsb(x)
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_ARCH_HAS_BARRIERS
|
||||
#include <mach/barriers.h>
|
||||
#elif defined(CONFIG_ARM_DMA_MEM_BUFFERABLE) || defined(CONFIG_SMP)
|
||||
#define mb() do { dsb(); outer_sync(); } while (0)
|
||||
#define mb() __arm_heavy_mb()
|
||||
#define rmb() dsb()
|
||||
#define wmb() do { dsb(st); outer_sync(); } while (0)
|
||||
#define wmb() __arm_heavy_mb(st)
|
||||
#define dma_rmb() dmb(osh)
|
||||
#define dma_wmb() dmb(oshst)
|
||||
#else
|
||||
|
|
|
|||
|
|
@ -35,9 +35,9 @@
|
|||
static inline void ____atomic_set_bit(unsigned int bit, volatile unsigned long *p)
|
||||
{
|
||||
unsigned long flags;
|
||||
unsigned long mask = 1UL << (bit & 31);
|
||||
unsigned long mask = BIT_MASK(bit);
|
||||
|
||||
p += bit >> 5;
|
||||
p += BIT_WORD(bit);
|
||||
|
||||
raw_local_irq_save(flags);
|
||||
*p |= mask;
|
||||
|
|
@ -47,9 +47,9 @@ static inline void ____atomic_set_bit(unsigned int bit, volatile unsigned long *
|
|||
static inline void ____atomic_clear_bit(unsigned int bit, volatile unsigned long *p)
|
||||
{
|
||||
unsigned long flags;
|
||||
unsigned long mask = 1UL << (bit & 31);
|
||||
unsigned long mask = BIT_MASK(bit);
|
||||
|
||||
p += bit >> 5;
|
||||
p += BIT_WORD(bit);
|
||||
|
||||
raw_local_irq_save(flags);
|
||||
*p &= ~mask;
|
||||
|
|
@ -59,9 +59,9 @@ static inline void ____atomic_clear_bit(unsigned int bit, volatile unsigned long
|
|||
static inline void ____atomic_change_bit(unsigned int bit, volatile unsigned long *p)
|
||||
{
|
||||
unsigned long flags;
|
||||
unsigned long mask = 1UL << (bit & 31);
|
||||
unsigned long mask = BIT_MASK(bit);
|
||||
|
||||
p += bit >> 5;
|
||||
p += BIT_WORD(bit);
|
||||
|
||||
raw_local_irq_save(flags);
|
||||
*p ^= mask;
|
||||
|
|
@ -73,9 +73,9 @@ ____atomic_test_and_set_bit(unsigned int bit, volatile unsigned long *p)
|
|||
{
|
||||
unsigned long flags;
|
||||
unsigned int res;
|
||||
unsigned long mask = 1UL << (bit & 31);
|
||||
unsigned long mask = BIT_MASK(bit);
|
||||
|
||||
p += bit >> 5;
|
||||
p += BIT_WORD(bit);
|
||||
|
||||
raw_local_irq_save(flags);
|
||||
res = *p;
|
||||
|
|
@ -90,9 +90,9 @@ ____atomic_test_and_clear_bit(unsigned int bit, volatile unsigned long *p)
|
|||
{
|
||||
unsigned long flags;
|
||||
unsigned int res;
|
||||
unsigned long mask = 1UL << (bit & 31);
|
||||
unsigned long mask = BIT_MASK(bit);
|
||||
|
||||
p += bit >> 5;
|
||||
p += BIT_WORD(bit);
|
||||
|
||||
raw_local_irq_save(flags);
|
||||
res = *p;
|
||||
|
|
@ -107,9 +107,9 @@ ____atomic_test_and_change_bit(unsigned int bit, volatile unsigned long *p)
|
|||
{
|
||||
unsigned long flags;
|
||||
unsigned int res;
|
||||
unsigned long mask = 1UL << (bit & 31);
|
||||
unsigned long mask = BIT_MASK(bit);
|
||||
|
||||
p += bit >> 5;
|
||||
p += BIT_WORD(bit);
|
||||
|
||||
raw_local_irq_save(flags);
|
||||
res = *p;
|
||||
|
|
|
|||
|
|
@ -140,8 +140,6 @@ extern struct cpu_cache_fns cpu_cache;
|
|||
* is visible to DMA, or data written by DMA to system memory is
|
||||
* visible to the CPU.
|
||||
*/
|
||||
#define dmac_map_area cpu_cache.dma_map_area
|
||||
#define dmac_unmap_area cpu_cache.dma_unmap_area
|
||||
#define dmac_flush_range cpu_cache.dma_flush_range
|
||||
|
||||
#else
|
||||
|
|
@ -161,8 +159,6 @@ extern void __cpuc_flush_dcache_area(void *, size_t);
|
|||
* is visible to DMA, or data written by DMA to system memory is
|
||||
* visible to the CPU.
|
||||
*/
|
||||
extern void dmac_map_area(const void *, size_t, int);
|
||||
extern void dmac_unmap_area(const void *, size_t, int);
|
||||
extern void dmac_flush_range(const void *, const void *);
|
||||
|
||||
#endif
|
||||
|
|
@ -506,4 +502,21 @@ static inline void set_kernel_text_ro(void) { }
|
|||
void flush_uprobe_xol_access(struct page *page, unsigned long uaddr,
|
||||
void *kaddr, unsigned long len);
|
||||
|
||||
/**
|
||||
* secure_flush_area - ensure coherency across the secure boundary
|
||||
* @addr: virtual address
|
||||
* @size: size of region
|
||||
*
|
||||
* Ensure that the specified area of memory is coherent across the secure
|
||||
* boundary from the non-secure side. This is used when calling secure
|
||||
* firmware where the secure firmware does not ensure coherency.
|
||||
*/
|
||||
static inline void secure_flush_area(const void *addr, size_t size)
|
||||
{
|
||||
phys_addr_t phys = __pa(addr);
|
||||
|
||||
__cpuc_flush_dcache_area((void *)addr, size);
|
||||
outer_flush_range(phys, phys + size);
|
||||
}
|
||||
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -14,7 +14,7 @@
|
|||
#include <xen/xen.h>
|
||||
#include <asm/xen/hypervisor.h>
|
||||
|
||||
#define DMA_ERROR_CODE (~0)
|
||||
#define DMA_ERROR_CODE (~(dma_addr_t)0x0)
|
||||
extern struct dma_map_ops arm_dma_ops;
|
||||
extern struct dma_map_ops arm_coherent_dma_ops;
|
||||
|
||||
|
|
|
|||
|
|
@ -34,15 +34,14 @@
|
|||
*/
|
||||
#ifndef CONFIG_IO_36
|
||||
#define DOMAIN_KERNEL 0
|
||||
#define DOMAIN_TABLE 0
|
||||
#define DOMAIN_USER 1
|
||||
#define DOMAIN_IO 2
|
||||
#else
|
||||
#define DOMAIN_KERNEL 2
|
||||
#define DOMAIN_TABLE 2
|
||||
#define DOMAIN_USER 1
|
||||
#define DOMAIN_IO 0
|
||||
#endif
|
||||
#define DOMAIN_VECTORS 3
|
||||
|
||||
/*
|
||||
* Domain types
|
||||
|
|
@ -55,11 +54,46 @@
|
|||
#define DOMAIN_MANAGER 1
|
||||
#endif
|
||||
|
||||
#define domain_val(dom,type) ((type) << (2*(dom)))
|
||||
#define domain_mask(dom) ((3) << (2 * (dom)))
|
||||
#define domain_val(dom,type) ((type) << (2 * (dom)))
|
||||
|
||||
#ifdef CONFIG_CPU_SW_DOMAIN_PAN
|
||||
#define DACR_INIT \
|
||||
(domain_val(DOMAIN_USER, DOMAIN_NOACCESS) | \
|
||||
domain_val(DOMAIN_KERNEL, DOMAIN_MANAGER) | \
|
||||
domain_val(DOMAIN_IO, DOMAIN_CLIENT) | \
|
||||
domain_val(DOMAIN_VECTORS, DOMAIN_CLIENT))
|
||||
#else
|
||||
#define DACR_INIT \
|
||||
(domain_val(DOMAIN_USER, DOMAIN_CLIENT) | \
|
||||
domain_val(DOMAIN_KERNEL, DOMAIN_MANAGER) | \
|
||||
domain_val(DOMAIN_IO, DOMAIN_CLIENT) | \
|
||||
domain_val(DOMAIN_VECTORS, DOMAIN_CLIENT))
|
||||
#endif
|
||||
|
||||
#define __DACR_DEFAULT \
|
||||
domain_val(DOMAIN_KERNEL, DOMAIN_CLIENT) | \
|
||||
domain_val(DOMAIN_IO, DOMAIN_CLIENT) | \
|
||||
domain_val(DOMAIN_VECTORS, DOMAIN_CLIENT)
|
||||
|
||||
#define DACR_UACCESS_DISABLE \
|
||||
(__DACR_DEFAULT | domain_val(DOMAIN_USER, DOMAIN_NOACCESS))
|
||||
#define DACR_UACCESS_ENABLE \
|
||||
(__DACR_DEFAULT | domain_val(DOMAIN_USER, DOMAIN_CLIENT))
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
|
||||
#ifdef CONFIG_CPU_USE_DOMAINS
|
||||
static inline unsigned int get_domain(void)
|
||||
{
|
||||
unsigned int domain;
|
||||
|
||||
asm(
|
||||
"mrc p15, 0, %0, c3, c0 @ get domain"
|
||||
: "=r" (domain));
|
||||
|
||||
return domain;
|
||||
}
|
||||
|
||||
static inline void set_domain(unsigned val)
|
||||
{
|
||||
asm volatile(
|
||||
|
|
@ -68,17 +102,16 @@ static inline void set_domain(unsigned val)
|
|||
isb();
|
||||
}
|
||||
|
||||
#ifdef CONFIG_CPU_USE_DOMAINS
|
||||
#define modify_domain(dom,type) \
|
||||
do { \
|
||||
struct thread_info *thread = current_thread_info(); \
|
||||
unsigned int domain = thread->cpu_domain; \
|
||||
domain &= ~domain_val(dom, DOMAIN_MANAGER); \
|
||||
thread->cpu_domain = domain | domain_val(dom, type); \
|
||||
set_domain(thread->cpu_domain); \
|
||||
unsigned int domain = get_domain(); \
|
||||
domain &= ~domain_mask(dom); \
|
||||
domain = domain | domain_val(dom, type); \
|
||||
set_domain(domain); \
|
||||
} while (0)
|
||||
|
||||
#else
|
||||
static inline void set_domain(unsigned val) { }
|
||||
static inline void modify_domain(unsigned dom, unsigned type) { }
|
||||
#endif
|
||||
|
||||
|
|
|
|||
|
|
@ -6,9 +6,13 @@
|
|||
#define FIXADDR_TOP (FIXADDR_END - PAGE_SIZE)
|
||||
|
||||
#include <asm/kmap_types.h>
|
||||
#include <asm/pgtable.h>
|
||||
|
||||
enum fixed_addresses {
|
||||
FIX_KMAP_BEGIN,
|
||||
FIX_EARLYCON_MEM_BASE,
|
||||
__end_of_permanent_fixed_addresses,
|
||||
|
||||
FIX_KMAP_BEGIN = __end_of_permanent_fixed_addresses,
|
||||
FIX_KMAP_END = FIX_KMAP_BEGIN + (KM_TYPE_NR * NR_CPUS) - 1,
|
||||
|
||||
/* Support writing RO kernel text via kprobes, jump labels, etc. */
|
||||
|
|
@ -18,7 +22,16 @@ enum fixed_addresses {
|
|||
__end_of_fixed_addresses
|
||||
};
|
||||
|
||||
#define FIXMAP_PAGE_COMMON (L_PTE_YOUNG | L_PTE_PRESENT | L_PTE_XN | L_PTE_DIRTY)
|
||||
|
||||
#define FIXMAP_PAGE_NORMAL (FIXMAP_PAGE_COMMON | L_PTE_MT_WRITEBACK)
|
||||
|
||||
/* Used by set_fixmap_(io|nocache), both meant for mapping a device */
|
||||
#define FIXMAP_PAGE_IO (FIXMAP_PAGE_COMMON | L_PTE_MT_DEV_SHARED | L_PTE_SHARED)
|
||||
#define FIXMAP_PAGE_NOCACHE FIXMAP_PAGE_IO
|
||||
|
||||
void __set_fixmap(enum fixed_addresses idx, phys_addr_t phys, pgprot_t prot);
|
||||
void __init early_fixmap_init(void);
|
||||
|
||||
#include <asm-generic/fixmap.h>
|
||||
|
||||
|
|
|
|||
|
|
@ -22,8 +22,11 @@
|
|||
#ifdef CONFIG_SMP
|
||||
|
||||
#define __futex_atomic_op(insn, ret, oldval, tmp, uaddr, oparg) \
|
||||
({ \
|
||||
unsigned int __ua_flags; \
|
||||
smp_mb(); \
|
||||
prefetchw(uaddr); \
|
||||
__ua_flags = uaccess_save_and_enable(); \
|
||||
__asm__ __volatile__( \
|
||||
"1: ldrex %1, [%3]\n" \
|
||||
" " insn "\n" \
|
||||
|
|
@ -34,12 +37,15 @@
|
|||
__futex_atomic_ex_table("%5") \
|
||||
: "=&r" (ret), "=&r" (oldval), "=&r" (tmp) \
|
||||
: "r" (uaddr), "r" (oparg), "Ir" (-EFAULT) \
|
||||
: "cc", "memory")
|
||||
: "cc", "memory"); \
|
||||
uaccess_restore(__ua_flags); \
|
||||
})
|
||||
|
||||
static inline int
|
||||
futex_atomic_cmpxchg_inatomic(u32 *uval, u32 __user *uaddr,
|
||||
u32 oldval, u32 newval)
|
||||
{
|
||||
unsigned int __ua_flags;
|
||||
int ret;
|
||||
u32 val;
|
||||
|
||||
|
|
@ -49,6 +55,7 @@ futex_atomic_cmpxchg_inatomic(u32 *uval, u32 __user *uaddr,
|
|||
smp_mb();
|
||||
/* Prefetching cannot fault */
|
||||
prefetchw(uaddr);
|
||||
__ua_flags = uaccess_save_and_enable();
|
||||
__asm__ __volatile__("@futex_atomic_cmpxchg_inatomic\n"
|
||||
"1: ldrex %1, [%4]\n"
|
||||
" teq %1, %2\n"
|
||||
|
|
@ -61,6 +68,7 @@ futex_atomic_cmpxchg_inatomic(u32 *uval, u32 __user *uaddr,
|
|||
: "=&r" (ret), "=&r" (val)
|
||||
: "r" (oldval), "r" (newval), "r" (uaddr), "Ir" (-EFAULT)
|
||||
: "cc", "memory");
|
||||
uaccess_restore(__ua_flags);
|
||||
smp_mb();
|
||||
|
||||
*uval = val;
|
||||
|
|
@ -73,6 +81,8 @@ futex_atomic_cmpxchg_inatomic(u32 *uval, u32 __user *uaddr,
|
|||
#include <asm/domain.h>
|
||||
|
||||
#define __futex_atomic_op(insn, ret, oldval, tmp, uaddr, oparg) \
|
||||
({ \
|
||||
unsigned int __ua_flags = uaccess_save_and_enable(); \
|
||||
__asm__ __volatile__( \
|
||||
"1: " TUSER(ldr) " %1, [%3]\n" \
|
||||
" " insn "\n" \
|
||||
|
|
@ -81,12 +91,15 @@ futex_atomic_cmpxchg_inatomic(u32 *uval, u32 __user *uaddr,
|
|||
__futex_atomic_ex_table("%5") \
|
||||
: "=&r" (ret), "=&r" (oldval), "=&r" (tmp) \
|
||||
: "r" (uaddr), "r" (oparg), "Ir" (-EFAULT) \
|
||||
: "cc", "memory")
|
||||
: "cc", "memory"); \
|
||||
uaccess_restore(__ua_flags); \
|
||||
})
|
||||
|
||||
static inline int
|
||||
futex_atomic_cmpxchg_inatomic(u32 *uval, u32 __user *uaddr,
|
||||
u32 oldval, u32 newval)
|
||||
{
|
||||
unsigned int __ua_flags;
|
||||
int ret = 0;
|
||||
u32 val;
|
||||
|
||||
|
|
@ -94,6 +107,7 @@ futex_atomic_cmpxchg_inatomic(u32 *uval, u32 __user *uaddr,
|
|||
return -EFAULT;
|
||||
|
||||
preempt_disable();
|
||||
__ua_flags = uaccess_save_and_enable();
|
||||
__asm__ __volatile__("@futex_atomic_cmpxchg_inatomic\n"
|
||||
"1: " TUSER(ldr) " %1, [%4]\n"
|
||||
" teq %1, %2\n"
|
||||
|
|
@ -103,6 +117,7 @@ futex_atomic_cmpxchg_inatomic(u32 *uval, u32 __user *uaddr,
|
|||
: "+r" (ret), "=&r" (val)
|
||||
: "r" (oldval), "r" (newval), "r" (uaddr), "Ir" (-EFAULT)
|
||||
: "cc", "memory");
|
||||
uaccess_restore(__ua_flags);
|
||||
|
||||
*uval = val;
|
||||
preempt_enable();
|
||||
|
|
|
|||
|
|
@ -158,8 +158,6 @@ static inline void nop_dma_unmap_area(const void *s, size_t l, int f) { }
|
|||
#define __cpuc_coherent_user_range __glue(_CACHE,_coherent_user_range)
|
||||
#define __cpuc_flush_dcache_area __glue(_CACHE,_flush_kern_dcache_area)
|
||||
|
||||
#define dmac_map_area __glue(_CACHE,_dma_map_area)
|
||||
#define dmac_unmap_area __glue(_CACHE,_dma_unmap_area)
|
||||
#define dmac_flush_range __glue(_CACHE,_dma_flush_range)
|
||||
#endif
|
||||
|
||||
|
|
|
|||
|
|
@ -129,21 +129,4 @@ static inline void outer_resume(void) { }
|
|||
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_OUTER_CACHE_SYNC
|
||||
/**
|
||||
* outer_sync - perform a sync point for outer cache
|
||||
*
|
||||
* Ensure that all outer cache operations are complete and any store
|
||||
* buffers are drained.
|
||||
*/
|
||||
static inline void outer_sync(void)
|
||||
{
|
||||
if (outer_cache.sync)
|
||||
outer_cache.sync();
|
||||
}
|
||||
#else
|
||||
static inline void outer_sync(void)
|
||||
{ }
|
||||
#endif
|
||||
|
||||
#endif /* __ASM_OUTERCACHE_H */
|
||||
|
|
|
|||
|
|
@ -23,6 +23,7 @@
|
|||
#define PMD_PXNTABLE (_AT(pmdval_t, 1) << 2) /* v7 */
|
||||
#define PMD_BIT4 (_AT(pmdval_t, 1) << 4)
|
||||
#define PMD_DOMAIN(x) (_AT(pmdval_t, (x)) << 5)
|
||||
#define PMD_DOMAIN_MASK PMD_DOMAIN(0x0f)
|
||||
#define PMD_PROTECTION (_AT(pmdval_t, 1) << 9) /* v5 */
|
||||
/*
|
||||
* - section
|
||||
|
|
|
|||
|
|
@ -14,34 +14,11 @@
|
|||
#ifndef __ASM_ARM_PSCI_H
|
||||
#define __ASM_ARM_PSCI_H
|
||||
|
||||
#define PSCI_POWER_STATE_TYPE_STANDBY 0
|
||||
#define PSCI_POWER_STATE_TYPE_POWER_DOWN 1
|
||||
|
||||
struct psci_power_state {
|
||||
u16 id;
|
||||
u8 type;
|
||||
u8 affinity_level;
|
||||
};
|
||||
|
||||
struct psci_operations {
|
||||
int (*cpu_suspend)(struct psci_power_state state,
|
||||
unsigned long entry_point);
|
||||
int (*cpu_off)(struct psci_power_state state);
|
||||
int (*cpu_on)(unsigned long cpuid, unsigned long entry_point);
|
||||
int (*migrate)(unsigned long cpuid);
|
||||
int (*affinity_info)(unsigned long target_affinity,
|
||||
unsigned long lowest_affinity_level);
|
||||
int (*migrate_info_type)(void);
|
||||
};
|
||||
|
||||
extern struct psci_operations psci_ops;
|
||||
extern struct smp_operations psci_smp_ops;
|
||||
|
||||
#ifdef CONFIG_ARM_PSCI
|
||||
int psci_init(void);
|
||||
bool psci_smp_available(void);
|
||||
#else
|
||||
static inline int psci_init(void) { return 0; }
|
||||
static inline bool psci_smp_available(void) { return false; }
|
||||
#endif
|
||||
|
||||
|
|
|
|||
|
|
@ -74,7 +74,6 @@ extern void secondary_startup_arm(void);
|
|||
extern int __cpu_disable(void);
|
||||
|
||||
extern void __cpu_die(unsigned int cpu);
|
||||
extern void cpu_die(void);
|
||||
|
||||
extern void arch_send_call_function_single_ipi(int cpu);
|
||||
extern void arch_send_call_function_ipi_mask(const struct cpumask *mask);
|
||||
|
|
@ -105,6 +104,7 @@ struct smp_operations {
|
|||
#ifdef CONFIG_HOTPLUG_CPU
|
||||
int (*cpu_kill)(unsigned int cpu);
|
||||
void (*cpu_die)(unsigned int cpu);
|
||||
bool (*cpu_can_disable)(unsigned int cpu);
|
||||
int (*cpu_disable)(unsigned int cpu);
|
||||
#endif
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -107,4 +107,13 @@ static inline u32 mpidr_hash_size(void)
|
|||
extern int platform_can_secondary_boot(void);
|
||||
extern int platform_can_cpu_hotplug(void);
|
||||
|
||||
#ifdef CONFIG_HOTPLUG_CPU
|
||||
extern int platform_can_hotplug_cpu(unsigned int cpu);
|
||||
#else
|
||||
static inline int platform_can_hotplug_cpu(unsigned int cpu)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
|
|
|||
Some files were not shown because too many files have changed in this diff Show more
Loading…
Reference in a new issue