mirror of
https://github.com/a52xq-dev/kernel.git
synced 2026-10-18 21:58:11 +07:00
arm64 updates for 4.12:
- kdump support, including two necessary memblock additions: memblock_clear_nomap() and memblock_cap_memory_range() - ARMv8.3 HWCAP bits for JavaScript conversion instructions, complex numbers and weaker release consistency - arm64 ACPI platform MSI support - arm perf updates: ACPI PMU support, L3 cache PMU in some Qualcomm SoCs, Cortex-A53 L2 cache events and DTLB refills, MAINTAINERS update for DT perf bindings - architected timer errata framework (the arch/arm64 changes only) - support for DMA_ATTR_FORCE_CONTIGUOUS in the arm64 iommu DMA API - arm64 KVM refactoring to use common system register definitions - remove support for ASID-tagged VIVT I-cache (no ARMv8 implementation using it and deprecated in the architecture) together with some I-cache handling clean-up - PE/COFF EFI header clean-up/hardening - define BUG() instruction without CONFIG_BUG -----BEGIN PGP SIGNATURE----- Version: GnuPG v1 iQIcBAABAgAGBQJZDKMoAAoJEGvWsS0AyF7xR+YP/0EMEz5MDfCv0PVYj7/AIa0G Zphl7OhysIkeDAz7urXw9Jdl0NfORNIqmD1vZNVSc321IyNp56Od+kWd82lBrOWB ad3nNT67pEmu0pAW7CO48ju3rTesEnEl3ra45E1tULeLihmv93jc4ZlfXgumlKq3 /GE84XJ5ZFmluuhq1zgNefeUtyl1tbxTxHJ74+INF7dTd/5sJcphpqS4Dzpb+msT 20WYliccQCBF9zBFUYHc2KjcXXKRQGxLulGS3MuoN2DLkD+U9YyR/OmA7SoXh2J2 WXC5b0x856xTQJFCJ39pb7rw5xHjt3l5zfU3VLSvqEVL/+asBqCcgGNtNUgOW1Es dEHC6bc66Ley6mn7bbpFE3MK8D+K5q8HwMF6G5KDtIVB6DB/iQ6kzi5aXKoupxtb 1EuU4OW6cDhmOFQYjgIDofLgqbmVvJofdF6+NfxasfZmWrMgHzv0rYvaCDnAV/Tr t7bhH7hf9/KcP/wpk86O2AMKKpgoNTqe1Qy8cWVFFLnut567Pb6zs/L3ZXfleoLv t613yM8Zj2fE05ja8ylMDjaasidNpXGttb08/4kAn06Daaoueqla0jmduAhy4aaV dQ3OFP9lJ5MFaFnMMTPfU3vtvNLMHuo9MZsYCrv5zCaNNs3lpAPUiPNh588ZscKa sWx4PEiaCi+wcOsLsJvh =SDkm -----END PGP SIGNATURE----- Merge tag 'arm64-upstream' of git://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux Pull arm64 updates from Catalin Marinas: - kdump support, including two necessary memblock additions: memblock_clear_nomap() and memblock_cap_memory_range() - ARMv8.3 HWCAP bits for JavaScript conversion instructions, complex numbers and weaker release consistency - arm64 ACPI platform MSI support - arm perf updates: ACPI PMU support, L3 cache PMU in some Qualcomm SoCs, Cortex-A53 L2 cache events and DTLB refills, MAINTAINERS update for DT perf bindings - architected timer errata framework (the arch/arm64 changes only) - support for DMA_ATTR_FORCE_CONTIGUOUS in the arm64 iommu DMA API - arm64 KVM refactoring to use common system register definitions - remove support for ASID-tagged VIVT I-cache (no ARMv8 implementation using it and deprecated in the architecture) together with some I-cache handling clean-up - PE/COFF EFI header clean-up/hardening - define BUG() instruction without CONFIG_BUG * tag 'arm64-upstream' of git://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux: (92 commits) arm64: Fix the DMA mmap and get_sgtable API with DMA_ATTR_FORCE_CONTIGUOUS arm64: Print DT machine model in setup_machine_fdt() arm64: pmu: Wire-up Cortex A53 L2 cache events and DTLB refills arm64: module: split core and init PLT sections arm64: pmuv3: handle pmuv3+ arm64: Add CNTFRQ_EL0 trap handler arm64: Silence spurious kbuild warning on menuconfig arm64: pmuv3: use arm_pmu ACPI framework arm64: pmuv3: handle !PMUv3 when probing drivers/perf: arm_pmu: add ACPI framework arm64: add function to get a cpu's MADT GICC table drivers/perf: arm_pmu: split out platform device probe logic drivers/perf: arm_pmu: move irq request/free into probe drivers/perf: arm_pmu: split cpu-local irq request/free drivers/perf: arm_pmu: rename irq request/free functions drivers/perf: arm_pmu: handle no platform_device drivers/perf: arm_pmu: simplify cpu_pmu_request_irqs() drivers/perf: arm_pmu: factor out pmu registration drivers/perf: arm_pmu: fold init into alloc drivers/perf: arm_pmu: define armpmu_init_fn ...
This commit is contained in:
Linus Torvalds
commit
ab182e67ec
77 changed files with 3754 additions and 1256 deletions
|
|
@ -169,6 +169,18 @@ infrastructure:
|
|||
as available on the CPU where it is fetched and is not a system
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wide safe value.
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4) ID_AA64ISAR1_EL1 - Instruction set attribute register 1
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||||
x--------------------------------------------------x
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||||
| Name | bits | visible |
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||||
|--------------------------------------------------|
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||||
| LRCPC | [23-20] | y |
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||||
|--------------------------------------------------|
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||||
| FCMA | [19-16] | y |
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||||
|--------------------------------------------------|
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||||
| JSCVT | [15-12] | y |
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x--------------------------------------------------x
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Appendix I: Example
|
||||
---------------------------
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||||
|
||||
|
|
|
|||
|
|
@ -52,3 +52,48 @@ This property is set (currently only on PowerPC, and only needed on
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book3e) by some versions of kexec-tools to tell the new kernel that it
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is being booted by kexec, as the booting environment may differ (e.g.
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a different secondary CPU release mechanism)
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linux,usable-memory-range
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-------------------------
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This property (arm64 only) holds a base address and size, describing a
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limited region in which memory may be considered available for use by
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the kernel. Memory outside of this range is not available for use.
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This property describes a limitation: memory within this range is only
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valid when also described through another mechanism that the kernel
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would otherwise use to determine available memory (e.g. memory nodes
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or the EFI memory map). Valid memory may be sparse within the range.
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e.g.
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||||
/ {
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chosen {
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linux,usable-memory-range = <0x9 0xf0000000 0x0 0x10000000>;
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};
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};
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The main usage is for crash dump kernel to identify its own usable
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memory and exclude, at its boot time, any other memory areas that are
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part of the panicked kernel's memory.
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|
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While this property does not represent a real hardware, the address
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and the size are expressed in #address-cells and #size-cells,
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respectively, of the root node.
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linux,elfcorehdr
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||||
----------------
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This property (currently used only on arm64) holds the memory range,
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the address and the size, of the elf core header which mainly describes
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the panicked kernel's memory layout as PT_LOAD segments of elf format.
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e.g.
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/ {
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chosen {
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linux,elfcorehdr = <0x9 0xfffff000 0x0 0x800>;
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||||
};
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};
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While this property does not represent a real hardware, the address
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and the size are expressed in #address-cells and #size-cells,
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respectively, of the root node.
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|
|
|
|||
|
|
@ -18,7 +18,7 @@ memory image to a dump file on the local disk, or across the network to
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a remote system.
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Kdump and kexec are currently supported on the x86, x86_64, ppc64, ia64,
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s390x and arm architectures.
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s390x, arm and arm64 architectures.
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When the system kernel boots, it reserves a small section of memory for
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the dump-capture kernel. This ensures that ongoing Direct Memory Access
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|
|
@ -249,6 +249,13 @@ Dump-capture kernel config options (Arch Dependent, arm)
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AUTO_ZRELADDR=y
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Dump-capture kernel config options (Arch Dependent, arm64)
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----------------------------------------------------------
|
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|
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- Please note that kvm of the dump-capture kernel will not be enabled
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on non-VHE systems even if it is configured. This is because the CPU
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will not be reset to EL2 on panic.
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|
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Extended crashkernel syntax
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===========================
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|
|
@ -305,6 +312,8 @@ Boot into System Kernel
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kernel will automatically locate the crash kernel image within the
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first 512MB of RAM if X is not given.
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|
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On arm64, use "crashkernel=Y[@X]". Note that the start address of
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the kernel, X if explicitly specified, must be aligned to 2MiB (0x200000).
|
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|
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Load the Dump-capture Kernel
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||||
============================
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|
|
@ -327,6 +336,8 @@ For s390x:
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|||
- Use image or bzImage
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For arm:
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- Use zImage
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For arm64:
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- Use vmlinux or Image
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If you are using a uncompressed vmlinux image then use following command
|
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to load dump-capture kernel.
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|
|
@ -370,6 +381,9 @@ For s390x:
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For arm:
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"1 maxcpus=1 reset_devices"
|
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|
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For arm64:
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||||
"1 maxcpus=1 reset_devices"
|
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|
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Notes on loading the dump-capture kernel:
|
||||
|
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* By default, the ELF headers are stored in ELF64 format to support
|
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|
|
|
|||
25
Documentation/perf/qcom_l3_pmu.txt
Normal file
25
Documentation/perf/qcom_l3_pmu.txt
Normal file
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|
@ -0,0 +1,25 @@
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|||
Qualcomm Datacenter Technologies L3 Cache Performance Monitoring Unit (PMU)
|
||||
===========================================================================
|
||||
|
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This driver supports the L3 cache PMUs found in Qualcomm Datacenter Technologies
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Centriq SoCs. The L3 cache on these SOCs is composed of multiple slices, shared
|
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by all cores within a socket. Each slice is exposed as a separate uncore perf
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PMU with device name l3cache_<socket>_<instance>. User space is responsible
|
||||
for aggregating across slices.
|
||||
|
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The driver provides a description of its available events and configuration
|
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options in sysfs, see /sys/devices/l3cache*. Given that these are uncore PMUs
|
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the driver also exposes a "cpumask" sysfs attribute which contains a mask
|
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consisting of one CPU per socket which will be used to handle all the PMU
|
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events on that socket.
|
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|
||||
The hardware implements 32bit event counters and has a flat 8bit event space
|
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exposed via the "event" format attribute. In addition to the 32bit physical
|
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counters the driver supports virtual 64bit hardware counters by using hardware
|
||||
counter chaining. This feature is exposed via the "lc" (long counter) format
|
||||
flag. E.g.:
|
||||
|
||||
perf stat -e l3cache_0_0/read-miss,lc/
|
||||
|
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Given that these are uncore PMUs the driver does not support sampling, therefore
|
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"perf record" will not work. Per-task perf sessions are not supported.
|
||||
|
|
@ -983,6 +983,7 @@ F: arch/arm*/include/asm/perf_event.h
|
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F: drivers/perf/*
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F: include/linux/perf/arm_pmu.h
|
||||
F: Documentation/devicetree/bindings/arm/pmu.txt
|
||||
F: Documentation/devicetree/bindings/perf/
|
||||
|
||||
ARM PORT
|
||||
M: Russell King <linux@armlinux.org.uk>
|
||||
|
|
|
|||
|
|
@ -736,6 +736,17 @@ config KEXEC
|
|||
but it is independent of the system firmware. And like a reboot
|
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you can start any kernel with it, not just Linux.
|
||||
|
||||
config CRASH_DUMP
|
||||
bool "Build kdump crash kernel"
|
||||
help
|
||||
Generate crash dump after being started by kexec. This should
|
||||
be normally only set in special crash dump kernels which are
|
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loaded in the main kernel with kexec-tools into a specially
|
||||
reserved region and then later executed after a crash by
|
||||
kdump/kexec.
|
||||
|
||||
For more details see Documentation/kdump/kdump.txt
|
||||
|
||||
config XEN_DOM0
|
||||
def_bool y
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||||
depends on XEN
|
||||
|
|
|
|||
|
|
@ -92,6 +92,10 @@ config DEBUG_EFI
|
|||
the kernel that are only useful when using a debug build of the
|
||||
UEFI firmware
|
||||
|
||||
config ARM64_RELOC_TEST
|
||||
depends on m
|
||||
tristate "Relocation testing module"
|
||||
|
||||
source "drivers/hwtracing/coresight/Kconfig"
|
||||
|
||||
endmenu
|
||||
|
|
|
|||
|
|
@ -37,10 +37,12 @@ $(warning LSE atomics not supported by binutils)
|
|||
endif
|
||||
endif
|
||||
|
||||
ifeq ($(CONFIG_ARM64), y)
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||||
brokengasinst := $(call as-instr,1:\n.inst 0\n.rept . - 1b\n\nnop\n.endr\n,,-DCONFIG_BROKEN_GAS_INST=1)
|
||||
|
||||
ifneq ($(brokengasinst),)
|
||||
ifneq ($(brokengasinst),)
|
||||
$(warning Detected assembler with broken .inst; disassembly will be unreliable)
|
||||
endif
|
||||
endif
|
||||
|
||||
KBUILD_CFLAGS += -mgeneral-regs-only $(lseinstr) $(brokengasinst)
|
||||
|
|
|
|||
|
|
@ -82,6 +82,7 @@ CONFIG_CMA=y
|
|||
CONFIG_SECCOMP=y
|
||||
CONFIG_XEN=y
|
||||
CONFIG_KEXEC=y
|
||||
CONFIG_CRASH_DUMP=y
|
||||
# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
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CONFIG_COMPAT=y
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CONFIG_CPU_IDLE=y
|
||||
|
|
|
|||
|
|
@ -85,6 +85,8 @@ static inline bool acpi_has_cpu_in_madt(void)
|
|||
return true;
|
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}
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||||
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struct acpi_madt_generic_interrupt *acpi_cpu_get_madt_gicc(int cpu);
|
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static inline void arch_fix_phys_package_id(int num, u32 slot) { }
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||||
void __init acpi_init_cpus(void);
|
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|
||||
|
|
|
|||
|
|
@ -20,69 +20,14 @@
|
|||
|
||||
#include <asm/sysreg.h>
|
||||
|
||||
#define ICC_EOIR1_EL1 sys_reg(3, 0, 12, 12, 1)
|
||||
#define ICC_DIR_EL1 sys_reg(3, 0, 12, 11, 1)
|
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#define ICC_IAR1_EL1 sys_reg(3, 0, 12, 12, 0)
|
||||
#define ICC_SGI1R_EL1 sys_reg(3, 0, 12, 11, 5)
|
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#define ICC_PMR_EL1 sys_reg(3, 0, 4, 6, 0)
|
||||
#define ICC_CTLR_EL1 sys_reg(3, 0, 12, 12, 4)
|
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#define ICC_SRE_EL1 sys_reg(3, 0, 12, 12, 5)
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#define ICC_GRPEN1_EL1 sys_reg(3, 0, 12, 12, 7)
|
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#define ICC_BPR1_EL1 sys_reg(3, 0, 12, 12, 3)
|
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|
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#define ICC_SRE_EL2 sys_reg(3, 4, 12, 9, 5)
|
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|
||||
/*
|
||||
* System register definitions
|
||||
*/
|
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#define ICH_VSEIR_EL2 sys_reg(3, 4, 12, 9, 4)
|
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#define ICH_HCR_EL2 sys_reg(3, 4, 12, 11, 0)
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#define ICH_VTR_EL2 sys_reg(3, 4, 12, 11, 1)
|
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#define ICH_MISR_EL2 sys_reg(3, 4, 12, 11, 2)
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#define ICH_EISR_EL2 sys_reg(3, 4, 12, 11, 3)
|
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#define ICH_ELSR_EL2 sys_reg(3, 4, 12, 11, 5)
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#define ICH_VMCR_EL2 sys_reg(3, 4, 12, 11, 7)
|
||||
|
||||
#define __LR0_EL2(x) sys_reg(3, 4, 12, 12, x)
|
||||
#define __LR8_EL2(x) sys_reg(3, 4, 12, 13, x)
|
||||
|
||||
#define ICH_LR0_EL2 __LR0_EL2(0)
|
||||
#define ICH_LR1_EL2 __LR0_EL2(1)
|
||||
#define ICH_LR2_EL2 __LR0_EL2(2)
|
||||
#define ICH_LR3_EL2 __LR0_EL2(3)
|
||||
#define ICH_LR4_EL2 __LR0_EL2(4)
|
||||
#define ICH_LR5_EL2 __LR0_EL2(5)
|
||||
#define ICH_LR6_EL2 __LR0_EL2(6)
|
||||
#define ICH_LR7_EL2 __LR0_EL2(7)
|
||||
#define ICH_LR8_EL2 __LR8_EL2(0)
|
||||
#define ICH_LR9_EL2 __LR8_EL2(1)
|
||||
#define ICH_LR10_EL2 __LR8_EL2(2)
|
||||
#define ICH_LR11_EL2 __LR8_EL2(3)
|
||||
#define ICH_LR12_EL2 __LR8_EL2(4)
|
||||
#define ICH_LR13_EL2 __LR8_EL2(5)
|
||||
#define ICH_LR14_EL2 __LR8_EL2(6)
|
||||
#define ICH_LR15_EL2 __LR8_EL2(7)
|
||||
|
||||
#define __AP0Rx_EL2(x) sys_reg(3, 4, 12, 8, x)
|
||||
#define ICH_AP0R0_EL2 __AP0Rx_EL2(0)
|
||||
#define ICH_AP0R1_EL2 __AP0Rx_EL2(1)
|
||||
#define ICH_AP0R2_EL2 __AP0Rx_EL2(2)
|
||||
#define ICH_AP0R3_EL2 __AP0Rx_EL2(3)
|
||||
|
||||
#define __AP1Rx_EL2(x) sys_reg(3, 4, 12, 9, x)
|
||||
#define ICH_AP1R0_EL2 __AP1Rx_EL2(0)
|
||||
#define ICH_AP1R1_EL2 __AP1Rx_EL2(1)
|
||||
#define ICH_AP1R2_EL2 __AP1Rx_EL2(2)
|
||||
#define ICH_AP1R3_EL2 __AP1Rx_EL2(3)
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
|
||||
#include <linux/stringify.h>
|
||||
#include <asm/barrier.h>
|
||||
#include <asm/cacheflush.h>
|
||||
|
||||
#define read_gicreg read_sysreg_s
|
||||
#define write_gicreg write_sysreg_s
|
||||
#define read_gicreg(r) read_sysreg_s(SYS_ ## r)
|
||||
#define write_gicreg(v, r) write_sysreg_s(v, SYS_ ## r)
|
||||
|
||||
/*
|
||||
* Low-level accessors
|
||||
|
|
@ -93,13 +38,13 @@
|
|||
|
||||
static inline void gic_write_eoir(u32 irq)
|
||||
{
|
||||
write_sysreg_s(irq, ICC_EOIR1_EL1);
|
||||
write_sysreg_s(irq, SYS_ICC_EOIR1_EL1);
|
||||
isb();
|
||||
}
|
||||
|
||||
static inline void gic_write_dir(u32 irq)
|
||||
{
|
||||
write_sysreg_s(irq, ICC_DIR_EL1);
|
||||
write_sysreg_s(irq, SYS_ICC_DIR_EL1);
|
||||
isb();
|
||||
}
|
||||
|
||||
|
|
@ -107,7 +52,7 @@ static inline u64 gic_read_iar_common(void)
|
|||
{
|
||||
u64 irqstat;
|
||||
|
||||
irqstat = read_sysreg_s(ICC_IAR1_EL1);
|
||||
irqstat = read_sysreg_s(SYS_ICC_IAR1_EL1);
|
||||
dsb(sy);
|
||||
return irqstat;
|
||||
}
|
||||
|
|
@ -124,7 +69,7 @@ static inline u64 gic_read_iar_cavium_thunderx(void)
|
|||
u64 irqstat;
|
||||
|
||||
nops(8);
|
||||
irqstat = read_sysreg_s(ICC_IAR1_EL1);
|
||||
irqstat = read_sysreg_s(SYS_ICC_IAR1_EL1);
|
||||
nops(4);
|
||||
mb();
|
||||
|
||||
|
|
@ -133,40 +78,40 @@ static inline u64 gic_read_iar_cavium_thunderx(void)
|
|||
|
||||
static inline void gic_write_pmr(u32 val)
|
||||
{
|
||||
write_sysreg_s(val, ICC_PMR_EL1);
|
||||
write_sysreg_s(val, SYS_ICC_PMR_EL1);
|
||||
}
|
||||
|
||||
static inline void gic_write_ctlr(u32 val)
|
||||
{
|
||||
write_sysreg_s(val, ICC_CTLR_EL1);
|
||||
write_sysreg_s(val, SYS_ICC_CTLR_EL1);
|
||||
isb();
|
||||
}
|
||||
|
||||
static inline void gic_write_grpen1(u32 val)
|
||||
{
|
||||
write_sysreg_s(val, ICC_GRPEN1_EL1);
|
||||
write_sysreg_s(val, SYS_ICC_GRPEN1_EL1);
|
||||
isb();
|
||||
}
|
||||
|
||||
static inline void gic_write_sgi1r(u64 val)
|
||||
{
|
||||
write_sysreg_s(val, ICC_SGI1R_EL1);
|
||||
write_sysreg_s(val, SYS_ICC_SGI1R_EL1);
|
||||
}
|
||||
|
||||
static inline u32 gic_read_sre(void)
|
||||
{
|
||||
return read_sysreg_s(ICC_SRE_EL1);
|
||||
return read_sysreg_s(SYS_ICC_SRE_EL1);
|
||||
}
|
||||
|
||||
static inline void gic_write_sre(u32 val)
|
||||
{
|
||||
write_sysreg_s(val, ICC_SRE_EL1);
|
||||
write_sysreg_s(val, SYS_ICC_SRE_EL1);
|
||||
isb();
|
||||
}
|
||||
|
||||
static inline void gic_write_bpr1(u32 val)
|
||||
{
|
||||
asm volatile("msr_s " __stringify(ICC_BPR1_EL1) ", %0" : : "r" (val));
|
||||
write_sysreg_s(val, SYS_ICC_BPR1_EL1);
|
||||
}
|
||||
|
||||
#define gic_read_typer(c) readq_relaxed(c)
|
||||
|
|
|
|||
|
|
@ -20,9 +20,6 @@
|
|||
|
||||
#include <asm/brk-imm.h>
|
||||
|
||||
#ifdef CONFIG_GENERIC_BUG
|
||||
#define HAVE_ARCH_BUG
|
||||
|
||||
#ifdef CONFIG_DEBUG_BUGVERBOSE
|
||||
#define _BUGVERBOSE_LOCATION(file, line) __BUGVERBOSE_LOCATION(file, line)
|
||||
#define __BUGVERBOSE_LOCATION(file, line) \
|
||||
|
|
@ -36,28 +33,35 @@
|
|||
#define _BUGVERBOSE_LOCATION(file, line)
|
||||
#endif
|
||||
|
||||
#define _BUG_FLAGS(flags) __BUG_FLAGS(flags)
|
||||
#ifdef CONFIG_GENERIC_BUG
|
||||
|
||||
#define __BUG_FLAGS(flags) asm volatile ( \
|
||||
#define __BUG_ENTRY(flags) \
|
||||
".pushsection __bug_table,\"a\"\n\t" \
|
||||
".align 2\n\t" \
|
||||
"0: .long 1f - 0b\n\t" \
|
||||
_BUGVERBOSE_LOCATION(__FILE__, __LINE__) \
|
||||
".short " #flags "\n\t" \
|
||||
".popsection\n" \
|
||||
\
|
||||
"1: brk %[imm]" \
|
||||
:: [imm] "i" (BUG_BRK_IMM) \
|
||||
)
|
||||
"1: "
|
||||
#else
|
||||
#define __BUG_ENTRY(flags) ""
|
||||
#endif
|
||||
|
||||
#define BUG() do { \
|
||||
_BUG_FLAGS(0); \
|
||||
unreachable(); \
|
||||
#define __BUG_FLAGS(flags) \
|
||||
asm volatile ( \
|
||||
__BUG_ENTRY(flags) \
|
||||
"brk %[imm]" :: [imm] "i" (BUG_BRK_IMM) \
|
||||
);
|
||||
|
||||
|
||||
#define BUG() do { \
|
||||
__BUG_FLAGS(0); \
|
||||
unreachable(); \
|
||||
} while (0)
|
||||
|
||||
#define __WARN_FLAGS(flags) _BUG_FLAGS(BUGFLAG_WARNING|(flags))
|
||||
#define __WARN_FLAGS(flags) __BUG_FLAGS(BUGFLAG_WARNING|(flags))
|
||||
|
||||
#endif /* ! CONFIG_GENERIC_BUG */
|
||||
#define HAVE_ARCH_BUG
|
||||
|
||||
#include <asm-generic/bug.h>
|
||||
|
||||
|
|
|
|||
|
|
@ -16,7 +16,18 @@
|
|||
#ifndef __ASM_CACHE_H
|
||||
#define __ASM_CACHE_H
|
||||
|
||||
#include <asm/cachetype.h>
|
||||
#include <asm/cputype.h>
|
||||
|
||||
#define CTR_L1IP_SHIFT 14
|
||||
#define CTR_L1IP_MASK 3
|
||||
#define CTR_CWG_SHIFT 24
|
||||
#define CTR_CWG_MASK 15
|
||||
|
||||
#define CTR_L1IP(ctr) (((ctr) >> CTR_L1IP_SHIFT) & CTR_L1IP_MASK)
|
||||
|
||||
#define ICACHE_POLICY_VPIPT 0
|
||||
#define ICACHE_POLICY_VIPT 2
|
||||
#define ICACHE_POLICY_PIPT 3
|
||||
|
||||
#define L1_CACHE_SHIFT 7
|
||||
#define L1_CACHE_BYTES (1 << L1_CACHE_SHIFT)
|
||||
|
|
@ -32,6 +43,31 @@
|
|||
|
||||
#ifndef __ASSEMBLY__
|
||||
|
||||
#include <linux/bitops.h>
|
||||
|
||||
#define ICACHEF_ALIASING 0
|
||||
#define ICACHEF_VPIPT 1
|
||||
extern unsigned long __icache_flags;
|
||||
|
||||
/*
|
||||
* Whilst the D-side always behaves as PIPT on AArch64, aliasing is
|
||||
* permitted in the I-cache.
|
||||
*/
|
||||
static inline int icache_is_aliasing(void)
|
||||
{
|
||||
return test_bit(ICACHEF_ALIASING, &__icache_flags);
|
||||
}
|
||||
|
||||
static inline int icache_is_vpipt(void)
|
||||
{
|
||||
return test_bit(ICACHEF_VPIPT, &__icache_flags);
|
||||
}
|
||||
|
||||
static inline u32 cache_type_cwg(void)
|
||||
{
|
||||
return (read_cpuid_cachetype() >> CTR_CWG_SHIFT) & CTR_CWG_MASK;
|
||||
}
|
||||
|
||||
#define __read_mostly __attribute__((__section__(".data..read_mostly")))
|
||||
|
||||
static inline int cache_line_size(void)
|
||||
|
|
|
|||
|
|
@ -154,5 +154,6 @@ int set_memory_ro(unsigned long addr, int numpages);
|
|||
int set_memory_rw(unsigned long addr, int numpages);
|
||||
int set_memory_x(unsigned long addr, int numpages);
|
||||
int set_memory_nx(unsigned long addr, int numpages);
|
||||
int set_memory_valid(unsigned long addr, unsigned long size, int enable);
|
||||
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -1,100 +0,0 @@
|
|||
/*
|
||||
* Copyright (C) 2012 ARM Ltd.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
*/
|
||||
#ifndef __ASM_CACHETYPE_H
|
||||
#define __ASM_CACHETYPE_H
|
||||
|
||||
#include <asm/cputype.h>
|
||||
|
||||
#define CTR_L1IP_SHIFT 14
|
||||
#define CTR_L1IP_MASK 3
|
||||
#define CTR_CWG_SHIFT 24
|
||||
#define CTR_CWG_MASK 15
|
||||
|
||||
#define ICACHE_POLICY_RESERVED 0
|
||||
#define ICACHE_POLICY_AIVIVT 1
|
||||
#define ICACHE_POLICY_VIPT 2
|
||||
#define ICACHE_POLICY_PIPT 3
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
|
||||
#include <linux/bitops.h>
|
||||
|
||||
#define CTR_L1IP(ctr) (((ctr) >> CTR_L1IP_SHIFT) & CTR_L1IP_MASK)
|
||||
|
||||
#define ICACHEF_ALIASING 0
|
||||
#define ICACHEF_AIVIVT 1
|
||||
|
||||
extern unsigned long __icache_flags;
|
||||
|
||||
/*
|
||||
* NumSets, bits[27:13] - (Number of sets in cache) - 1
|
||||
* Associativity, bits[12:3] - (Associativity of cache) - 1
|
||||
* LineSize, bits[2:0] - (Log2(Number of words in cache line)) - 2
|
||||
*/
|
||||
#define CCSIDR_EL1_WRITE_THROUGH BIT(31)
|
||||
#define CCSIDR_EL1_WRITE_BACK BIT(30)
|
||||
#define CCSIDR_EL1_READ_ALLOCATE BIT(29)
|
||||
#define CCSIDR_EL1_WRITE_ALLOCATE BIT(28)
|
||||
#define CCSIDR_EL1_LINESIZE_MASK 0x7
|
||||
#define CCSIDR_EL1_LINESIZE(x) ((x) & CCSIDR_EL1_LINESIZE_MASK)
|
||||
#define CCSIDR_EL1_ASSOCIATIVITY_SHIFT 3
|
||||
#define CCSIDR_EL1_ASSOCIATIVITY_MASK 0x3ff
|
||||
#define CCSIDR_EL1_ASSOCIATIVITY(x) \
|
||||
(((x) >> CCSIDR_EL1_ASSOCIATIVITY_SHIFT) & CCSIDR_EL1_ASSOCIATIVITY_MASK)
|
||||
#define CCSIDR_EL1_NUMSETS_SHIFT 13
|
||||
#define CCSIDR_EL1_NUMSETS_MASK 0x7fff
|
||||
#define CCSIDR_EL1_NUMSETS(x) \
|
||||
(((x) >> CCSIDR_EL1_NUMSETS_SHIFT) & CCSIDR_EL1_NUMSETS_MASK)
|
||||
|
||||
#define CACHE_LINESIZE(x) (16 << CCSIDR_EL1_LINESIZE(x))
|
||||
#define CACHE_NUMSETS(x) (CCSIDR_EL1_NUMSETS(x) + 1)
|
||||
#define CACHE_ASSOCIATIVITY(x) (CCSIDR_EL1_ASSOCIATIVITY(x) + 1)
|
||||
|
||||
extern u64 __attribute_const__ cache_get_ccsidr(u64 csselr);
|
||||
|
||||
/* Helpers for Level 1 Instruction cache csselr = 1L */
|
||||
static inline int icache_get_linesize(void)
|
||||
{
|
||||
return CACHE_LINESIZE(cache_get_ccsidr(1L));
|
||||
}
|
||||
|
||||
static inline int icache_get_numsets(void)
|
||||
{
|
||||
return CACHE_NUMSETS(cache_get_ccsidr(1L));
|
||||
}
|
||||
|
||||
/*
|
||||
* Whilst the D-side always behaves as PIPT on AArch64, aliasing is
|
||||
* permitted in the I-cache.
|
||||
*/
|
||||
static inline int icache_is_aliasing(void)
|
||||
{
|
||||
return test_bit(ICACHEF_ALIASING, &__icache_flags);
|
||||
}
|
||||
|
||||
static inline int icache_is_aivivt(void)
|
||||
{
|
||||
return test_bit(ICACHEF_AIVIVT, &__icache_flags);
|
||||
}
|
||||
|
||||
static inline u32 cache_type_cwg(void)
|
||||
{
|
||||
return (read_cpuid_cachetype() >> CTR_CWG_SHIFT) & CTR_CWG_MASK;
|
||||
}
|
||||
|
||||
#endif /* __ASSEMBLY__ */
|
||||
|
||||
#endif /* __ASM_CACHETYPE_H */
|
||||
|
|
@ -226,7 +226,7 @@ void update_cpu_errata_workarounds(void);
|
|||
void __init enable_errata_workarounds(void);
|
||||
void verify_local_cpu_errata_workarounds(void);
|
||||
|
||||
u64 read_system_reg(u32 id);
|
||||
u64 read_sanitised_ftr_reg(u32 id);
|
||||
|
||||
static inline bool cpu_supports_mixed_endian_el0(void)
|
||||
{
|
||||
|
|
@ -240,7 +240,7 @@ static inline bool system_supports_32bit_el0(void)
|
|||
|
||||
static inline bool system_supports_mixed_endian_el0(void)
|
||||
{
|
||||
return id_aa64mmfr0_mixed_endian_el0(read_system_reg(SYS_ID_AA64MMFR0_EL1));
|
||||
return id_aa64mmfr0_mixed_endian_el0(read_sanitised_ftr_reg(SYS_ID_AA64MMFR0_EL1));
|
||||
}
|
||||
|
||||
static inline bool system_supports_fpsimd(void)
|
||||
|
|
|
|||
|
|
@ -177,6 +177,10 @@
|
|||
|
||||
#define ESR_ELx_SYS64_ISS_SYS_CNTVCT (ESR_ELx_SYS64_ISS_SYS_VAL(3, 3, 2, 14, 0) | \
|
||||
ESR_ELx_SYS64_ISS_DIR_READ)
|
||||
|
||||
#define ESR_ELx_SYS64_ISS_SYS_CNTFRQ (ESR_ELx_SYS64_ISS_SYS_VAL(3, 3, 0, 14, 0) | \
|
||||
ESR_ELx_SYS64_ISS_DIR_READ)
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
#include <asm/types.h>
|
||||
|
||||
|
|
|
|||
|
|
@ -20,7 +20,7 @@
|
|||
#include <linux/threads.h>
|
||||
#include <asm/irq.h>
|
||||
|
||||
#define NR_IPI 6
|
||||
#define NR_IPI 7
|
||||
|
||||
typedef struct {
|
||||
unsigned int __softirq_pending;
|
||||
|
|
|
|||
|
|
@ -149,7 +149,7 @@ static inline void ptrace_hw_copy_thread(struct task_struct *task)
|
|||
/* Determine number of BRP registers available. */
|
||||
static inline int get_num_brps(void)
|
||||
{
|
||||
u64 dfr0 = read_system_reg(SYS_ID_AA64DFR0_EL1);
|
||||
u64 dfr0 = read_sanitised_ftr_reg(SYS_ID_AA64DFR0_EL1);
|
||||
return 1 +
|
||||
cpuid_feature_extract_unsigned_field(dfr0,
|
||||
ID_AA64DFR0_BRPS_SHIFT);
|
||||
|
|
@ -158,7 +158,7 @@ static inline int get_num_brps(void)
|
|||
/* Determine number of WRP registers available. */
|
||||
static inline int get_num_wrps(void)
|
||||
{
|
||||
u64 dfr0 = read_system_reg(SYS_ID_AA64DFR0_EL1);
|
||||
u64 dfr0 = read_sanitised_ftr_reg(SYS_ID_AA64DFR0_EL1);
|
||||
return 1 +
|
||||
cpuid_feature_extract_unsigned_field(dfr0,
|
||||
ID_AA64DFR0_WRPS_SHIFT);
|
||||
|
|
|
|||
|
|
@ -40,9 +40,59 @@
|
|||
static inline void crash_setup_regs(struct pt_regs *newregs,
|
||||
struct pt_regs *oldregs)
|
||||
{
|
||||
/* Empty routine needed to avoid build errors. */
|
||||
if (oldregs) {
|
||||
memcpy(newregs, oldregs, sizeof(*newregs));
|
||||
} else {
|
||||
u64 tmp1, tmp2;
|
||||
|
||||
__asm__ __volatile__ (
|
||||
"stp x0, x1, [%2, #16 * 0]\n"
|
||||
"stp x2, x3, [%2, #16 * 1]\n"
|
||||
"stp x4, x5, [%2, #16 * 2]\n"
|
||||
"stp x6, x7, [%2, #16 * 3]\n"
|
||||
"stp x8, x9, [%2, #16 * 4]\n"
|
||||
"stp x10, x11, [%2, #16 * 5]\n"
|
||||
"stp x12, x13, [%2, #16 * 6]\n"
|
||||
"stp x14, x15, [%2, #16 * 7]\n"
|
||||
"stp x16, x17, [%2, #16 * 8]\n"
|
||||
"stp x18, x19, [%2, #16 * 9]\n"
|
||||
"stp x20, x21, [%2, #16 * 10]\n"
|
||||
"stp x22, x23, [%2, #16 * 11]\n"
|
||||
"stp x24, x25, [%2, #16 * 12]\n"
|
||||
"stp x26, x27, [%2, #16 * 13]\n"
|
||||
"stp x28, x29, [%2, #16 * 14]\n"
|
||||
"mov %0, sp\n"
|
||||
"stp x30, %0, [%2, #16 * 15]\n"
|
||||
|
||||
"/* faked current PSTATE */\n"
|
||||
"mrs %0, CurrentEL\n"
|
||||
"mrs %1, SPSEL\n"
|
||||
"orr %0, %0, %1\n"
|
||||
"mrs %1, DAIF\n"
|
||||
"orr %0, %0, %1\n"
|
||||
"mrs %1, NZCV\n"
|
||||
"orr %0, %0, %1\n"
|
||||
/* pc */
|
||||
"adr %1, 1f\n"
|
||||
"1:\n"
|
||||
"stp %1, %0, [%2, #16 * 16]\n"
|
||||
: "=&r" (tmp1), "=&r" (tmp2)
|
||||
: "r" (newregs)
|
||||
: "memory"
|
||||
);
|
||||
}
|
||||
}
|
||||
|
||||
#if defined(CONFIG_KEXEC_CORE) && defined(CONFIG_HIBERNATION)
|
||||
extern bool crash_is_nosave(unsigned long pfn);
|
||||
extern void crash_prepare_suspend(void);
|
||||
extern void crash_post_resume(void);
|
||||
#else
|
||||
static inline bool crash_is_nosave(unsigned long pfn) {return false; }
|
||||
static inline void crash_prepare_suspend(void) {}
|
||||
static inline void crash_post_resume(void) {}
|
||||
#endif
|
||||
|
||||
#endif /* __ASSEMBLY__ */
|
||||
|
||||
#endif
|
||||
|
|
|
|||
Some files were not shown because too many files have changed in this diff Show more
Loading…
Reference in a new issue