mirror of
https://github.com/a52xq-dev/kernel.git
synced 2026-10-18 21:58:11 +07:00
Merge git://git.kernel.org/pub/scm/linux/kernel/git/davem/net
Pull networking fixes from David Miller:
1) Fix list tests in netfilter ingress support, from Florian Westphal.
2) Fix reversal of input and output interfaces in ingress hook
invocation, from Pablo Neira Ayuso.
3) We have a use after free in r8169, caught by Dave Jones, fixed by
Francois Romieu.
4) Splice use-after-free fix in AF_UNIX frmo Hannes Frederic Sowa.
5) Three ipv6 route handling bug fixes from Martin KaFai Lau:
a) Don't create clone routes not managed by the fib6 tree
b) Don't forget to check expiration of DST_NOCACHE routes.
c) Handle rt->dst.from == NULL properly.
6) Several AF_PACKET fixes wrt transport header setting and SKB
protocol setting, from Daniel Borkmann.
7) Fix thunder driver crash on shutdown, from Pavel Fedin.
8) Several Mellanox driver fixes (max MTU calculations, use of correct
DMA unmap in TX path, etc.) from Saeed Mahameed, Tariq Toukan, Doron
Tsur, Achiad Shochat, Eran Ben Elisha, and Noa Osherovich.
9) Several mv88e6060 DSA driver fixes (wrong bit definitions for
certain registers, etc.) from Neil Armstrong.
10) Make sure to disable preemption while updating per-cpu stats of ip
tunnels, from Jason A. Donenfeld.
11) Various ARM64 bpf JIT fixes, from Yang Shi.
12) Flush icache properly in ARM JITs, from Daniel Borkmann.
13) Fix masking of RX and TX interrupts in ravb driver, from Masaru
Nagai.
14) Fix netdev feature propagation for devices not implementing
->ndo_set_features(). From Nikolay Aleksandrov.
15) Big endian fix in vmxnet3 driver, from Shrikrishna Khare.
16) RAW socket code increments incorrect SNMP counters, fix from Ben
Cartwright-Cox.
17) IPv6 multicast SNMP counters are bumped twice, fix from Neil Horman.
18) Fix handling of VLAN headers on stacked devices when REORDER is
disabled. From Vlad Yasevich.
19) Fix SKB leaks and use-after-free in ipvlan and macvlan drivers, from
Sabrina Dubroca.
* git://git.kernel.org/pub/scm/linux/kernel/git/davem/net: (83 commits)
MAINTAINERS: Update Mellanox's Eth NIC driver entries
net/core: revert "net: fix __netdev_update_features return.." and add comment
af_unix: take receive queue lock while appending new skb
rtnetlink: fix frame size warning in rtnl_fill_ifinfo
net: use skb_clone to avoid alloc_pages failure.
packet: Use PAGE_ALIGNED macro
packet: Don't check frames_per_block against negative values
net: phy: Use interrupts when available in NOLINK state
phy: marvell: Add support for 88E1540 PHY
arm64: bpf: make BPF prologue and epilogue align with ARM64 AAPCS
macvlan: fix leak in macvlan_handle_frame
ipvlan: fix use after free of skb
ipvlan: fix leak in ipvlan_rcv_frame
vlan: Do not put vlan headers back on bridge and macvlan ports
vlan: Fix untag operations of stacked vlans with REORDER_HEADER off
via-velocity: unconditionally drop frames with bad l2 length
ipg: Remove ipg driver
dl2k: Add support for IP1000A-based cards
snmp: Remove duplicate OUTMCAST stat increment
net: thunder: Check for driver data in nicvf_remove()
...
This commit is contained in:
Linus Torvalds
commit
7f151f1d8a
84 changed files with 1036 additions and 3650 deletions
17
MAINTAINERS
17
MAINTAINERS
|
|
@ -5711,13 +5711,6 @@ M: Juanjo Ciarlante <jjciarla@raiz.uncu.edu.ar>
|
|||
S: Maintained
|
||||
F: net/ipv4/netfilter/ipt_MASQUERADE.c
|
||||
|
||||
IP1000A 10/100/1000 GIGABIT ETHERNET DRIVER
|
||||
M: Francois Romieu <romieu@fr.zoreil.com>
|
||||
M: Sorbica Shieh <sorbica@icplus.com.tw>
|
||||
L: netdev@vger.kernel.org
|
||||
S: Maintained
|
||||
F: drivers/net/ethernet/icplus/ipg.*
|
||||
|
||||
IPATH DRIVER
|
||||
M: Mike Marciniszyn <infinipath@intel.com>
|
||||
L: linux-rdma@vger.kernel.org
|
||||
|
|
@ -6923,13 +6916,21 @@ F: drivers/scsi/megaraid.*
|
|||
F: drivers/scsi/megaraid/
|
||||
|
||||
MELLANOX ETHERNET DRIVER (mlx4_en)
|
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M: Amir Vadai <amirv@mellanox.com>
|
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M: Eugenia Emantayev <eugenia@mellanox.com>
|
||||
L: netdev@vger.kernel.org
|
||||
S: Supported
|
||||
W: http://www.mellanox.com
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Q: http://patchwork.ozlabs.org/project/netdev/list/
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F: drivers/net/ethernet/mellanox/mlx4/en_*
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MELLANOX ETHERNET DRIVER (mlx5e)
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M: Saeed Mahameed <saeedm@mellanox.com>
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||||
L: netdev@vger.kernel.org
|
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S: Supported
|
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W: http://www.mellanox.com
|
||||
Q: http://patchwork.ozlabs.org/project/netdev/list/
|
||||
F: drivers/net/ethernet/mellanox/mlx5/core/en_*
|
||||
|
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MELLANOX ETHERNET SWITCH DRIVERS
|
||||
M: Jiri Pirko <jiri@mellanox.com>
|
||||
M: Ido Schimmel <idosch@mellanox.com>
|
||||
|
|
|
|||
|
|
@ -1061,7 +1061,7 @@ void bpf_jit_compile(struct bpf_prog *fp)
|
|||
}
|
||||
build_epilogue(&ctx);
|
||||
|
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flush_icache_range((u32)ctx.target, (u32)(ctx.target + ctx.idx));
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flush_icache_range((u32)header, (u32)(ctx.target + ctx.idx));
|
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|
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#if __LINUX_ARM_ARCH__ < 7
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if (ctx.imm_count)
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|
|
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|||
|
|
@ -50,7 +50,7 @@ static const int bpf2a64[] = {
|
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[BPF_REG_8] = A64_R(21),
|
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[BPF_REG_9] = A64_R(22),
|
||||
/* read-only frame pointer to access stack */
|
||||
[BPF_REG_FP] = A64_FP,
|
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[BPF_REG_FP] = A64_R(25),
|
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/* temporary register for internal BPF JIT */
|
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[TMP_REG_1] = A64_R(23),
|
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[TMP_REG_2] = A64_R(24),
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|
|
@ -155,18 +155,49 @@ static void build_prologue(struct jit_ctx *ctx)
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stack_size += 4; /* extra for skb_copy_bits buffer */
|
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stack_size = STACK_ALIGN(stack_size);
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|
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/*
|
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* BPF prog stack layout
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*
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* high
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* original A64_SP => 0:+-----+ BPF prologue
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* |FP/LR|
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* current A64_FP => -16:+-----+
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* | ... | callee saved registers
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* +-----+
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* | | x25/x26
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* BPF fp register => -80:+-----+
|
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* | |
|
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* | ... | BPF prog stack
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* | |
|
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* | |
|
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* current A64_SP => +-----+
|
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* | |
|
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* | ... | Function call stack
|
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* | |
|
||||
* +-----+
|
||||
* low
|
||||
*
|
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*/
|
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|
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/* Save FP and LR registers to stay align with ARM64 AAPCS */
|
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emit(A64_PUSH(A64_FP, A64_LR, A64_SP), ctx);
|
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emit(A64_MOV(1, A64_FP, A64_SP), ctx);
|
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|
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/* Save callee-saved register */
|
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emit(A64_PUSH(r6, r7, A64_SP), ctx);
|
||||
emit(A64_PUSH(r8, r9, A64_SP), ctx);
|
||||
if (ctx->tmp_used)
|
||||
emit(A64_PUSH(tmp1, tmp2, A64_SP), ctx);
|
||||
|
||||
/* Set up BPF stack */
|
||||
emit(A64_SUB_I(1, A64_SP, A64_SP, stack_size), ctx);
|
||||
/* Save fp (x25) and x26. SP requires 16 bytes alignment */
|
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emit(A64_PUSH(fp, A64_R(26), A64_SP), ctx);
|
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|
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/* Set up frame pointer */
|
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/* Set up BPF prog stack base register (x25) */
|
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emit(A64_MOV(1, fp, A64_SP), ctx);
|
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|
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/* Set up function call stack */
|
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emit(A64_SUB_I(1, A64_SP, A64_SP, stack_size), ctx);
|
||||
|
||||
/* Clear registers A and X */
|
||||
emit_a64_mov_i64(ra, 0, ctx);
|
||||
emit_a64_mov_i64(rx, 0, ctx);
|
||||
|
|
@ -190,14 +221,17 @@ static void build_epilogue(struct jit_ctx *ctx)
|
|||
/* We're done with BPF stack */
|
||||
emit(A64_ADD_I(1, A64_SP, A64_SP, stack_size), ctx);
|
||||
|
||||
/* Restore fs (x25) and x26 */
|
||||
emit(A64_POP(fp, A64_R(26), A64_SP), ctx);
|
||||
|
||||
/* Restore callee-saved register */
|
||||
if (ctx->tmp_used)
|
||||
emit(A64_POP(tmp1, tmp2, A64_SP), ctx);
|
||||
emit(A64_POP(r8, r9, A64_SP), ctx);
|
||||
emit(A64_POP(r6, r7, A64_SP), ctx);
|
||||
|
||||
/* Restore frame pointer */
|
||||
emit(A64_MOV(1, fp, A64_SP), ctx);
|
||||
/* Restore FP/LR registers */
|
||||
emit(A64_POP(A64_FP, A64_LR, A64_SP), ctx);
|
||||
|
||||
/* Set return value */
|
||||
emit(A64_MOV(1, A64_R(0), r0), ctx);
|
||||
|
|
@ -758,7 +792,7 @@ void bpf_int_jit_compile(struct bpf_prog *prog)
|
|||
if (bpf_jit_enable > 1)
|
||||
bpf_jit_dump(prog->len, image_size, 2, ctx.image);
|
||||
|
||||
bpf_flush_icache(ctx.image, ctx.image + ctx.idx);
|
||||
bpf_flush_icache(header, ctx.image + ctx.idx);
|
||||
|
||||
set_memory_ro((unsigned long)header, header->pages);
|
||||
prog->bpf_func = (void *)ctx.image;
|
||||
|
|
|
|||
|
|
@ -15,9 +15,7 @@
|
|||
#include <linux/netdevice.h>
|
||||
#include <linux/phy.h>
|
||||
#include <net/dsa.h>
|
||||
|
||||
#define REG_PORT(p) (8 + (p))
|
||||
#define REG_GLOBAL 0x0f
|
||||
#include "mv88e6060.h"
|
||||
|
||||
static int reg_read(struct dsa_switch *ds, int addr, int reg)
|
||||
{
|
||||
|
|
@ -67,13 +65,14 @@ static char *mv88e6060_probe(struct device *host_dev, int sw_addr)
|
|||
if (bus == NULL)
|
||||
return NULL;
|
||||
|
||||
ret = mdiobus_read(bus, sw_addr + REG_PORT(0), 0x03);
|
||||
ret = mdiobus_read(bus, sw_addr + REG_PORT(0), PORT_SWITCH_ID);
|
||||
if (ret >= 0) {
|
||||
if (ret == 0x0600)
|
||||
if (ret == PORT_SWITCH_ID_6060)
|
||||
return "Marvell 88E6060 (A0)";
|
||||
if (ret == 0x0601 || ret == 0x0602)
|
||||
if (ret == PORT_SWITCH_ID_6060_R1 ||
|
||||
ret == PORT_SWITCH_ID_6060_R2)
|
||||
return "Marvell 88E6060 (B0)";
|
||||
if ((ret & 0xfff0) == 0x0600)
|
||||
if ((ret & PORT_SWITCH_ID_6060_MASK) == PORT_SWITCH_ID_6060)
|
||||
return "Marvell 88E6060";
|
||||
}
|
||||
|
||||
|
|
@ -87,22 +86,26 @@ static int mv88e6060_switch_reset(struct dsa_switch *ds)
|
|||
unsigned long timeout;
|
||||
|
||||
/* Set all ports to the disabled state. */
|
||||
for (i = 0; i < 6; i++) {
|
||||
ret = REG_READ(REG_PORT(i), 0x04);
|
||||
REG_WRITE(REG_PORT(i), 0x04, ret & 0xfffc);
|
||||
for (i = 0; i < MV88E6060_PORTS; i++) {
|
||||
ret = REG_READ(REG_PORT(i), PORT_CONTROL);
|
||||
REG_WRITE(REG_PORT(i), PORT_CONTROL,
|
||||
ret & ~PORT_CONTROL_STATE_MASK);
|
||||
}
|
||||
|
||||
/* Wait for transmit queues to drain. */
|
||||
usleep_range(2000, 4000);
|
||||
|
||||
/* Reset the switch. */
|
||||
REG_WRITE(REG_GLOBAL, 0x0a, 0xa130);
|
||||
REG_WRITE(REG_GLOBAL, GLOBAL_ATU_CONTROL,
|
||||
GLOBAL_ATU_CONTROL_SWRESET |
|
||||
GLOBAL_ATU_CONTROL_ATUSIZE_1024 |
|
||||
GLOBAL_ATU_CONTROL_ATE_AGE_5MIN);
|
||||
|
||||
/* Wait up to one second for reset to complete. */
|
||||
timeout = jiffies + 1 * HZ;
|
||||
while (time_before(jiffies, timeout)) {
|
||||
ret = REG_READ(REG_GLOBAL, 0x00);
|
||||
if ((ret & 0x8000) == 0x0000)
|
||||
ret = REG_READ(REG_GLOBAL, GLOBAL_STATUS);
|
||||
if (ret & GLOBAL_STATUS_INIT_READY)
|
||||
break;
|
||||
|
||||
usleep_range(1000, 2000);
|
||||
|
|
@ -119,13 +122,15 @@ static int mv88e6060_setup_global(struct dsa_switch *ds)
|
|||
* set the maximum frame size to 1536 bytes, and mask all
|
||||
* interrupt sources.
|
||||
*/
|
||||
REG_WRITE(REG_GLOBAL, 0x04, 0x0800);
|
||||
REG_WRITE(REG_GLOBAL, GLOBAL_CONTROL, GLOBAL_CONTROL_MAX_FRAME_1536);
|
||||
|
||||
/* Enable automatic address learning, set the address
|
||||
* database size to 1024 entries, and set the default aging
|
||||
* time to 5 minutes.
|
||||
*/
|
||||
REG_WRITE(REG_GLOBAL, 0x0a, 0x2130);
|
||||
REG_WRITE(REG_GLOBAL, GLOBAL_ATU_CONTROL,
|
||||
GLOBAL_ATU_CONTROL_ATUSIZE_1024 |
|
||||
GLOBAL_ATU_CONTROL_ATE_AGE_5MIN);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -139,25 +144,30 @@ static int mv88e6060_setup_port(struct dsa_switch *ds, int p)
|
|||
* state to Forwarding. Additionally, if this is the CPU
|
||||
* port, enable Ingress and Egress Trailer tagging mode.
|
||||
*/
|
||||
REG_WRITE(addr, 0x04, dsa_is_cpu_port(ds, p) ? 0x4103 : 0x0003);
|
||||
REG_WRITE(addr, PORT_CONTROL,
|
||||
dsa_is_cpu_port(ds, p) ?
|
||||
PORT_CONTROL_TRAILER |
|
||||
PORT_CONTROL_INGRESS_MODE |
|
||||
PORT_CONTROL_STATE_FORWARDING :
|
||||
PORT_CONTROL_STATE_FORWARDING);
|
||||
|
||||
/* Port based VLAN map: give each port its own address
|
||||
* database, allow the CPU port to talk to each of the 'real'
|
||||
* ports, and allow each of the 'real' ports to only talk to
|
||||
* the CPU port.
|
||||
*/
|
||||
REG_WRITE(addr, 0x06,
|
||||
((p & 0xf) << 12) |
|
||||
(dsa_is_cpu_port(ds, p) ?
|
||||
ds->phys_port_mask :
|
||||
(1 << ds->dst->cpu_port)));
|
||||
REG_WRITE(addr, PORT_VLAN_MAP,
|
||||
((p & 0xf) << PORT_VLAN_MAP_DBNUM_SHIFT) |
|
||||
(dsa_is_cpu_port(ds, p) ?
|
||||
ds->phys_port_mask :
|
||||
BIT(ds->dst->cpu_port)));
|
||||
|
||||
/* Port Association Vector: when learning source addresses
|
||||
* of packets, add the address to the address database using
|
||||
* a port bitmap that has only the bit for this port set and
|
||||
* the other bits clear.
|
||||
*/
|
||||
REG_WRITE(addr, 0x0b, 1 << p);
|
||||
REG_WRITE(addr, PORT_ASSOC_VECTOR, BIT(p));
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -177,7 +187,7 @@ static int mv88e6060_setup(struct dsa_switch *ds)
|
|||
if (ret < 0)
|
||||
return ret;
|
||||
|
||||
for (i = 0; i < 6; i++) {
|
||||
for (i = 0; i < MV88E6060_PORTS; i++) {
|
||||
ret = mv88e6060_setup_port(ds, i);
|
||||
if (ret < 0)
|
||||
return ret;
|
||||
|
|
@ -188,16 +198,17 @@ static int mv88e6060_setup(struct dsa_switch *ds)
|
|||
|
||||
static int mv88e6060_set_addr(struct dsa_switch *ds, u8 *addr)
|
||||
{
|
||||
REG_WRITE(REG_GLOBAL, 0x01, (addr[0] << 8) | addr[1]);
|
||||
REG_WRITE(REG_GLOBAL, 0x02, (addr[2] << 8) | addr[3]);
|
||||
REG_WRITE(REG_GLOBAL, 0x03, (addr[4] << 8) | addr[5]);
|
||||
/* Use the same MAC Address as FD Pause frames for all ports */
|
||||
REG_WRITE(REG_GLOBAL, GLOBAL_MAC_01, (addr[0] << 9) | addr[1]);
|
||||
REG_WRITE(REG_GLOBAL, GLOBAL_MAC_23, (addr[2] << 8) | addr[3]);
|
||||
REG_WRITE(REG_GLOBAL, GLOBAL_MAC_45, (addr[4] << 8) | addr[5]);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int mv88e6060_port_to_phy_addr(int port)
|
||||
{
|
||||
if (port >= 0 && port <= 5)
|
||||
if (port >= 0 && port < MV88E6060_PORTS)
|
||||
return port;
|
||||
return -1;
|
||||
}
|
||||
|
|
@ -225,54 +236,6 @@ mv88e6060_phy_write(struct dsa_switch *ds, int port, int regnum, u16 val)
|
|||
return reg_write(ds, addr, regnum, val);
|
||||
}
|
||||
|
||||
static void mv88e6060_poll_link(struct dsa_switch *ds)
|
||||
{
|
||||
int i;
|
||||
|
||||
for (i = 0; i < DSA_MAX_PORTS; i++) {
|
||||
struct net_device *dev;
|
||||
int uninitialized_var(port_status);
|
||||
int link;
|
||||
int speed;
|
||||
int duplex;
|
||||
int fc;
|
||||
|
||||
dev = ds->ports[i];
|
||||
if (dev == NULL)
|
||||
continue;
|
||||
|
||||
link = 0;
|
||||
if (dev->flags & IFF_UP) {
|
||||
port_status = reg_read(ds, REG_PORT(i), 0x00);
|
||||
if (port_status < 0)
|
||||
continue;
|
||||
|
||||
link = !!(port_status & 0x1000);
|
||||
}
|
||||
|
||||
if (!link) {
|
||||
if (netif_carrier_ok(dev)) {
|
||||
netdev_info(dev, "link down\n");
|
||||
netif_carrier_off(dev);
|
||||
}
|
||||
continue;
|
||||
}
|
||||
|
||||
speed = (port_status & 0x0100) ? 100 : 10;
|
||||
duplex = (port_status & 0x0200) ? 1 : 0;
|
||||
fc = ((port_status & 0xc000) == 0xc000) ? 1 : 0;
|
||||
|
||||
if (!netif_carrier_ok(dev)) {
|
||||
netdev_info(dev,
|
||||
"link up, %d Mb/s, %s duplex, flow control %sabled\n",
|
||||
speed,
|
||||
duplex ? "full" : "half",
|
||||
fc ? "en" : "dis");
|
||||
netif_carrier_on(dev);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
static struct dsa_switch_driver mv88e6060_switch_driver = {
|
||||
.tag_protocol = DSA_TAG_PROTO_TRAILER,
|
||||
.probe = mv88e6060_probe,
|
||||
|
|
@ -280,7 +243,6 @@ static struct dsa_switch_driver mv88e6060_switch_driver = {
|
|||
.set_addr = mv88e6060_set_addr,
|
||||
.phy_read = mv88e6060_phy_read,
|
||||
.phy_write = mv88e6060_phy_write,
|
||||
.poll_link = mv88e6060_poll_link,
|
||||
};
|
||||
|
||||
static int __init mv88e6060_init(void)
|
||||
|
|
|
|||
111
drivers/net/dsa/mv88e6060.h
Normal file
111
drivers/net/dsa/mv88e6060.h
Normal file
|
|
@ -0,0 +1,111 @@
|
|||
/*
|
||||
* drivers/net/dsa/mv88e6060.h - Marvell 88e6060 switch chip support
|
||||
* Copyright (c) 2015 Neil Armstrong
|
||||
*
|
||||
* Based on mv88e6xxx.h
|
||||
* Copyright (c) 2008 Marvell Semiconductor
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*/
|
||||
|
||||
#ifndef __MV88E6060_H
|
||||
#define __MV88E6060_H
|
||||
|
||||
#define MV88E6060_PORTS 6
|
||||
|
||||
#define REG_PORT(p) (0x8 + (p))
|
||||
#define PORT_STATUS 0x00
|
||||
#define PORT_STATUS_PAUSE_EN BIT(15)
|
||||
#define PORT_STATUS_MY_PAUSE BIT(14)
|
||||
#define PORT_STATUS_FC (PORT_STATUS_MY_PAUSE | PORT_STATUS_PAUSE_EN)
|
||||
#define PORT_STATUS_RESOLVED BIT(13)
|
||||
#define PORT_STATUS_LINK BIT(12)
|
||||
#define PORT_STATUS_PORTMODE BIT(11)
|
||||
#define PORT_STATUS_PHYMODE BIT(10)
|
||||
#define PORT_STATUS_DUPLEX BIT(9)
|
||||
#define PORT_STATUS_SPEED BIT(8)
|
||||
#define PORT_SWITCH_ID 0x03
|
||||
#define PORT_SWITCH_ID_6060 0x0600
|
||||
#define PORT_SWITCH_ID_6060_MASK 0xfff0
|
||||
#define PORT_SWITCH_ID_6060_R1 0x0601
|
||||
#define PORT_SWITCH_ID_6060_R2 0x0602
|
||||
#define PORT_CONTROL 0x04
|
||||
#define PORT_CONTROL_FORCE_FLOW_CTRL BIT(15)
|
||||
#define PORT_CONTROL_TRAILER BIT(14)
|
||||
#define PORT_CONTROL_HEADER BIT(11)
|
||||
#define PORT_CONTROL_INGRESS_MODE BIT(8)
|
||||
#define PORT_CONTROL_VLAN_TUNNEL BIT(7)
|
||||
#define PORT_CONTROL_STATE_MASK 0x03
|
||||
#define PORT_CONTROL_STATE_DISABLED 0x00
|
||||
#define PORT_CONTROL_STATE_BLOCKING 0x01
|
||||
#define PORT_CONTROL_STATE_LEARNING 0x02
|
||||
#define PORT_CONTROL_STATE_FORWARDING 0x03
|
||||
#define PORT_VLAN_MAP 0x06
|
||||
#define PORT_VLAN_MAP_DBNUM_SHIFT 12
|
||||
#define PORT_VLAN_MAP_TABLE_MASK 0x1f
|
||||
#define PORT_ASSOC_VECTOR 0x0b
|
||||
#define PORT_ASSOC_VECTOR_MONITOR BIT(15)
|
||||
#define PORT_ASSOC_VECTOR_PAV_MASK 0x1f
|
||||
#define PORT_RX_CNTR 0x10
|
||||
#define PORT_TX_CNTR 0x11
|
||||
|
||||
#define REG_GLOBAL 0x0f
|
||||
#define GLOBAL_STATUS 0x00
|
||||
#define GLOBAL_STATUS_SW_MODE_MASK (0x3 << 12)
|
||||
#define GLOBAL_STATUS_SW_MODE_0 (0x0 << 12)
|
||||
#define GLOBAL_STATUS_SW_MODE_1 (0x1 << 12)
|
||||
#define GLOBAL_STATUS_SW_MODE_2 (0x2 << 12)
|
||||
#define GLOBAL_STATUS_SW_MODE_3 (0x3 << 12)
|
||||
#define GLOBAL_STATUS_INIT_READY BIT(11)
|
||||
#define GLOBAL_STATUS_ATU_FULL BIT(3)
|
||||
#define GLOBAL_STATUS_ATU_DONE BIT(2)
|
||||
#define GLOBAL_STATUS_PHY_INT BIT(1)
|
||||
#define GLOBAL_STATUS_EEINT BIT(0)
|
||||
#define GLOBAL_MAC_01 0x01
|
||||
#define GLOBAL_MAC_01_DIFF_ADDR BIT(8)
|
||||
#define GLOBAL_MAC_23 0x02
|
||||
#define GLOBAL_MAC_45 0x03
|
||||
#define GLOBAL_CONTROL 0x04
|
||||
#define GLOBAL_CONTROL_DISCARD_EXCESS BIT(13)
|
||||
#define GLOBAL_CONTROL_MAX_FRAME_1536 BIT(10)
|
||||
#define GLOBAL_CONTROL_RELOAD_EEPROM BIT(9)
|
||||
#define GLOBAL_CONTROL_CTRMODE BIT(8)
|
||||
#define GLOBAL_CONTROL_ATU_FULL_EN BIT(3)
|
||||
#define GLOBAL_CONTROL_ATU_DONE_EN BIT(2)
|
||||
#define GLOBAL_CONTROL_PHYINT_EN BIT(1)
|
||||
#define GLOBAL_CONTROL_EEPROM_DONE_EN BIT(0)
|
||||
#define GLOBAL_ATU_CONTROL 0x0a
|
||||
#define GLOBAL_ATU_CONTROL_SWRESET BIT(15)
|
||||
#define GLOBAL_ATU_CONTROL_LEARNDIS BIT(14)
|
||||
#define GLOBAL_ATU_CONTROL_ATUSIZE_256 (0x0 << 12)
|
||||
#define GLOBAL_ATU_CONTROL_ATUSIZE_512 (0x1 << 12)
|
||||
#define GLOBAL_ATU_CONTROL_ATUSIZE_1024 (0x2 << 12)
|
||||
#define GLOBAL_ATU_CONTROL_ATE_AGE_SHIFT 4
|
||||
#define GLOBAL_ATU_CONTROL_ATE_AGE_MASK (0xff << 4)
|
||||
#define GLOBAL_ATU_CONTROL_ATE_AGE_5MIN (0x13 << 4)
|
||||
#define GLOBAL_ATU_OP 0x0b
|
||||
#define GLOBAL_ATU_OP_BUSY BIT(15)
|
||||
#define GLOBAL_ATU_OP_NOP (0 << 12)
|
||||
#define GLOBAL_ATU_OP_FLUSH_ALL ((1 << 12) | GLOBAL_ATU_OP_BUSY)
|
||||
#define GLOBAL_ATU_OP_FLUSH_UNLOCKED ((2 << 12) | GLOBAL_ATU_OP_BUSY)
|
||||
#define GLOBAL_ATU_OP_LOAD_DB ((3 << 12) | GLOBAL_ATU_OP_BUSY)
|
||||
#define GLOBAL_ATU_OP_GET_NEXT_DB ((4 << 12) | GLOBAL_ATU_OP_BUSY)
|
||||
#define GLOBAL_ATU_OP_FLUSH_DB ((5 << 12) | GLOBAL_ATU_OP_BUSY)
|
||||
#define GLOBAL_ATU_OP_FLUSH_UNLOCKED_DB ((6 << 12) | GLOBAL_ATU_OP_BUSY)
|
||||
#define GLOBAL_ATU_DATA 0x0c
|
||||
#define GLOBAL_ATU_DATA_PORT_VECTOR_MASK 0x3f0
|
||||
#define GLOBAL_ATU_DATA_PORT_VECTOR_SHIFT 4
|
||||
#define GLOBAL_ATU_DATA_STATE_MASK 0x0f
|
||||
#define GLOBAL_ATU_DATA_STATE_UNUSED 0x00
|
||||
#define GLOBAL_ATU_DATA_STATE_UC_STATIC 0x0e
|
||||
#define GLOBAL_ATU_DATA_STATE_UC_LOCKED 0x0f
|
||||
#define GLOBAL_ATU_DATA_STATE_MC_STATIC 0x07
|
||||
#define GLOBAL_ATU_DATA_STATE_MC_LOCKED 0x0e
|
||||
#define GLOBAL_ATU_MAC_01 0x0d
|
||||
#define GLOBAL_ATU_MAC_23 0x0e
|
||||
#define GLOBAL_ATU_MAC_45 0x0f
|
||||
|
||||
#endif
|
||||
|
|
@ -78,7 +78,6 @@ source "drivers/net/ethernet/ibm/Kconfig"
|
|||
source "drivers/net/ethernet/intel/Kconfig"
|
||||
source "drivers/net/ethernet/i825xx/Kconfig"
|
||||
source "drivers/net/ethernet/xscale/Kconfig"
|
||||
source "drivers/net/ethernet/icplus/Kconfig"
|
||||
|
||||
config JME
|
||||
tristate "JMicron(R) PCI-Express Gigabit Ethernet support"
|
||||
|
|
|
|||
|
|
@ -41,7 +41,6 @@ obj-$(CONFIG_NET_VENDOR_IBM) += ibm/
|
|||
obj-$(CONFIG_NET_VENDOR_INTEL) += intel/
|
||||
obj-$(CONFIG_NET_VENDOR_I825XX) += i825xx/
|
||||
obj-$(CONFIG_NET_VENDOR_XSCALE) += xscale/
|
||||
obj-$(CONFIG_IP1000) += icplus/
|
||||
obj-$(CONFIG_JME) += jme.o
|
||||
obj-$(CONFIG_KORINA) += korina.o
|
||||
obj-$(CONFIG_LANTIQ_ETOP) += lantiq_etop.o
|
||||
|
|
|
|||
|
|
@ -13207,7 +13207,7 @@ static int bnx2x_init_dev(struct bnx2x *bp, struct pci_dev *pdev,
|
|||
|
||||
/* VF with OLD Hypervisor or old PF do not support filtering */
|
||||
if (IS_PF(bp)) {
|
||||
if (CHIP_IS_E1x(bp))
|
||||
if (chip_is_e1x)
|
||||
bp->accept_any_vlan = true;
|
||||
else
|
||||
dev->hw_features |= NETIF_F_HW_VLAN_CTAG_FILTER;
|
||||
|
|
|
|||
|
|
@ -560,7 +560,7 @@ static int liquidio_resume(struct pci_dev *pdev)
|
|||
#endif
|
||||
|
||||
/* For PCI-E Advanced Error Recovery (AER) Interface */
|
||||
static struct pci_error_handlers liquidio_err_handler = {
|
||||
static const struct pci_error_handlers liquidio_err_handler = {
|
||||
.error_detected = liquidio_pcie_error_detected,
|
||||
.mmio_enabled = liquidio_pcie_mmio_enabled,
|
||||
.slot_reset = liquidio_pcie_slot_reset,
|
||||
|
|
|
|||
|
|
@ -1583,8 +1583,14 @@ err_disable_device:
|
|||
static void nicvf_remove(struct pci_dev *pdev)
|
||||
{
|
||||
struct net_device *netdev = pci_get_drvdata(pdev);
|
||||
struct nicvf *nic = netdev_priv(netdev);
|
||||
struct net_device *pnetdev = nic->pnicvf->netdev;
|
||||
struct nicvf *nic;
|
||||
struct net_device *pnetdev;
|
||||
|
||||
if (!netdev)
|
||||
return;
|
||||
|
||||
nic = netdev_priv(netdev);
|
||||
pnetdev = nic->pnicvf->netdev;
|
||||
|
||||
/* Check if this Qset is assigned to different VF.
|
||||
* If yes, clean primary and all secondary Qsets.
|
||||
|
|
|
|||
|
|
@ -17,15 +17,16 @@ config NET_VENDOR_DLINK
|
|||
if NET_VENDOR_DLINK
|
||||
|
||||
config DL2K
|
||||
tristate "DL2000/TC902x-based Gigabit Ethernet support"
|
||||
tristate "DL2000/TC902x/IP1000A-based Gigabit Ethernet support"
|
||||
depends on PCI
|
||||
select CRC32
|
||||
---help---
|
||||
This driver supports DL2000/TC902x-based Gigabit ethernet cards,
|
||||
This driver supports DL2000/TC902x/IP1000A-based Gigabit ethernet cards,
|
||||
which includes
|
||||
D-Link DGE-550T Gigabit Ethernet Adapter.
|
||||
D-Link DL2000-based Gigabit Ethernet Adapter.
|
||||
Sundance/Tamarack TC902x Gigabit Ethernet Adapter.
|
||||
ICPlus IP1000A-based cards
|
||||
|
||||
To compile this driver as a module, choose M here: the
|
||||
module will be called dl2k.
|
||||
|
|
|
|||
|
|
@ -253,6 +253,19 @@ rio_probe1 (struct pci_dev *pdev, const struct pci_device_id *ent)
|
|||
if (err)
|
||||
goto err_out_unmap_rx;
|
||||
|
||||
if (np->chip_id == CHIP_IP1000A &&
|
||||
(np->pdev->revision == 0x40 || np->pdev->revision == 0x41)) {
|
||||
/* PHY magic taken from ipg driver, undocumented registers */
|
||||
mii_write(dev, np->phy_addr, 31, 0x0001);
|
||||
mii_write(dev, np->phy_addr, 27, 0x01e0);
|
||||
mii_write(dev, np->phy_addr, 31, 0x0002);
|
||||
mii_write(dev, np->phy_addr, 27, 0xeb8e);
|
||||
mii_write(dev, np->phy_addr, 31, 0x0000);
|
||||
mii_write(dev, np->phy_addr, 30, 0x005e);
|
||||
/* advertise 1000BASE-T half & full duplex, prefer MASTER */
|
||||
mii_write(dev, np->phy_addr, MII_CTRL1000, 0x0700);
|
||||
}
|
||||
|
||||
/* Fiber device? */
|
||||
np->phy_media = (dr16(ASICCtrl) & PhyMedia) ? 1 : 0;
|
||||
np->link_status = 0;
|
||||
|
|
@ -361,6 +374,11 @@ parse_eeprom (struct net_device *dev)
|
|||
for (i = 0; i < 6; i++)
|
||||
dev->dev_addr[i] = psrom->mac_addr[i];
|
||||
|
||||
if (np->chip_id == CHIP_IP1000A) {
|
||||
np->led_mode = psrom->led_mode;
|
||||
return 0;
|
||||
}
|
||||
|
||||
if (np->pdev->vendor != PCI_VENDOR_ID_DLINK) {
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -406,6 +424,28 @@ parse_eeprom (struct net_device *dev)
|
|||
return 0;
|
||||
}
|
||||
|
||||
static void rio_set_led_mode(struct net_device *dev)
|
||||
{
|
||||
struct netdev_private *np = netdev_priv(dev);
|
||||
void __iomem *ioaddr = np->ioaddr;
|
||||
u32 mode;
|
||||
|
||||
if (np->chip_id != CHIP_IP1000A)
|
||||
return;
|
||||
|
||||
mode = dr32(ASICCtrl);
|
||||
mode &= ~(IPG_AC_LED_MODE_BIT_1 | IPG_AC_LED_MODE | IPG_AC_LED_SPEED);
|
||||
|
||||
if (np->led_mode & 0x01)
|
||||
mode |= IPG_AC_LED_MODE;
|
||||
if (np->led_mode & 0x02)
|
||||
mode |= IPG_AC_LED_MODE_BIT_1;
|
||||
if (np->led_mode & 0x08)
|
||||
mode |= IPG_AC_LED_SPEED;
|
||||
|
||||
dw32(ASICCtrl, mode);
|
||||
}
|
||||
|
||||
static int
|
||||
rio_open (struct net_device *dev)
|
||||
{
|
||||
|
|
@ -424,6 +464,8 @@ rio_open (struct net_device *dev)
|
|||
GlobalReset | DMAReset | FIFOReset | NetworkReset | HostReset);
|
||||
mdelay(10);
|
||||
|
||||
rio_set_led_mode(dev);
|
||||
|
||||
/* DebugCtrl bit 4, 5, 9 must set */
|
||||
dw32(DebugCtrl, dr32(DebugCtrl) | 0x0230);
|
||||
|
||||
|
|
@ -433,9 +475,13 @@ rio_open (struct net_device *dev)
|
|||
|
||||
alloc_list (dev);
|
||||
|
||||
/* Get station address */
|
||||
for (i = 0; i < 6; i++)
|
||||
dw8(StationAddr0 + i, dev->dev_addr[i]);
|
||||
/* Set station address */
|
||||
/* 16 or 32-bit access is required by TC9020 datasheet but 8-bit works
|
||||
* too. However, it doesn't work on IP1000A so we use 16-bit access.
|
||||
*/
|
||||
for (i = 0; i < 3; i++)
|
||||
dw16(StationAddr0 + 2 * i,
|
||||
cpu_to_le16(((u16 *)dev->dev_addr)[i]));
|
||||
|
||||
set_multicast (dev);
|
||||
if (np->coalesce) {
|
||||
|
|
@ -780,6 +826,7 @@ tx_error (struct net_device *dev, int tx_status)
|
|||
break;
|
||||
mdelay (1);
|
||||
}
|
||||
rio_set_led_mode(dev);
|
||||
rio_free_tx (dev, 1);
|
||||
/* Reset TFDListPtr */
|
||||
dw32(TFDListPtr0, np->tx_ring_dma +
|
||||
|
|
@ -799,6 +846,7 @@ tx_error (struct net_device *dev, int tx_status)
|
|||
break;
|
||||
mdelay (1);
|
||||
}
|
||||
rio_set_led_mode(dev);
|
||||
/* Let TxStartThresh stay default value */
|
||||
}
|
||||
/* Maximum Collisions */
|
||||
|
|
@ -965,6 +1013,7 @@ rio_error (struct net_device *dev, int int_status)
|
|||
dev->name, int_status);
|
||||
dw16(ASICCtrl + 2, GlobalReset | HostReset);
|
||||
mdelay (500);
|
||||
rio_set_led_mode(dev);
|
||||
}
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -211,6 +211,10 @@ enum ASICCtrl_HiWord_bits {
|
|||
ResetBusy = 0x0400,
|
||||
};
|
||||
|
||||
#define IPG_AC_LED_MODE BIT(14)
|
||||
#define IPG_AC_LED_SPEED BIT(27)
|
||||
#define IPG_AC_LED_MODE_BIT_1 BIT(29)
|
||||
|
||||
/* Transmit Frame Control bits */
|
||||
enum TFC_bits {
|
||||
DwordAlign = 0x00000000,
|
||||
|
|
@ -332,7 +336,10 @@ typedef struct t_SROM {
|
|||
u16 asic_ctrl; /* 0x02 */
|
||||
u16 sub_vendor_id; /* 0x04 */
|
||||
u16 sub_system_id; /* 0x06 */
|
||||
u16 reserved1[12]; /* 0x08-0x1f */
|
||||
u16 pci_base_1; /* 0x08 (IP1000A only) */
|
||||
u16 pci_base_2; /* 0x0a (IP1000A only) */
|
||||
u16 led_mode; /* 0x0c (IP1000A only) */
|
||||
u16 reserved1[9]; /* 0x0e-0x1f */
|
||||
u8 mac_addr[6]; /* 0x20-0x25 */
|
||||
u8 reserved2[10]; /* 0x26-0x2f */
|
||||
u8 sib[204]; /* 0x30-0xfb */
|
||||
|
|
@ -397,6 +404,7 @@ struct netdev_private {
|
|||
u16 advertising; /* NWay media advertisement */
|
||||
u16 negotiate; /* Negotiated media */
|
||||
int phy_addr; /* PHY addresses. */
|
||||
u16 led_mode; /* LED mode read from EEPROM (IP1000A only) */
|
||||
};
|
||||
|
||||
/* The station address location in the EEPROM. */
|
||||
|
|
@ -407,10 +415,15 @@ struct netdev_private {
|
|||
class_mask of the class are honored during the comparison.
|
||||
driver_data Data private to the driver.
|
||||
*/
|
||||
#define CHIP_IP1000A 1
|
||||
|
||||
static const struct pci_device_id rio_pci_tbl[] = {
|
||||
{0x1186, 0x4000, PCI_ANY_ID, PCI_ANY_ID, },
|
||||
{0x13f0, 0x1021, PCI_ANY_ID, PCI_ANY_ID, },
|
||||
{ PCI_VDEVICE(SUNDANCE, 0x1023), CHIP_IP1000A },
|
||||
{ PCI_VDEVICE(SUNDANCE, 0x2021), CHIP_IP1000A },
|
||||
{ PCI_VDEVICE(DLINK, 0x9021), CHIP_IP1000A },
|
||||
{ PCI_VDEVICE(DLINK, 0x4020), CHIP_IP1000A },
|
||||
{ }
|
||||
};
|
||||
MODULE_DEVICE_TABLE (pci, rio_pci_tbl);
|
||||
|
|
|
|||
|
|
@ -1062,9 +1062,7 @@ static int be_get_rxnfc(struct net_device *netdev, struct ethtool_rxnfc *cmd,
|
|||
static int be_set_rss_hash_opts(struct be_adapter *adapter,
|
||||
struct ethtool_rxnfc *cmd)
|
||||
{
|
||||
struct be_rx_obj *rxo;
|
||||
int status = 0, i, j;
|
||||
u8 rsstable[128];
|
||||
int status;
|
||||
u32 rss_flags = adapter->rss_info.rss_flags;
|
||||
|
||||
if (cmd->data != L3_RSS_FLAGS &&
|
||||
|
|
@ -1113,20 +1111,11 @@ static int be_set_rss_hash_opts(struct be_adapter *adapter,
|
|||
}
|
||||
|
||||
if (rss_flags == adapter->rss_info.rss_flags)
|
||||
return status;
|
||||
|
||||
if (be_multi_rxq(adapter)) {
|
||||
for (j = 0; j < 128; j += adapter->num_rss_qs) {
|
||||
for_all_rss_queues(adapter, rxo, i) {
|
||||
if ((j + i) >= 128)
|
||||
break;
|
||||
rsstable[j + i] = rxo->rss_id;
|
||||
}
|
||||
}
|
||||
}
|
||||
return 0;
|
||||
|
||||
status = be_cmd_rss_config(adapter, adapter->rss_info.rsstable,
|
||||
rss_flags, 128, adapter->rss_info.rss_hkey);
|
||||
rss_flags, RSS_INDIR_TABLE_LEN,
|
||||
adapter->rss_info.rss_hkey);
|
||||
if (!status)
|
||||
adapter->rss_info.rss_flags = rss_flags;
|
||||
|
||||
|
|
|
|||
|
|
@ -3518,7 +3518,7 @@ static int be_rx_qs_create(struct be_adapter *adapter)
|
|||
|
||||
netdev_rss_key_fill(rss_key, RSS_HASH_KEY_LEN);
|
||||
rc = be_cmd_rss_config(adapter, rss->rsstable, rss->rss_flags,
|
||||
128, rss_key);
|
||||
RSS_INDIR_TABLE_LEN, rss_key);
|
||||
if (rc) {
|
||||
rss->rss_flags = RSS_ENABLE_NONE;
|
||||
return rc;
|
||||
|
|
|
|||
|
|
@ -1,13 +0,0 @@
|
|||
#
|
||||
# IC Plus device configuration
|
||||
#
|
||||
|
||||
config IP1000
|
||||
tristate "IP1000 Gigabit Ethernet support"
|
||||
depends on PCI
|
||||
select MII
|
||||
---help---
|
||||
This driver supports IP1000 gigabit Ethernet cards.
|
||||
|
||||
To compile this driver as a module, choose M here: the module
|
||||
will be called ipg. This is recommended.
|
||||
|
|
@ -1,5 +0,0 @@
|
|||
#
|
||||
# Makefile for the IC Plus device drivers
|
||||
#
|
||||
|
||||
obj-$(CONFIG_IP1000) += ipg.o
|
||||
File diff suppressed because it is too large
Load diff
|
|
@ -1,748 +0,0 @@
|
|||
/*
|
||||
* Include file for Gigabit Ethernet device driver for Network
|
||||
* Interface Cards (NICs) utilizing the Tamarack Microelectronics
|
||||
* Inc. IPG Gigabit or Triple Speed Ethernet Media Access
|
||||
* Controller.
|
||||
*/
|
||||
#ifndef __LINUX_IPG_H
|
||||
#define __LINUX_IPG_H
|
||||
|
||||
#include <linux/module.h>
|
||||
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/pci.h>
|
||||
#include <linux/ioport.h>
|
||||
#include <linux/errno.h>
|
||||
#include <asm/io.h>
|
||||
#include <linux/delay.h>
|
||||
#include <linux/types.h>
|
||||
#include <linux/netdevice.h>
|
||||
#include <linux/etherdevice.h>
|
||||
#include <linux/skbuff.h>
|
||||
#include <asm/bitops.h>
|
||||
|
||||
/*
|
||||
* Constants
|
||||
*/
|
||||
|
||||
/* GMII based PHY IDs */
|
||||
#define NS 0x2000
|
||||
#define MARVELL 0x0141
|
||||
#define ICPLUS_PHY 0x243
|
||||
|
||||
/* NIC Physical Layer Device MII register fields. */
|
||||
#define MII_PHY_SELECTOR_IEEE8023 0x0001
|
||||
#define MII_PHY_TECHABILITYFIELD 0x1FE0
|
||||
|
||||
/* GMII_PHY_1000 need to set to prefer master */
|
||||
#define GMII_PHY_1000BASETCONTROL_PreferMaster 0x0400
|
||||
|
||||
/* NIC Physical Layer Device GMII constants. */
|
||||
#define GMII_PREAMBLE 0xFFFFFFFF
|
||||
#define GMII_ST 0x1
|
||||
#define GMII_READ 0x2
|
||||
#define GMII_WRITE 0x1
|
||||
#define GMII_TA_READ_MASK 0x1
|
||||
#define GMII_TA_WRITE 0x2
|
||||
|
||||
/* I/O register offsets. */
|
||||
enum ipg_regs {
|
||||
DMA_CTRL = 0x00,
|
||||
RX_DMA_STATUS = 0x08, /* Unused + reserved */
|
||||
TFD_LIST_PTR_0 = 0x10,
|
||||
TFD_LIST_PTR_1 = 0x14,
|
||||
TX_DMA_BURST_THRESH = 0x18,
|
||||
TX_DMA_URGENT_THRESH = 0x19,
|
||||
TX_DMA_POLL_PERIOD = 0x1a,
|
||||
RFD_LIST_PTR_0 = 0x1c,
|
||||
RFD_LIST_PTR_1 = 0x20,
|
||||
RX_DMA_BURST_THRESH = 0x24,
|
||||
RX_DMA_URGENT_THRESH = 0x25,
|
||||
RX_DMA_POLL_PERIOD = 0x26,
|
||||
DEBUG_CTRL = 0x2c,
|
||||
ASIC_CTRL = 0x30,
|
||||
FIFO_CTRL = 0x38, /* Unused */
|
||||
FLOW_OFF_THRESH = 0x3c,
|
||||
FLOW_ON_THRESH = 0x3e,
|
||||
EEPROM_DATA = 0x48,
|
||||
EEPROM_CTRL = 0x4a,
|
||||
EXPROM_ADDR = 0x4c, /* Unused */
|
||||
EXPROM_DATA = 0x50, /* Unused */
|
||||
WAKE_EVENT = 0x51, /* Unused */
|
||||
COUNTDOWN = 0x54, /* Unused */
|
||||
INT_STATUS_ACK = 0x5a,
|
||||
INT_ENABLE = 0x5c,
|
||||
INT_STATUS = 0x5e, /* Unused */
|
||||
TX_STATUS = 0x60,
|
||||
MAC_CTRL = 0x6c,
|
||||
VLAN_TAG = 0x70, /* Unused */
|
||||
PHY_SET = 0x75,
|
||||
PHY_CTRL = 0x76,
|
||||
STATION_ADDRESS_0 = 0x78,
|
||||
STATION_ADDRESS_1 = 0x7a,
|
||||
STATION_ADDRESS_2 = 0x7c,
|
||||
MAX_FRAME_SIZE = 0x86,
|
||||
RECEIVE_MODE = 0x88,
|
||||
HASHTABLE_0 = 0x8c,
|
||||
HASHTABLE_1 = 0x90,
|
||||
RMON_STATISTICS_MASK = 0x98,
|
||||
STATISTICS_MASK = 0x9c,
|
||||
RX_JUMBO_FRAMES = 0xbc, /* Unused */
|
||||
TCP_CHECKSUM_ERRORS = 0xc0, /* Unused */
|
||||
IP_CHECKSUM_ERRORS = 0xc2, /* Unused */
|
||||
UDP_CHECKSUM_ERRORS = 0xc4, /* Unused */
|
||||
TX_JUMBO_FRAMES = 0xf4 /* Unused */
|
||||
};
|
||||
|
||||
/* Ethernet MIB statistic register offsets. */
|
||||
#define IPG_OCTETRCVOK 0xA8
|
||||
#define IPG_MCSTOCTETRCVDOK 0xAC
|
||||
#define IPG_BCSTOCTETRCVOK 0xB0
|
||||
#define IPG_FRAMESRCVDOK 0xB4
|
||||
#define IPG_MCSTFRAMESRCVDOK 0xB8
|
||||
#define IPG_BCSTFRAMESRCVDOK 0xBE
|
||||
#define IPG_MACCONTROLFRAMESRCVD 0xC6
|
||||
#define IPG_FRAMETOOLONGERRORS 0xC8
|
||||
#define IPG_INRANGELENGTHERRORS 0xCA
|
||||
#define IPG_FRAMECHECKSEQERRORS 0xCC
|
||||
#define IPG_FRAMESLOSTRXERRORS 0xCE
|
||||
#define IPG_OCTETXMTOK 0xD0
|
||||
#define IPG_MCSTOCTETXMTOK 0xD4
|
||||
#define IPG_BCSTOCTETXMTOK 0xD8
|
||||
#define IPG_FRAMESXMTDOK 0xDC
|
||||
#define IPG_MCSTFRAMESXMTDOK 0xE0
|
||||
#define IPG_FRAMESWDEFERREDXMT 0xE4
|
||||
#define IPG_LATECOLLISIONS 0xE8
|
||||
#define IPG_MULTICOLFRAMES 0xEC
|
||||
#define IPG_SINGLECOLFRAMES 0xF0
|
||||
#define IPG_BCSTFRAMESXMTDOK 0xF6
|
||||
#define IPG_CARRIERSENSEERRORS 0xF8
|
||||
#define IPG_MACCONTROLFRAMESXMTDOK 0xFA
|
||||
#define IPG_FRAMESABORTXSCOLLS 0xFC
|
||||
#define IPG_FRAMESWEXDEFERRAL 0xFE
|
||||
|
||||
/* RMON statistic register offsets. */
|
||||
#define IPG_ETHERSTATSCOLLISIONS 0x100
|
||||
#define IPG_ETHERSTATSOCTETSTRANSMIT 0x104
|
||||
#define IPG_ETHERSTATSPKTSTRANSMIT 0x108
|
||||
#define IPG_ETHERSTATSPKTS64OCTESTSTRANSMIT 0x10C
|
||||
#define IPG_ETHERSTATSPKTS65TO127OCTESTSTRANSMIT 0x110
|
||||
#define IPG_ETHERSTATSPKTS128TO255OCTESTSTRANSMIT 0x114
|
||||
#define IPG_ETHERSTATSPKTS256TO511OCTESTSTRANSMIT 0x118
|
||||
#define IPG_ETHERSTATSPKTS512TO1023OCTESTSTRANSMIT 0x11C
|
||||
#define IPG_ETHERSTATSPKTS1024TO1518OCTESTSTRANSMIT 0x120
|
||||
#define IPG_ETHERSTATSCRCALIGNERRORS 0x124
|
||||
#define IPG_ETHERSTATSUNDERSIZEPKTS 0x128
|
||||
#define IPG_ETHERSTATSFRAGMENTS 0x12C
|
||||
#define IPG_ETHERSTATSJABBERS 0x130
|
||||
#define IPG_ETHERSTATSOCTETS 0x134
|
||||
#define IPG_ETHERSTATSPKTS 0x138
|
||||
#define IPG_ETHERSTATSPKTS64OCTESTS 0x13C
|
||||
#define IPG_ETHERSTATSPKTS65TO127OCTESTS 0x140
|
||||
#define IPG_ETHERSTATSPKTS128TO255OCTESTS 0x144
|
||||
#define IPG_ETHERSTATSPKTS256TO511OCTESTS 0x148
|
||||
#define IPG_ETHERSTATSPKTS512TO1023OCTESTS 0x14C
|
||||
#define IPG_ETHERSTATSPKTS1024TO1518OCTESTS 0x150
|
||||
|
||||
/* RMON statistic register equivalents. */
|
||||
#define IPG_ETHERSTATSMULTICASTPKTSTRANSMIT 0xE0
|
||||
#define IPG_ETHERSTATSBROADCASTPKTSTRANSMIT 0xF6
|
||||
#define IPG_ETHERSTATSMULTICASTPKTS 0xB8
|
||||
#define IPG_ETHERSTATSBROADCASTPKTS 0xBE
|
||||
#define IPG_ETHERSTATSOVERSIZEPKTS 0xC8
|
||||
#define IPG_ETHERSTATSDROPEVENTS 0xCE
|
||||
|
||||
/* Serial EEPROM offsets */
|
||||
#define IPG_EEPROM_CONFIGPARAM 0x00
|
||||
#define IPG_EEPROM_ASICCTRL 0x01
|
||||
#define IPG_EEPROM_SUBSYSTEMVENDORID 0x02
|
||||
#define IPG_EEPROM_SUBSYSTEMID 0x03
|
||||
#define IPG_EEPROM_STATIONADDRESS0 0x10
|
||||
#define IPG_EEPROM_STATIONADDRESS1 0x11
|
||||
#define IPG_EEPROM_STATIONADDRESS2 0x12
|
||||
|
||||
/* Register & data structure bit masks */
|
||||
|
||||
/* PCI register masks. */
|
||||
|
||||
/* IOBaseAddress */
|
||||
#define IPG_PIB_RSVD_MASK 0xFFFFFE01
|
||||
#define IPG_PIB_IOBASEADDRESS 0xFFFFFF00
|
||||
#define IPG_PIB_IOBASEADDRIND 0x00000001
|
||||
|
||||
/* MemBaseAddress */
|
||||
#define IPG_PMB_RSVD_MASK 0xFFFFFE07
|
||||
#define IPG_PMB_MEMBASEADDRIND 0x00000001
|
||||
#define IPG_PMB_MEMMAPTYPE 0x00000006
|
||||
#define IPG_PMB_MEMMAPTYPE0 0x00000002
|
||||
#define IPG_PMB_MEMMAPTYPE1 0x00000004
|
||||
#define IPG_PMB_MEMBASEADDRESS 0xFFFFFE00
|
||||
|
||||
/* ConfigStatus */
|
||||
#define IPG_CS_RSVD_MASK 0xFFB0
|
||||
#define IPG_CS_CAPABILITIES 0x0010
|
||||
#define IPG_CS_66MHZCAPABLE 0x0020
|
||||
#define IPG_CS_FASTBACK2BACK 0x0080
|
||||
#define IPG_CS_DATAPARITYREPORTED 0x0100
|
||||
#define IPG_CS_DEVSELTIMING 0x0600
|
||||
#define IPG_CS_SIGNALEDTARGETABORT 0x0800
|
||||
#define IPG_CS_RECEIVEDTARGETABORT 0x1000
|
||||
#define IPG_CS_RECEIVEDMASTERABORT 0x2000
|
||||
#define IPG_CS_SIGNALEDSYSTEMERROR 0x4000
|
||||
#define IPG_CS_DETECTEDPARITYERROR 0x8000
|
||||
|
||||
/* TFD data structure masks. */
|
||||
|
||||
/* TFDList, TFC */
|
||||
#define IPG_TFC_RSVD_MASK 0x0000FFFF9FFFFFFFULL
|
||||
#define IPG_TFC_FRAMEID 0x000000000000FFFFULL
|
||||
#define IPG_TFC_WORDALIGN 0x0000000000030000ULL
|
||||
#define IPG_TFC_WORDALIGNTODWORD 0x0000000000000000ULL
|
||||
#define IPG_TFC_WORDALIGNTOWORD 0x0000000000020000ULL
|
||||
#define IPG_TFC_WORDALIGNDISABLED 0x0000000000030000ULL
|
||||
#define IPG_TFC_TCPCHECKSUMENABLE 0x0000000000040000ULL
|
||||
#define IPG_TFC_UDPCHECKSUMENABLE 0x0000000000080000ULL
|
||||
#define IPG_TFC_IPCHECKSUMENABLE 0x0000000000100000ULL
|
||||
#define IPG_TFC_FCSAPPENDDISABLE 0x0000000000200000ULL
|
||||
#define IPG_TFC_TXINDICATE 0x0000000000400000ULL
|
||||
#define IPG_TFC_TXDMAINDICATE 0x0000000000800000ULL
|
||||
#define IPG_TFC_FRAGCOUNT 0x000000000F000000ULL
|
||||
#define IPG_TFC_VLANTAGINSERT 0x0000000010000000ULL
|
||||
#define IPG_TFC_TFDDONE 0x0000000080000000ULL
|
||||
#define IPG_TFC_VID 0x00000FFF00000000ULL
|
||||
#define IPG_TFC_CFI 0x0000100000000000ULL
|
||||
#define IPG_TFC_USERPRIORITY 0x0000E00000000000ULL
|
||||
|
||||
/* TFDList, FragInfo */
|
||||
#define IPG_TFI_RSVD_MASK 0xFFFF00FFFFFFFFFFULL
|
||||
#define IPG_TFI_FRAGADDR 0x000000FFFFFFFFFFULL
|
||||
#define IPG_TFI_FRAGLEN 0xFFFF000000000000ULL
|
||||
|
||||
/* RFD data structure masks. */
|
||||
|
||||
/* RFDList, RFS */
|
||||
#define IPG_RFS_RSVD_MASK 0x0000FFFFFFFFFFFFULL
|
||||
#define IPG_RFS_RXFRAMELEN 0x000000000000FFFFULL
|
||||
#define IPG_RFS_RXFIFOOVERRUN 0x0000000000010000ULL
|
||||
#define IPG_RFS_RXRUNTFRAME 0x0000000000020000ULL
|
||||
#define IPG_RFS_RXALIGNMENTERROR 0x0000000000040000ULL
|
||||
#define IPG_RFS_RXFCSERROR 0x0000000000080000ULL
|
||||
#define IPG_RFS_RXOVERSIZEDFRAME 0x0000000000100000ULL
|
||||
#define IPG_RFS_RXLENGTHERROR 0x0000000000200000ULL
|
||||
#define IPG_RFS_VLANDETECTED 0x0000000000400000ULL
|
||||
#define IPG_RFS_TCPDETECTED 0x0000000000800000ULL
|
||||
#define IPG_RFS_TCPERROR 0x0000000001000000ULL
|
||||
#define IPG_RFS_UDPDETECTED 0x0000000002000000ULL
|
||||
#define IPG_RFS_UDPERROR 0x0000000004000000ULL
|
||||
#define IPG_RFS_IPDETECTED 0x0000000008000000ULL
|
||||
#define IPG_RFS_IPERROR 0x0000000010000000ULL
|
||||
#define IPG_RFS_FRAMESTART 0x0000000020000000ULL
|
||||
#define IPG_RFS_FRAMEEND 0x0000000040000000ULL
|
||||
#define IPG_RFS_RFDDONE 0x0000000080000000ULL
|
||||
#define IPG_RFS_TCI 0x0000FFFF00000000ULL
|
||||
|
||||
/* RFDList, FragInfo */
|
||||
#define IPG_RFI_RSVD_MASK 0xFFFF00FFFFFFFFFFULL
|
||||
#define IPG_RFI_FRAGADDR 0x000000FFFFFFFFFFULL
|
||||
#define IPG_RFI_FRAGLEN 0xFFFF000000000000ULL
|
||||
|
||||
/* I/O Register masks. */
|
||||
|
||||
/* RMON Statistics Mask */
|
||||
#define IPG_RZ_ALL 0x0FFFFFFF
|
||||
|
||||
/* Statistics Mask */
|
||||
#define IPG_SM_ALL 0x0FFFFFFF
|
||||
#define IPG_SM_OCTETRCVOK_FRAMESRCVDOK 0x00000001
|
||||
#define IPG_SM_MCSTOCTETRCVDOK_MCSTFRAMESRCVDOK 0x00000002
|
||||
#define IPG_SM_BCSTOCTETRCVDOK_BCSTFRAMESRCVDOK 0x00000004
|
||||
#define IPG_SM_RXJUMBOFRAMES 0x00000008
|
||||
#define IPG_SM_TCPCHECKSUMERRORS 0x00000010
|
||||
#define IPG_SM_IPCHECKSUMERRORS 0x00000020
|
||||
#define IPG_SM_UDPCHECKSUMERRORS 0x00000040
|
||||
#define IPG_SM_MACCONTROLFRAMESRCVD 0x00000080
|
||||
#define IPG_SM_FRAMESTOOLONGERRORS 0x00000100
|
||||
#define IPG_SM_INRANGELENGTHERRORS 0x00000200
|
||||
#define IPG_SM_FRAMECHECKSEQERRORS 0x00000400
|
||||
#define IPG_SM_FRAMESLOSTRXERRORS 0x00000800
|
||||
#define IPG_SM_OCTETXMTOK_FRAMESXMTOK 0x00001000
|
||||
#define IPG_SM_MCSTOCTETXMTOK_MCSTFRAMESXMTDOK 0x00002000
|
||||
#define IPG_SM_BCSTOCTETXMTOK_BCSTFRAMESXMTDOK 0x00004000
|
||||
#define IPG_SM_FRAMESWDEFERREDXMT 0x00008000
|
||||
#define IPG_SM_LATECOLLISIONS 0x00010000
|
||||
#define IPG_SM_MULTICOLFRAMES 0x00020000
|
||||
#define IPG_SM_SINGLECOLFRAMES 0x00040000
|
||||
#define IPG_SM_TXJUMBOFRAMES 0x00080000
|
||||
#define IPG_SM_CARRIERSENSEERRORS 0x00100000
|
||||
#define IPG_SM_MACCONTROLFRAMESXMTD 0x00200000
|
||||
#define IPG_SM_FRAMESABORTXSCOLLS 0x00400000
|
||||
#define IPG_SM_FRAMESWEXDEFERAL 0x00800000
|
||||
|
||||
/* Countdown */
|
||||
#define IPG_CD_RSVD_MASK 0x0700FFFF
|
||||
#define IPG_CD_COUNT 0x0000FFFF
|
||||
#define IPG_CD_COUNTDOWNSPEED 0x01000000
|
||||
#define IPG_CD_COUNTDOWNMODE 0x02000000
|
||||
#define IPG_CD_COUNTINTENABLED 0x04000000
|
||||
|
||||
/* TxDMABurstThresh */
|
||||
#define IPG_TB_RSVD_MASK 0xFF
|
||||
|
||||
/* TxDMAUrgentThresh */
|
||||
#define IPG_TU_RSVD_MASK 0xFF
|
||||
|
||||
/* TxDMAPollPeriod */
|
||||
#define IPG_TP_RSVD_MASK 0xFF
|
||||
|
||||
/* RxDMAUrgentThresh */
|
||||
#define IPG_RU_RSVD_MASK 0xFF
|
||||
|
||||
/* RxDMAPollPeriod */
|
||||
#define IPG_RP_RSVD_MASK 0xFF
|
||||
|
||||
/* ReceiveMode */
|
||||
#define IPG_RM_RSVD_MASK 0x3F
|
||||
#define IPG_RM_RECEIVEUNICAST 0x01
|
||||
#define IPG_RM_RECEIVEMULTICAST 0x02
|
||||
#define IPG_RM_RECEIVEBROADCAST 0x04
|
||||
#define IPG_RM_RECEIVEALLFRAMES 0x08
|
||||
#define IPG_RM_RECEIVEMULTICASTHASH 0x10
|
||||
#define IPG_RM_RECEIVEIPMULTICAST 0x20
|
||||
|
||||
/* PhySet */
|
||||
#define IPG_PS_MEM_LENB9B 0x01
|
||||
#define IPG_PS_MEM_LEN9 0x02
|
||||
#define IPG_PS_NON_COMPDET 0x04
|
||||
|
||||
/* PhyCtrl */
|
||||
#define IPG_PC_RSVD_MASK 0xFF
|
||||
#define IPG_PC_MGMTCLK_LO 0x00
|
||||
#define IPG_PC_MGMTCLK_HI 0x01
|
||||
#define IPG_PC_MGMTCLK 0x01
|
||||
#define IPG_PC_MGMTDATA 0x02
|
||||
#define IPG_PC_MGMTDIR 0x04
|
||||
#define IPG_PC_DUPLEX_POLARITY 0x08
|
||||
#define IPG_PC_DUPLEX_STATUS 0x10
|
||||
#define IPG_PC_LINK_POLARITY 0x20
|
||||
#define IPG_PC_LINK_SPEED 0xC0
|
||||
#define IPG_PC_LINK_SPEED_10MBPS 0x40
|
||||
#define IPG_PC_LINK_SPEED_100MBPS 0x80
|
||||
#define IPG_PC_LINK_SPEED_1000MBPS 0xC0
|
||||
|
||||
/* DMACtrl */
|
||||
#define IPG_DC_RSVD_MASK 0xC07D9818
|
||||
#define IPG_DC_RX_DMA_COMPLETE 0x00000008
|
||||
#define IPG_DC_RX_DMA_POLL_NOW 0x00000010
|
||||
#define IPG_DC_TX_DMA_COMPLETE 0x00000800
|
||||
#define IPG_DC_TX_DMA_POLL_NOW 0x00001000
|
||||
#define IPG_DC_TX_DMA_IN_PROG 0x00008000
|
||||
#define IPG_DC_RX_EARLY_DISABLE 0x00010000
|
||||
#define IPG_DC_MWI_DISABLE 0x00040000
|
||||
#define IPG_DC_TX_WRITE_BACK_DISABLE 0x00080000
|
||||
#define IPG_DC_TX_BURST_LIMIT 0x00700000
|
||||
#define IPG_DC_TARGET_ABORT 0x40000000
|
||||
#define IPG_DC_MASTER_ABORT 0x80000000
|
||||
|
||||
/* ASICCtrl */
|
||||
#define IPG_AC_RSVD_MASK 0x07FFEFF2
|
||||
#define IPG_AC_EXP_ROM_SIZE 0x00000002
|
||||
#define IPG_AC_PHY_SPEED10 0x00000010
|
||||
#define IPG_AC_PHY_SPEED100 0x00000020
|
||||
#define IPG_AC_PHY_SPEED1000 0x00000040
|
||||
#define IPG_AC_PHY_MEDIA 0x00000080
|
||||
#define IPG_AC_FORCED_CFG 0x00000700
|
||||
#define IPG_AC_D3RESETDISABLE 0x00000800
|
||||
#define IPG_AC_SPEED_UP_MODE 0x00002000
|
||||
#define IPG_AC_LED_MODE 0x00004000
|
||||
#define IPG_AC_RST_OUT_POLARITY 0x00008000
|
||||
#define IPG_AC_GLOBAL_RESET 0x00010000
|
||||
#define IPG_AC_RX_RESET 0x00020000
|
||||
#define IPG_AC_TX_RESET 0x00040000
|
||||
#define IPG_AC_DMA 0x00080000
|
||||
#define IPG_AC_FIFO 0x00100000
|
||||
#define IPG_AC_NETWORK 0x00200000
|
||||
#define IPG_AC_HOST 0x00400000
|
||||
#define IPG_AC_AUTO_INIT 0x00800000
|
||||
#define IPG_AC_RST_OUT 0x01000000
|
||||
#define IPG_AC_INT_REQUEST 0x02000000
|
||||
#define IPG_AC_RESET_BUSY 0x04000000
|
||||
#define IPG_AC_LED_SPEED 0x08000000
|
||||
#define IPG_AC_LED_MODE_BIT_1 0x20000000
|
||||
|
||||
/* EepromCtrl */
|
||||
#define IPG_EC_RSVD_MASK 0x83FF
|
||||
#define IPG_EC_EEPROM_ADDR 0x00FF
|
||||
#define IPG_EC_EEPROM_OPCODE 0x0300
|
||||
#define IPG_EC_EEPROM_SUBCOMMAD 0x0000
|
||||
#define IPG_EC_EEPROM_WRITEOPCODE 0x0100
|
||||
#define IPG_EC_EEPROM_READOPCODE 0x0200
|
||||
#define IPG_EC_EEPROM_ERASEOPCODE 0x0300
|
||||
#define IPG_EC_EEPROM_BUSY 0x8000
|
||||
|
||||
/* FIFOCtrl */
|
||||
#define IPG_FC_RSVD_MASK 0xC001
|
||||
#define IPG_FC_RAM_TEST_MODE 0x0001
|
||||
#define IPG_FC_TRANSMITTING 0x4000
|
||||
#define IPG_FC_RECEIVING 0x8000
|
||||
|
||||
/* TxStatus */
|
||||
#define IPG_TS_RSVD_MASK 0xFFFF00DD
|
||||
#define IPG_TS_TX_ERROR 0x00000001
|
||||
#define IPG_TS_LATE_COLLISION 0x00000004
|
||||
#define IPG_TS_TX_MAX_COLL 0x00000008
|
||||
#define IPG_TS_TX_UNDERRUN 0x00000010
|
||||
#define IPG_TS_TX_IND_REQD 0x00000040
|
||||
#define IPG_TS_TX_COMPLETE 0x00000080
|
||||
#define IPG_TS_TX_FRAMEID 0xFFFF0000
|
||||
|
||||
/* WakeEvent */
|
||||
#define IPG_WE_WAKE_PKT_ENABLE 0x01
|
||||
#define IPG_WE_MAGIC_PKT_ENABLE 0x02
|
||||
#define IPG_WE_LINK_EVT_ENABLE 0x04
|
||||
#define IPG_WE_WAKE_POLARITY 0x08
|
||||
#define IPG_WE_WAKE_PKT_EVT 0x10
|
||||
#define IPG_WE_MAGIC_PKT_EVT 0x20
|
||||
#define IPG_WE_LINK_EVT 0x40
|
||||
#define IPG_WE_WOL_ENABLE 0x80
|
||||
|
||||
/* IntEnable */
|
||||
#define IPG_IE_RSVD_MASK 0x1FFE
|
||||
#define IPG_IE_HOST_ERROR 0x0002
|
||||
#define IPG_IE_TX_COMPLETE 0x0004
|
||||
#define IPG_IE_MAC_CTRL_FRAME 0x0008
|
||||
#define IPG_IE_RX_COMPLETE 0x0010
|
||||
#define IPG_IE_RX_EARLY 0x0020
|
||||
#define IPG_IE_INT_REQUESTED 0x0040
|
||||
#define IPG_IE_UPDATE_STATS 0x0080
|
||||
#define IPG_IE_LINK_EVENT 0x0100
|
||||
#define IPG_IE_TX_DMA_COMPLETE 0x0200
|
||||
#define IPG_IE_RX_DMA_COMPLETE 0x0400
|
||||
#define IPG_IE_RFD_LIST_END 0x0800
|
||||
#define IPG_IE_RX_DMA_PRIORITY 0x1000
|
||||
|
||||
/* IntStatus */
|
||||
#define IPG_IS_RSVD_MASK 0x1FFF
|
||||
#define IPG_IS_INTERRUPT_STATUS 0x0001
|
||||
#define IPG_IS_HOST_ERROR 0x0002
|
||||
#define IPG_IS_TX_COMPLETE 0x0004
|
||||
#define IPG_IS_MAC_CTRL_FRAME 0x0008
|
||||
#define IPG_IS_RX_COMPLETE 0x0010
|
||||
#define IPG_IS_RX_EARLY 0x0020
|
||||
#define IPG_IS_INT_REQUESTED 0x0040
|
||||
#define IPG_IS_UPDATE_STATS 0x0080
|
||||
#define IPG_IS_LINK_EVENT 0x0100
|
||||
#define IPG_IS_TX_DMA_COMPLETE 0x0200
|
||||
#define IPG_IS_RX_DMA_COMPLETE 0x0400
|
||||
#define IPG_IS_RFD_LIST_END 0x0800
|
||||
#define IPG_IS_RX_DMA_PRIORITY 0x1000
|
||||
|
||||
/* MACCtrl */
|
||||
#define IPG_MC_RSVD_MASK 0x7FE33FA3
|
||||
#define IPG_MC_IFS_SELECT 0x00000003
|
||||
#define IPG_MC_IFS_4352BIT 0x00000003
|
||||
#define IPG_MC_IFS_1792BIT 0x00000002
|
||||
#define IPG_MC_IFS_1024BIT 0x00000001
|
||||
#define IPG_MC_IFS_96BIT 0x00000000
|
||||
#define IPG_MC_DUPLEX_SELECT 0x00000020
|
||||
#define IPG_MC_DUPLEX_SELECT_FD 0x00000020
|
||||
#define IPG_MC_DUPLEX_SELECT_HD 0x00000000
|
||||
#define IPG_MC_TX_FLOW_CONTROL_ENABLE 0x00000080
|
||||
#define IPG_MC_RX_FLOW_CONTROL_ENABLE 0x00000100
|
||||
#define IPG_MC_RCV_FCS 0x00000200
|
||||
#define IPG_MC_FIFO_LOOPBACK 0x00000400
|
||||
#define IPG_MC_MAC_LOOPBACK 0x00000800
|
||||
#define IPG_MC_AUTO_VLAN_TAGGING 0x00001000
|
||||
#define IPG_MC_AUTO_VLAN_UNTAGGING 0x00002000
|
||||
#define IPG_MC_COLLISION_DETECT 0x00010000
|
||||
#define IPG_MC_CARRIER_SENSE 0x00020000
|
||||
#define IPG_MC_STATISTICS_ENABLE 0x00200000
|
||||
#define IPG_MC_STATISTICS_DISABLE 0x00400000
|
||||
#define IPG_MC_STATISTICS_ENABLED 0x00800000
|
||||
#define IPG_MC_TX_ENABLE 0x01000000
|
||||
#define IPG_MC_TX_DISABLE 0x02000000
|
||||
#define IPG_MC_TX_ENABLED 0x04000000
|
||||
#define IPG_MC_RX_ENABLE 0x08000000
|
||||
#define IPG_MC_RX_DISABLE 0x10000000
|
||||
#define IPG_MC_RX_ENABLED 0x20000000
|
||||
#define IPG_MC_PAUSED 0x40000000
|
||||
|
||||
/*
|
||||
* Tune
|
||||
*/
|
||||
|
||||
/* Assign IPG_APPEND_FCS_ON_TX > 0 for auto FCS append on TX. */
|
||||
#define IPG_APPEND_FCS_ON_TX 1
|
||||
|
||||
/* Assign IPG_APPEND_FCS_ON_TX > 0 for auto FCS strip on RX. */
|
||||
#define IPG_STRIP_FCS_ON_RX 1
|
||||
|
||||
/* Assign IPG_DROP_ON_RX_ETH_ERRORS > 0 to drop RX frames with
|
||||
* Ethernet errors.
|
||||
*/
|
||||
#define IPG_DROP_ON_RX_ETH_ERRORS 1
|
||||
|
||||
/* Assign IPG_INSERT_MANUAL_VLAN_TAG > 0 to insert VLAN tags manually
|
||||
* (via TFC).
|
||||
*/
|
||||
#define IPG_INSERT_MANUAL_VLAN_TAG 0
|
||||
|
||||
/* Assign IPG_ADD_IPCHECKSUM_ON_TX > 0 for auto IP checksum on TX. */
|
||||
#define IPG_ADD_IPCHECKSUM_ON_TX 0
|
||||
|
||||
/* Assign IPG_ADD_TCPCHECKSUM_ON_TX > 0 for auto TCP checksum on TX.
|
||||
* DO NOT USE FOR SILICON REVISIONS B3 AND EARLIER.
|
||||
*/
|
||||
#define IPG_ADD_TCPCHECKSUM_ON_TX 0
|
||||
|
||||
/* Assign IPG_ADD_UDPCHECKSUM_ON_TX > 0 for auto UDP checksum on TX.
|
||||
* DO NOT USE FOR SILICON REVISIONS B3 AND EARLIER.
|
||||
*/
|
||||
#define IPG_ADD_UDPCHECKSUM_ON_TX 0
|
||||
|
||||
/* If inserting VLAN tags manually, assign the IPG_MANUAL_VLAN_xx
|
||||
* constants as desired.
|
||||
*/
|
||||
#define IPG_MANUAL_VLAN_VID 0xABC
|
||||
#define IPG_MANUAL_VLAN_CFI 0x1
|
||||
#define IPG_MANUAL_VLAN_USERPRIORITY 0x5
|
||||
|
||||
#define IPG_IO_REG_RANGE 0xFF
|
||||
#define IPG_MEM_REG_RANGE 0x154
|
||||
#define IPG_DRIVER_NAME "Sundance Technology IPG Triple-Speed Ethernet"
|
||||
#define IPG_NIC_PHY_ADDRESS 0x01
|
||||
#define IPG_DMALIST_ALIGN_PAD 0x07
|
||||
#define IPG_MULTICAST_HASHTABLE_SIZE 0x40
|
||||
|
||||
/* Number of milliseconds to wait after issuing a software reset.
|
||||
* 0x05 <= IPG_AC_RESETWAIT to account for proper 10Mbps operation.
|
||||
*/
|
||||
#define IPG_AC_RESETWAIT 0x05
|
||||
|
||||
/* Number of IPG_AC_RESETWAIT timeperiods before declaring timeout. */
|
||||
#define IPG_AC_RESET_TIMEOUT 0x0A
|
||||
|
||||
/* Minimum number of nanoseconds used to toggle MDC clock during
|
||||
* MII/GMII register access.
|
||||
*/
|
||||
#define IPG_PC_PHYCTRLWAIT_NS 200
|
||||
|
||||
#define IPG_TFDLIST_LENGTH 0x100
|
||||
|
||||
/* Number of frames between TxDMAComplete interrupt.
|
||||
* 0 < IPG_FRAMESBETWEENTXDMACOMPLETES <= IPG_TFDLIST_LENGTH
|
||||
*/
|
||||
#define IPG_FRAMESBETWEENTXDMACOMPLETES 0x1
|
||||
|
||||
#define IPG_RFDLIST_LENGTH 0x100
|
||||
|
||||
/* Maximum number of RFDs to process per interrupt.
|
||||
* 1 < IPG_MAXRFDPROCESS_COUNT < IPG_RFDLIST_LENGTH
|
||||
*/
|
||||
#define IPG_MAXRFDPROCESS_COUNT 0x80
|
||||
|
||||
/* Minimum margin between last freed RFD, and current RFD.
|
||||
* 1 < IPG_MINUSEDRFDSTOFREE < IPG_RFDLIST_LENGTH
|
||||
*/
|
||||
#define IPG_MINUSEDRFDSTOFREE 0x80
|
||||
|
||||
/* specify the jumbo frame maximum size
|
||||
* per unit is 0x600 (the rx_buffer size that one RFD can carry)
|
||||
*/
|
||||
#define MAX_JUMBOSIZE 0x8 /* max is 12K */
|
||||
|
||||
/* Key register values loaded at driver start up. */
|
||||
|
||||
/* TXDMAPollPeriod is specified in 320ns increments.
|
||||
*
|
||||
* Value Time
|
||||
* ---------------------
|
||||
* 0x00-0x01 320ns
|
||||
* 0x03 ~1us
|
||||
* 0x1F ~10us
|
||||
* 0xFF ~82us
|
||||
*/
|
||||
#define IPG_TXDMAPOLLPERIOD_VALUE 0x26
|
||||
|
||||
/* TxDMAUrgentThresh specifies the minimum amount of
|
||||
* data in the transmit FIFO before asserting an
|
||||
* urgent transmit DMA request.
|
||||
*
|
||||
* Value Min TxFIFO occupied space before urgent TX request
|
||||
* ---------------------------------------------------------------
|
||||
* 0x00-0x04 128 bytes (1024 bits)
|
||||
* 0x27 1248 bytes (~10000 bits)
|
||||
* 0x30 1536 bytes (12288 bits)
|
||||
* 0xFF 8192 bytes (65535 bits)
|
||||
*/
|
||||
#define IPG_TXDMAURGENTTHRESH_VALUE 0x04
|
||||
|
||||
/* TxDMABurstThresh specifies the minimum amount of
|
||||
* free space in the transmit FIFO before asserting an
|
||||
* transmit DMA request.
|
||||
*
|
||||
* Value Min TxFIFO free space before TX request
|
||||
* ----------------------------------------------------
|
||||
* 0x00-0x08 256 bytes
|
||||
* 0x30 1536 bytes
|
||||
* 0xFF 8192 bytes
|
||||
*/
|
||||
#define IPG_TXDMABURSTTHRESH_VALUE 0x30
|
||||
|
||||
/* RXDMAPollPeriod is specified in 320ns increments.
|
||||
*
|
||||
* Value Time
|
||||
* ---------------------
|
||||
* 0x00-0x01 320ns
|
||||
* 0x03 ~1us
|
||||
* 0x1F ~10us
|
||||
* 0xFF ~82us
|
||||
*/
|
||||
#define IPG_RXDMAPOLLPERIOD_VALUE 0x01
|
||||
|
||||
/* RxDMAUrgentThresh specifies the minimum amount of
|
||||
* free space within the receive FIFO before asserting
|
||||
* a urgent receive DMA request.
|
||||
*
|
||||
* Value Min RxFIFO free space before urgent RX request
|
||||
* ---------------------------------------------------------------
|
||||
* 0x00-0x04 128 bytes (1024 bits)
|
||||
* 0x27 1248 bytes (~10000 bits)
|
||||
* 0x30 1536 bytes (12288 bits)
|
||||
* 0xFF 8192 bytes (65535 bits)
|
||||
*/
|
||||
#define IPG_RXDMAURGENTTHRESH_VALUE 0x30
|
||||
|
||||
/* RxDMABurstThresh specifies the minimum amount of
|
||||
* occupied space within the receive FIFO before asserting
|
||||
* a receive DMA request.
|
||||
*
|
||||
* Value Min TxFIFO free space before TX request
|
||||
* ----------------------------------------------------
|
||||
* 0x00-0x08 256 bytes
|
||||
* 0x30 1536 bytes
|
||||
* 0xFF 8192 bytes
|
||||
*/
|
||||
#define IPG_RXDMABURSTTHRESH_VALUE 0x30
|
||||
|
||||
/* FlowOnThresh specifies the maximum amount of occupied
|
||||
* space in the receive FIFO before a PAUSE frame with
|
||||
* maximum pause time transmitted.
|
||||
*
|
||||
* Value Max RxFIFO occupied space before PAUSE
|
||||
* ---------------------------------------------------
|
||||
* 0x0000 0 bytes
|
||||
* 0x0740 29,696 bytes
|
||||
* 0x07FF 32,752 bytes
|
||||
*/
|
||||
#define IPG_FLOWONTHRESH_VALUE 0x0740
|
||||
|
||||
/* FlowOffThresh specifies the minimum amount of occupied
|
||||
* space in the receive FIFO before a PAUSE frame with
|
||||
* zero pause time is transmitted.
|
||||
*
|
||||
* Value Max RxFIFO occupied space before PAUSE
|
||||
* ---------------------------------------------------
|
||||
* 0x0000 0 bytes
|
||||
* 0x00BF 3056 bytes
|
||||
* 0x07FF 32,752 bytes
|
||||
*/
|
||||
#define IPG_FLOWOFFTHRESH_VALUE 0x00BF
|
||||
|
||||
/*
|
||||
* Miscellaneous macros.
|
||||
*/
|
||||
|
||||
/* Macros for printing debug statements. */
|
||||
#ifdef IPG_DEBUG
|
||||
# define IPG_DEBUG_MSG(fmt, args...) \
|
||||
do { \
|
||||
if (0) \
|
||||
printk(KERN_DEBUG "IPG: " fmt, ##args); \
|
||||
} while (0)
|
||||
# define IPG_DDEBUG_MSG(fmt, args...) \
|
||||
printk(KERN_DEBUG "IPG: " fmt, ##args)
|
||||
# define IPG_DUMPRFDLIST(args) ipg_dump_rfdlist(args)
|
||||
# define IPG_DUMPTFDLIST(args) ipg_dump_tfdlist(args)
|
||||
#else
|
||||
# define IPG_DEBUG_MSG(fmt, args...) \
|
||||
do { \
|
||||
if (0) \
|
||||
printk(KERN_DEBUG "IPG: " fmt, ##args); \
|
||||
} while (0)
|
||||
# define IPG_DDEBUG_MSG(fmt, args...) \
|
||||
do { \
|
||||
if (0) \
|
||||
printk(KERN_DEBUG "IPG: " fmt, ##args); \
|
||||
} while (0)
|
||||
# define IPG_DUMPRFDLIST(args)
|
||||
# define IPG_DUMPTFDLIST(args)
|
||||
#endif
|
||||
|
||||
/*
|
||||
* End miscellaneous macros.
|
||||
*/
|
||||
|
||||
/* Transmit Frame Descriptor. The IPG supports 15 fragments,
|
||||
* however Linux requires only a single fragment. Note, each
|
||||
* TFD field is 64 bits wide.
|
||||
*/
|
||||
struct ipg_tx {
|
||||
__le64 next_desc;
|
||||
__le64 tfc;
|
||||
__le64 frag_info;
|
||||
};
|
||||
|
||||
/* Receive Frame Descriptor. Note, each RFD field is 64 bits wide.
|
||||
*/
|
||||
struct ipg_rx {
|
||||
__le64 next_desc;
|
||||
__le64 rfs;
|
||||
__le64 frag_info;
|
||||
};
|
||||
|
||||
struct ipg_jumbo {
|
||||
int found_start;
|
||||
int current_size;
|
||||
struct sk_buff *skb;
|
||||
};
|
||||
|
||||
/* Structure of IPG NIC specific data. */
|
||||
struct ipg_nic_private {
|
||||
void __iomem *ioaddr;
|
||||
struct ipg_tx *txd;
|
||||
struct ipg_rx *rxd;
|
||||
dma_addr_t txd_map;
|
||||
dma_addr_t rxd_map;
|
||||
struct sk_buff *tx_buff[IPG_TFDLIST_LENGTH];
|
||||
struct sk_buff *rx_buff[IPG_RFDLIST_LENGTH];
|
||||
unsigned int tx_current;
|
||||
unsigned int tx_dirty;
|
||||
unsigned int rx_current;
|
||||
unsigned int rx_dirty;
|
||||
bool is_jumbo;
|
||||
struct ipg_jumbo jumbo;
|
||||
unsigned long rxfrag_size;
|
||||
unsigned long rxsupport_size;
|
||||
unsigned long max_rxframe_size;
|
||||
unsigned int rx_buf_sz;
|
||||
struct pci_dev *pdev;
|
||||
struct net_device *dev;
|
||||
struct net_device_stats stats;
|
||||
spinlock_t lock;
|
||||
int tenmbpsmode;
|
||||
|
||||
u16 led_mode;
|
||||
u16 station_addr[3]; /* Station Address in EEPROM Reg 0x10..0x12 */
|
||||
|
||||
struct mutex mii_mutex;
|
||||
struct mii_if_info mii_if;
|
||||
int reset_current_tfd;
|
||||
#ifdef IPG_DEBUG
|
||||
int RFDlistendCount;
|
||||
int RFDListCheckedCount;
|
||||
int EmptyRFDListCount;
|
||||
#endif
|
||||
struct delayed_work task;
|
||||
};
|
||||
|
||||
#endif /* __LINUX_IPG_H */
|
||||
|
|
@ -892,9 +892,10 @@ static int mlx4_slave_cap(struct mlx4_dev *dev)
|
|||
dev->caps.qp1_proxy[i - 1] = func_cap.qp1_proxy_qpn;
|
||||
dev->caps.port_mask[i] = dev->caps.port_type[i];
|
||||
dev->caps.phys_port_id[i] = func_cap.phys_port_id;
|
||||
if (mlx4_get_slave_pkey_gid_tbl_len(dev, i,
|
||||
&dev->caps.gid_table_len[i],
|
||||
&dev->caps.pkey_table_len[i]))
|
||||
err = mlx4_get_slave_pkey_gid_tbl_len(dev, i,
|
||||
&dev->caps.gid_table_len[i],
|
||||
&dev->caps.pkey_table_len[i]);
|
||||
if (err)
|
||||
goto err_mem;
|
||||
}
|
||||
|
||||
|
|
@ -906,6 +907,7 @@ static int mlx4_slave_cap(struct mlx4_dev *dev)
|
|||
dev->caps.uar_page_size * dev->caps.num_uars,
|
||||
(unsigned long long)
|
||||
pci_resource_len(dev->persist->pdev, 2));
|
||||
err = -ENOMEM;
|
||||
goto err_mem;
|
||||
}
|
||||
|
||||
|
|
|
|||
Some files were not shown because too many files have changed in this diff Show more
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Reference in a new issue