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pci-v4.19-changes
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R. Silva) - Move DMA-debug PCI init from arch code to PCI core (Christoph Hellwig) - Fix pci_request_irq() usage of IRQF_ONESHOT when no handler is supplied (Heiner Kallweit) - Unify PCI and DMA direction #defines (Shunyong Yang) - Add PCI_DEVICE_DATA() macro (Andy Shevchenko) - Check for VPD completion before checking for timeout (Bert Kenward) - Limit Netronome NFP5000 config space size to work around erratum (Jakub Kicinski) - Set IRQCHIP_ONESHOT_SAFE for PCI MSI irqchips (Heiner Kallweit) - Document ACPI description of PCI host bridges (Bjorn Helgaas) - Add "pci=disable_acs_redir=" parameter to disable ACS redirection for peer-to-peer DMA support (we don't have the peer-to-peer support yet; this is just one piece) (Logan Gunthorpe) - Clean up devm_of_pci_get_host_bridge_resources() resource allocation (Jan Kiszka) - Fixup resizable BARs after suspend/resume (Christian König) - Make "pci=earlydump" generic (Sinan Kaya) - Fix ROM BAR access routines to stay in bounds and check for signature correctly (Rex Zhu) - Add DMA alias quirk for Microsemi Switchtec NTB (Doug Meyer) - Expand documentation for pci_add_dma_alias() (Logan Gunthorpe) - To avoid bus errors, enable PASID only if entire path supports End-End TLP prefixes (Sinan Kaya) - Unify slot and bus reset functions and remove hotplug knowledge from callers (Sinan Kaya) - Add Function-Level Reset quirks for Intel and Samsung NVMe devices to fix guest reboot issues (Alex Williamson) - Add function 1 DMA alias quirk for Marvell 88SS9183 PCIe SSD Controller (Bjorn Helgaas) - Remove Xilinx AXI-PCIe host bridge arch dependency (Palmer Dabbelt) - Remove Aardvark outbound window configuration (Evan Wang) - Fix Aardvark bridge window sizing issue (Zachary Zhang) - Convert Aardvark to use pci_host_probe() to reduce code duplication (Thomas Petazzoni) - Correct the Cadence cdns_pcie_writel() signature (Alan Douglas) - Add Cadence support for optional generic PHYs (Alan Douglas) - Add Cadence power management ops (Alan Douglas) - Remove redundant variable from Cadence driver (Colin Ian King) - Add Kirin MSI support (Xiaowei Song) - Drop unnecessary root_bus_nr setting from exynos, imx6, keystone, armada8k, artpec6, designware-plat, histb, qcom, spear13xx (Shawn Guo) - Move link notification settings from DesignWare core to individual drivers (Gustavo Pimentel) - Add endpoint library MSI-X interfaces (Gustavo Pimentel) - Correct signature of endpoint library IRQ interfaces (Gustavo Pimentel) - Add DesignWare endpoint library MSI-X callbacks (Gustavo Pimentel) - Add endpoint library MSI-X test support (Gustavo Pimentel) - Remove unnecessary GFP_ATOMIC from Hyper-V "new child" allocation (Jia-Ju Bai) - Add more devices to Broadcom PAXC quirk (Ray Jui) - Work around corrupted Broadcom PAXC config space to enable SMMU and GICv3 ITS (Ray Jui) - Disable MSI parsing to work around broken Broadcom PAXC logic in some devices (Ray Jui) - Hide unconfigured functions to work around a Broadcom PAXC defect (Ray Jui) - Lower iproc log level to reduce console output during boot (Ray Jui) - Fix mobiveil iomem/phys_addr_t type usage (Lorenzo Pieralisi) - Fix mobiveil missing include file (Lorenzo Pieralisi) - Add mobiveil Kconfig/Makefile support (Lorenzo Pieralisi) - Fix mvebu I/O space remapping issues (Thomas Petazzoni) - Use generic pci_host_bridge in mvebu instead of ARM-specific API (Thomas Petazzoni) - Whitelist VMD devices with fast interrupt handlers to avoid sharing vectors with slow handlers (Keith Busch) * tag 'pci-v4.19-changes' of git://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci: (153 commits) PCI/AER: Don't clear AER bits if error handling is Firmware-First PCI: Limit config space size for Netronome NFP5000 PCI/MSI: Set IRQCHIP_ONESHOT_SAFE for PCI-MSI irqchips PCI/VPD: Check for VPD access completion before checking for timeout PCI: Add PCI_DEVICE_DATA() macro to fully describe device ID entry PCI: Match Root Port's MPS to endpoint's MPSS as necessary PCI: Skip MPS logic for Virtual Functions (VFs) PCI: Add function 1 DMA alias quirk for Marvell 88SS9183 PCI: Check for PCIe Link downtraining PCI: Add ACS Redirect disable quirk for Intel Sunrise Point PCI: Add device-specific ACS Redirect disable infrastructure PCI: Convert device-specific ACS quirks from NULL termination to ARRAY_SIZE PCI: Add "pci=disable_acs_redir=" parameter for peer-to-peer support PCI: Allow specifying devices using a base bus and path of devfns PCI: Make specifying PCI devices in kernel parameters reusable PCI: Hide ACS quirk declarations inside PCI core PCI: Delay after FLR of Intel DC P3700 NVMe PCI: Disable Samsung SM961/PM961 NVMe before FLR PCI: Export pcie_has_flr() PCI: mvebu: Drop bogus comment above mvebu_pcie_map_registers() ...
This commit is contained in:
Linus Torvalds
commit
4e31843f68
115 changed files with 3571 additions and 1786 deletions
122
Documentation/ABI/testing/sysfs-bus-pci-devices-aer_stats
Normal file
122
Documentation/ABI/testing/sysfs-bus-pci-devices-aer_stats
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@ -0,0 +1,122 @@
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==========================
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PCIe Device AER statistics
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==========================
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These attributes show up under all the devices that are AER capable. These
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statistical counters indicate the errors "as seen/reported by the device".
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Note that this may mean that if an endpoint is causing problems, the AER
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counters may increment at its link partner (e.g. root port) because the
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errors may be "seen" / reported by the link partner and not the
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problematic endpoint itself (which may report all counters as 0 as it never
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saw any problems).
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Where: /sys/bus/pci/devices/<dev>/aer_dev_correctable
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Date: July 2018
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Kernel Version: 4.19.0
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Contact: linux-pci@vger.kernel.org, rajatja@google.com
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Description: List of correctable errors seen and reported by this
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PCI device using ERR_COR. Note that since multiple errors may
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be reported using a single ERR_COR message, thus
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TOTAL_ERR_COR at the end of the file may not match the actual
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total of all the errors in the file. Sample output:
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-------------------------------------------------------------------------
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localhost /sys/devices/pci0000:00/0000:00:1c.0 # cat aer_dev_correctable
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Receiver Error 2
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Bad TLP 0
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Bad DLLP 0
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RELAY_NUM Rollover 0
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Replay Timer Timeout 0
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Advisory Non-Fatal 0
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Corrected Internal Error 0
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Header Log Overflow 0
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TOTAL_ERR_COR 2
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-------------------------------------------------------------------------
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Where: /sys/bus/pci/devices/<dev>/aer_dev_fatal
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Date: July 2018
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Kernel Version: 4.19.0
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Contact: linux-pci@vger.kernel.org, rajatja@google.com
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Description: List of uncorrectable fatal errors seen and reported by this
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PCI device using ERR_FATAL. Note that since multiple errors may
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be reported using a single ERR_FATAL message, thus
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TOTAL_ERR_FATAL at the end of the file may not match the actual
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total of all the errors in the file. Sample output:
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-------------------------------------------------------------------------
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localhost /sys/devices/pci0000:00/0000:00:1c.0 # cat aer_dev_fatal
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Undefined 0
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Data Link Protocol 0
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Surprise Down Error 0
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Poisoned TLP 0
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Flow Control Protocol 0
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Completion Timeout 0
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Completer Abort 0
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Unexpected Completion 0
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Receiver Overflow 0
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Malformed TLP 0
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ECRC 0
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Unsupported Request 0
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ACS Violation 0
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Uncorrectable Internal Error 0
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MC Blocked TLP 0
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AtomicOp Egress Blocked 0
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TLP Prefix Blocked Error 0
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TOTAL_ERR_FATAL 0
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-------------------------------------------------------------------------
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Where: /sys/bus/pci/devices/<dev>/aer_dev_nonfatal
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Date: July 2018
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Kernel Version: 4.19.0
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Contact: linux-pci@vger.kernel.org, rajatja@google.com
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Description: List of uncorrectable nonfatal errors seen and reported by this
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PCI device using ERR_NONFATAL. Note that since multiple errors
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may be reported using a single ERR_FATAL message, thus
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TOTAL_ERR_NONFATAL at the end of the file may not match the
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actual total of all the errors in the file. Sample output:
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-------------------------------------------------------------------------
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localhost /sys/devices/pci0000:00/0000:00:1c.0 # cat aer_dev_nonfatal
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Undefined 0
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Data Link Protocol 0
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Surprise Down Error 0
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Poisoned TLP 0
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Flow Control Protocol 0
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Completion Timeout 0
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Completer Abort 0
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Unexpected Completion 0
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Receiver Overflow 0
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Malformed TLP 0
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ECRC 0
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Unsupported Request 0
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ACS Violation 0
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Uncorrectable Internal Error 0
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MC Blocked TLP 0
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AtomicOp Egress Blocked 0
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TLP Prefix Blocked Error 0
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TOTAL_ERR_NONFATAL 0
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-------------------------------------------------------------------------
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============================
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PCIe Rootport AER statistics
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============================
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These attributes show up under only the rootports (or root complex event
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collectors) that are AER capable. These indicate the number of error messages as
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"reported to" the rootport. Please note that the rootports also transmit
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(internally) the ERR_* messages for errors seen by the internal rootport PCI
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device, so these counters include them and are thus cumulative of all the error
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messages on the PCI hierarchy originating at that root port.
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Where: /sys/bus/pci/devices/<dev>/aer_stats/aer_rootport_total_err_cor
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Date: July 2018
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Kernel Version: 4.19.0
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Contact: linux-pci@vger.kernel.org, rajatja@google.com
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Description: Total number of ERR_COR messages reported to rootport.
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Where: /sys/bus/pci/devices/<dev>/aer_stats/aer_rootport_total_err_fatal
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Date: July 2018
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Kernel Version: 4.19.0
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Contact: linux-pci@vger.kernel.org, rajatja@google.com
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Description: Total number of ERR_FATAL messages reported to rootport.
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Where: /sys/bus/pci/devices/<dev>/aer_stats/aer_rootport_total_err_nonfatal
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Date: July 2018
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Kernel Version: 4.19.0
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Contact: linux-pci@vger.kernel.org, rajatja@google.com
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Description: Total number of ERR_NONFATAL messages reported to rootport.
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@ -1,5 +1,7 @@
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00-INDEX
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- this file
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acpi-info.txt
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- info on how PCI host bridges are represented in ACPI
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MSI-HOWTO.txt
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- the Message Signaled Interrupts (MSI) Driver Guide HOWTO and FAQ.
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PCIEBUS-HOWTO.txt
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187
Documentation/PCI/acpi-info.txt
Normal file
187
Documentation/PCI/acpi-info.txt
Normal file
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@ -0,0 +1,187 @@
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ACPI considerations for PCI host bridges
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The general rule is that the ACPI namespace should describe everything the
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OS might use unless there's another way for the OS to find it [1, 2].
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For example, there's no standard hardware mechanism for enumerating PCI
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host bridges, so the ACPI namespace must describe each host bridge, the
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method for accessing PCI config space below it, the address space windows
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the host bridge forwards to PCI (using _CRS), and the routing of legacy
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INTx interrupts (using _PRT).
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PCI devices, which are below the host bridge, generally do not need to be
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described via ACPI. The OS can discover them via the standard PCI
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enumeration mechanism, using config accesses to discover and identify
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devices and read and size their BARs. However, ACPI may describe PCI
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devices if it provides power management or hotplug functionality for them
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or if the device has INTx interrupts connected by platform interrupt
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controllers and a _PRT is needed to describe those connections.
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ACPI resource description is done via _CRS objects of devices in the ACPI
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namespace [2]. The _CRS is like a generalized PCI BAR: the OS can read
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_CRS and figure out what resource is being consumed even if it doesn't have
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a driver for the device [3]. That's important because it means an old OS
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can work correctly even on a system with new devices unknown to the OS.
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The new devices might not do anything, but the OS can at least make sure no
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resources conflict with them.
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Static tables like MCFG, HPET, ECDT, etc., are *not* mechanisms for
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reserving address space. The static tables are for things the OS needs to
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know early in boot, before it can parse the ACPI namespace. If a new table
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is defined, an old OS needs to operate correctly even though it ignores the
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table. _CRS allows that because it is generic and understood by the old
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OS; a static table does not.
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If the OS is expected to manage a non-discoverable device described via
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ACPI, that device will have a specific _HID/_CID that tells the OS what
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driver to bind to it, and the _CRS tells the OS and the driver where the
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device's registers are.
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PCI host bridges are PNP0A03 or PNP0A08 devices. Their _CRS should
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describe all the address space they consume. This includes all the windows
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they forward down to the PCI bus, as well as registers of the host bridge
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itself that are not forwarded to PCI. The host bridge registers include
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things like secondary/subordinate bus registers that determine the bus
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range below the bridge, window registers that describe the apertures, etc.
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These are all device-specific, non-architected things, so the only way a
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PNP0A03/PNP0A08 driver can manage them is via _PRS/_CRS/_SRS, which contain
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the device-specific details. The host bridge registers also include ECAM
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space, since it is consumed by the host bridge.
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ACPI defines a Consumer/Producer bit to distinguish the bridge registers
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("Consumer") from the bridge apertures ("Producer") [4, 5], but early
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BIOSes didn't use that bit correctly. The result is that the current ACPI
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spec defines Consumer/Producer only for the Extended Address Space
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descriptors; the bit should be ignored in the older QWord/DWord/Word
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Address Space descriptors. Consequently, OSes have to assume all
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QWord/DWord/Word descriptors are windows.
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Prior to the addition of Extended Address Space descriptors, the failure of
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Consumer/Producer meant there was no way to describe bridge registers in
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the PNP0A03/PNP0A08 device itself. The workaround was to describe the
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bridge registers (including ECAM space) in PNP0C02 catch-all devices [6].
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With the exception of ECAM, the bridge register space is device-specific
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anyway, so the generic PNP0A03/PNP0A08 driver (pci_root.c) has no need to
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know about it.
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New architectures should be able to use "Consumer" Extended Address Space
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descriptors in the PNP0A03 device for bridge registers, including ECAM,
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although a strict interpretation of [6] might prohibit this. Old x86 and
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ia64 kernels assume all address space descriptors, including "Consumer"
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Extended Address Space ones, are windows, so it would not be safe to
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describe bridge registers this way on those architectures.
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PNP0C02 "motherboard" devices are basically a catch-all. There's no
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programming model for them other than "don't use these resources for
|
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anything else." So a PNP0C02 _CRS should claim any address space that is
|
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(1) not claimed by _CRS under any other device object in the ACPI namespace
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and (2) should not be assigned by the OS to something else.
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|
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The PCIe spec requires the Enhanced Configuration Access Method (ECAM)
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unless there's a standard firmware interface for config access, e.g., the
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ia64 SAL interface [7]. A host bridge consumes ECAM memory address space
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and converts memory accesses into PCI configuration accesses. The spec
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defines the ECAM address space layout and functionality; only the base of
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the address space is device-specific. An ACPI OS learns the base address
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from either the static MCFG table or a _CBA method in the PNP0A03 device.
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The MCFG table must describe the ECAM space of non-hot pluggable host
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bridges [8]. Since MCFG is a static table and can't be updated by hotplug,
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a _CBA method in the PNP0A03 device describes the ECAM space of a
|
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hot-pluggable host bridge [9]. Note that for both MCFG and _CBA, the base
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address always corresponds to bus 0, even if the bus range below the bridge
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(which is reported via _CRS) doesn't start at 0.
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[1] ACPI 6.2, sec 6.1:
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For any device that is on a non-enumerable type of bus (for example, an
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ISA bus), OSPM enumerates the devices' identifier(s) and the ACPI
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system firmware must supply an _HID object ... for each device to
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enable OSPM to do that.
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[2] ACPI 6.2, sec 3.7:
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The OS enumerates motherboard devices simply by reading through the
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ACPI Namespace looking for devices with hardware IDs.
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Each device enumerated by ACPI includes ACPI-defined objects in the
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ACPI Namespace that report the hardware resources the device could
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occupy [_PRS], an object that reports the resources that are currently
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used by the device [_CRS], and objects for configuring those resources
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||||
[_SRS]. The information is used by the Plug and Play OS (OSPM) to
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configure the devices.
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[3] ACPI 6.2, sec 6.2:
|
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OSPM uses device configuration objects to configure hardware resources
|
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for devices enumerated via ACPI. Device configuration objects provide
|
||||
information about current and possible resource requirements, the
|
||||
relationship between shared resources, and methods for configuring
|
||||
hardware resources.
|
||||
|
||||
When OSPM enumerates a device, it calls _PRS to determine the resource
|
||||
requirements of the device. It may also call _CRS to find the current
|
||||
resource settings for the device. Using this information, the Plug and
|
||||
Play system determines what resources the device should consume and
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||||
sets those resources by calling the device’s _SRS control method.
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||||
|
||||
In ACPI, devices can consume resources (for example, legacy keyboards),
|
||||
provide resources (for example, a proprietary PCI bridge), or do both.
|
||||
Unless otherwise specified, resources for a device are assumed to be
|
||||
taken from the nearest matching resource above the device in the device
|
||||
hierarchy.
|
||||
|
||||
[4] ACPI 6.2, sec 6.4.3.5.1, 2, 3, 4:
|
||||
QWord/DWord/Word Address Space Descriptor (.1, .2, .3)
|
||||
General Flags: Bit [0] Ignored
|
||||
|
||||
Extended Address Space Descriptor (.4)
|
||||
General Flags: Bit [0] Consumer/Producer:
|
||||
1–This device consumes this resource
|
||||
0–This device produces and consumes this resource
|
||||
|
||||
[5] ACPI 6.2, sec 19.6.43:
|
||||
ResourceUsage specifies whether the Memory range is consumed by
|
||||
this device (ResourceConsumer) or passed on to child devices
|
||||
(ResourceProducer). If nothing is specified, then
|
||||
ResourceConsumer is assumed.
|
||||
|
||||
[6] PCI Firmware 3.2, sec 4.1.2:
|
||||
If the operating system does not natively comprehend reserving the
|
||||
MMCFG region, the MMCFG region must be reserved by firmware. The
|
||||
address range reported in the MCFG table or by _CBA method (see Section
|
||||
4.1.3) must be reserved by declaring a motherboard resource. For most
|
||||
systems, the motherboard resource would appear at the root of the ACPI
|
||||
namespace (under \_SB) in a node with a _HID of EISAID (PNP0C02), and
|
||||
the resources in this case should not be claimed in the root PCI bus’s
|
||||
_CRS. The resources can optionally be returned in Int15 E820 or
|
||||
EFIGetMemoryMap as reserved memory but must always be reported through
|
||||
ACPI as a motherboard resource.
|
||||
|
||||
[7] PCI Express 4.0, sec 7.2.2:
|
||||
For systems that are PC-compatible, or that do not implement a
|
||||
processor-architecture-specific firmware interface standard that allows
|
||||
access to the Configuration Space, the ECAM is required as defined in
|
||||
this section.
|
||||
|
||||
[8] PCI Firmware 3.2, sec 4.1.2:
|
||||
The MCFG table is an ACPI table that is used to communicate the base
|
||||
addresses corresponding to the non-hot removable PCI Segment Groups
|
||||
range within a PCI Segment Group available to the operating system at
|
||||
boot. This is required for the PC-compatible systems.
|
||||
|
||||
The MCFG table is only used to communicate the base addresses
|
||||
corresponding to the PCI Segment Groups available to the system at
|
||||
boot.
|
||||
|
||||
[9] PCI Firmware 3.2, sec 4.1.3:
|
||||
The _CBA (Memory mapped Configuration Base Address) control method is
|
||||
an optional ACPI object that returns the 64-bit memory mapped
|
||||
configuration base address for the hot plug capable host bridge. The
|
||||
base address returned by _CBA is processor-relative address. The _CBA
|
||||
control method evaluates to an Integer.
|
||||
|
||||
This control method appears under a host bridge object. When the _CBA
|
||||
method appears under an active host bridge object, the operating system
|
||||
evaluates this structure to identify the memory mapped configuration
|
||||
base address corresponding to the PCI Segment Group for the bus number
|
||||
range specified in _CRS method. An ACPI name space object that contains
|
||||
the _CBA method must also contain a corresponding _SEG method.
|
||||
|
|
@ -15,3 +15,5 @@ subsys_id : don't care
|
|||
interrupt_pin : Should be 1 - INTA, 2 - INTB, 3 - INTC, 4 -INTD
|
||||
msi_interrupts : Should be 1 to 32 depending on the number of MSI interrupts
|
||||
to test
|
||||
msix_interrupts : Should be 1 to 2048 depending on the number of MSI-X
|
||||
interrupts to test
|
||||
|
|
|
|||
|
|
@ -44,7 +44,7 @@ by the PCI controller driver.
|
|||
* clear_bar: ops to reset the BAR
|
||||
* alloc_addr_space: ops to allocate in PCI controller address space
|
||||
* free_addr_space: ops to free the allocated address space
|
||||
* raise_irq: ops to raise a legacy or MSI interrupt
|
||||
* raise_irq: ops to raise a legacy, MSI or MSI-X interrupt
|
||||
* start: ops to start the PCI link
|
||||
* stop: ops to stop the PCI link
|
||||
|
||||
|
|
@ -96,7 +96,7 @@ by the PCI endpoint function driver.
|
|||
*) pci_epc_raise_irq()
|
||||
|
||||
The PCI endpoint function driver should use pci_epc_raise_irq() to raise
|
||||
Legacy Interrupt or MSI Interrupt.
|
||||
Legacy Interrupt, MSI or MSI-X Interrupt.
|
||||
|
||||
*) pci_epc_mem_alloc_addr()
|
||||
|
||||
|
|
|
|||
|
|
@ -20,6 +20,8 @@ The PCI endpoint test device has the following registers:
|
|||
5) PCI_ENDPOINT_TEST_DST_ADDR
|
||||
6) PCI_ENDPOINT_TEST_SIZE
|
||||
7) PCI_ENDPOINT_TEST_CHECKSUM
|
||||
8) PCI_ENDPOINT_TEST_IRQ_TYPE
|
||||
9) PCI_ENDPOINT_TEST_IRQ_NUMBER
|
||||
|
||||
*) PCI_ENDPOINT_TEST_MAGIC
|
||||
|
||||
|
|
@ -34,10 +36,10 @@ that the endpoint device must perform.
|
|||
Bitfield Description:
|
||||
Bit 0 : raise legacy IRQ
|
||||
Bit 1 : raise MSI IRQ
|
||||
Bit 2 - 7 : MSI interrupt number
|
||||
Bit 8 : read command (read data from RC buffer)
|
||||
Bit 9 : write command (write data to RC buffer)
|
||||
Bit 10 : copy command (copy data from one RC buffer to another
|
||||
Bit 2 : raise MSI-X IRQ
|
||||
Bit 3 : read command (read data from RC buffer)
|
||||
Bit 4 : write command (write data to RC buffer)
|
||||
Bit 5 : copy command (copy data from one RC buffer to another
|
||||
RC buffer)
|
||||
|
||||
*) PCI_ENDPOINT_TEST_STATUS
|
||||
|
|
@ -64,3 +66,22 @@ COPY/READ command.
|
|||
|
||||
This register contains the destination address (RC buffer address) for
|
||||
the COPY/WRITE command.
|
||||
|
||||
*) PCI_ENDPOINT_TEST_IRQ_TYPE
|
||||
|
||||
This register contains the interrupt type (Legacy/MSI) triggered
|
||||
for the READ/WRITE/COPY and raise IRQ (Legacy/MSI) commands.
|
||||
|
||||
Possible types:
|
||||
- Legacy : 0
|
||||
- MSI : 1
|
||||
- MSI-X : 2
|
||||
|
||||
*) PCI_ENDPOINT_TEST_IRQ_NUMBER
|
||||
|
||||
This register contains the triggered ID interrupt.
|
||||
|
||||
Admissible values:
|
||||
- Legacy : 0
|
||||
- MSI : [1 .. 32]
|
||||
- MSI-X : [1 .. 2048]
|
||||
|
|
|
|||
|
|
@ -45,9 +45,9 @@ The PCI endpoint framework populates the directory with the following
|
|||
configurable fields.
|
||||
|
||||
# ls functions/pci_epf_test/func1
|
||||
baseclass_code interrupt_pin revid subsys_vendor_id
|
||||
cache_line_size msi_interrupts subclass_code vendorid
|
||||
deviceid progif_code subsys_id
|
||||
baseclass_code interrupt_pin progif_code subsys_id
|
||||
cache_line_size msi_interrupts revid subsys_vendorid
|
||||
deviceid msix_interrupts subclass_code vendorid
|
||||
|
||||
The PCI endpoint function driver populates these entries with default values
|
||||
when the device is bound to the driver. The pci-epf-test driver populates
|
||||
|
|
@ -67,6 +67,7 @@ device, the following commands can be used.
|
|||
# echo 0x104c > functions/pci_epf_test/func1/vendorid
|
||||
# echo 0xb500 > functions/pci_epf_test/func1/deviceid
|
||||
# echo 16 > functions/pci_epf_test/func1/msi_interrupts
|
||||
# echo 8 > functions/pci_epf_test/func1/msix_interrupts
|
||||
|
||||
1.5 Binding pci-epf-test Device to EP Controller
|
||||
|
||||
|
|
@ -120,7 +121,9 @@ following commands.
|
|||
|
||||
Interrupt tests
|
||||
|
||||
SET IRQ TYPE TO LEGACY: OKAY
|
||||
LEGACY IRQ: NOT OKAY
|
||||
SET IRQ TYPE TO MSI: OKAY
|
||||
MSI1: OKAY
|
||||
MSI2: OKAY
|
||||
MSI3: OKAY
|
||||
|
|
@ -153,9 +156,30 @@ following commands.
|
|||
MSI30: NOT OKAY
|
||||
MSI31: NOT OKAY
|
||||
MSI32: NOT OKAY
|
||||
SET IRQ TYPE TO MSI-X: OKAY
|
||||
MSI-X1: OKAY
|
||||
MSI-X2: OKAY
|
||||
MSI-X3: OKAY
|
||||
MSI-X4: OKAY
|
||||
MSI-X5: OKAY
|
||||
MSI-X6: OKAY
|
||||
MSI-X7: OKAY
|
||||
MSI-X8: OKAY
|
||||
MSI-X9: NOT OKAY
|
||||
MSI-X10: NOT OKAY
|
||||
MSI-X11: NOT OKAY
|
||||
MSI-X12: NOT OKAY
|
||||
MSI-X13: NOT OKAY
|
||||
MSI-X14: NOT OKAY
|
||||
MSI-X15: NOT OKAY
|
||||
MSI-X16: NOT OKAY
|
||||
[...]
|
||||
MSI-X2047: NOT OKAY
|
||||
MSI-X2048: NOT OKAY
|
||||
|
||||
Read Tests
|
||||
|
||||
SET IRQ TYPE TO MSI: OKAY
|
||||
READ ( 1 bytes): OKAY
|
||||
READ ( 1024 bytes): OKAY
|
||||
READ ( 1025 bytes): OKAY
|
||||
|
|
|
|||
|
|
@ -73,6 +73,11 @@ In the example, 'Requester ID' means the ID of the device who sends
|
|||
the error message to root port. Pls. refer to pci express specs for
|
||||
other fields.
|
||||
|
||||
2.4 AER Statistics / Counters
|
||||
|
||||
When PCIe AER errors are captured, the counters / statistics are also exposed
|
||||
in the form of sysfs attributes which are documented at
|
||||
Documentation/ABI/testing/sysfs-bus-pci-devices-aer_stats
|
||||
|
||||
3. Developer Guide
|
||||
|
||||
|
|
|
|||
|
|
@ -3089,8 +3089,31 @@
|
|||
See header of drivers/block/paride/pcd.c.
|
||||
See also Documentation/blockdev/paride.txt.
|
||||
|
||||
pci=option[,option...] [PCI] various PCI subsystem options:
|
||||
earlydump [X86] dump PCI config space before the kernel
|
||||
pci=option[,option...] [PCI] various PCI subsystem options.
|
||||
|
||||
Some options herein operate on a specific device
|
||||
or a set of devices (<pci_dev>). These are
|
||||
specified in one of the following formats:
|
||||
|
||||
[<domain>:]<bus>:<dev>.<func>[/<dev>.<func>]*
|
||||
pci:<vendor>:<device>[:<subvendor>:<subdevice>]
|
||||
|
||||
Note: the first format specifies a PCI
|
||||
bus/device/function address which may change
|
||||
if new hardware is inserted, if motherboard
|
||||
firmware changes, or due to changes caused
|
||||
by other kernel parameters. If the
|
||||
domain is left unspecified, it is
|
||||
taken to be zero. Optionally, a path
|
||||
to a device through multiple device/function
|
||||
addresses can be specified after the base
|
||||
address (this is more robust against
|
||||
renumbering issues). The second format
|
||||
selects devices using IDs from the
|
||||
configuration space which may match multiple
|
||||
devices in the system.
|
||||
|
||||
earlydump dump PCI config space before the kernel
|
||||
changes anything
|
||||
off [X86] don't probe for the PCI bus
|
||||
bios [X86-32] force use of PCI BIOS, don't access
|
||||
|
|
@ -3218,11 +3241,10 @@
|
|||
window. The default value is 64 megabytes.
|
||||
resource_alignment=
|
||||
Format:
|
||||
[<order of align>@][<domain>:]<bus>:<slot>.<func>[; ...]
|
||||
[<order of align>@]pci:<vendor>:<device>\
|
||||
[:<subvendor>:<subdevice>][; ...]
|
||||
[<order of align>@]<pci_dev>[; ...]
|
||||
Specifies alignment and device to reassign
|
||||
aligned memory resources.
|
||||
aligned memory resources. How to
|
||||
specify the device is described above.
|
||||
If <order of align> is not specified,
|
||||
PAGE_SIZE is used as alignment.
|
||||
PCI-PCI bridge can be specified, if resource
|
||||
|
|
@ -3265,6 +3287,15 @@
|
|||
Adding the window is slightly risky (it may
|
||||
conflict with unreported devices), so this
|
||||
taints the kernel.
|
||||
disable_acs_redir=<pci_dev>[; ...]
|
||||
Specify one or more PCI devices (in the format
|
||||
specified above) separated by semicolons.
|
||||
Each device specified will have the PCI ACS
|
||||
redirect capabilities forced off which will
|
||||
allow P2P traffic between devices through
|
||||
bridges without forcing it upstream. Note:
|
||||
this removes isolation between devices and
|
||||
may put more devices in an IOMMU group.
|
||||
|
||||
pcie_aspm= [PCIE] Forcibly enable or disable PCIe Active State Power
|
||||
Management.
|
||||
|
|
|
|||
|
|
@ -9,6 +9,9 @@ Required properties:
|
|||
|
||||
Optional properties:
|
||||
- max-functions: Maximum number of functions that can be configured (default 1).
|
||||
- phys: From PHY bindings: List of Generic PHY phandles. One per lane if more
|
||||
than one in the list. If only one PHY listed it must manage all lanes.
|
||||
- phy-names: List of names to identify the PHY.
|
||||
|
||||
Example:
|
||||
|
||||
|
|
@ -19,4 +22,6 @@ pcie@fc000000 {
|
|||
reg-names = "reg", "mem";
|
||||
cdns,max-outbound-regions = <16>;
|
||||
max-functions = /bits/ 8 <8>;
|
||||
phys = <&ep_phy0 &ep_phy1>;
|
||||
phy-names = "pcie-lane0","pcie-lane1";
|
||||
};
|
||||
|
|
|
|||
|
|
@ -24,6 +24,9 @@ Optional properties:
|
|||
translations (default 32)
|
||||
- vendor-id: The PCI vendor ID (16 bits, default is design dependent)
|
||||
- device-id: The PCI device ID (16 bits, default is design dependent)
|
||||
- phys: From PHY bindings: List of Generic PHY phandles. One per lane if more
|
||||
than one in the list. If only one PHY listed it must manage all lanes.
|
||||
- phy-names: List of names to identify the PHY.
|
||||
|
||||
Example:
|
||||
|
||||
|
|
@ -57,4 +60,7 @@ pcie@fb000000 {
|
|||
interrupt-map-mask = <0x0 0x0 0x0 0x7>;
|
||||
|
||||
msi-parent = <&its_pci>;
|
||||
|
||||
phys = <&pcie_phy0>;
|
||||
phy-names = "pcie-phy";
|
||||
};
|
||||
|
|
|
|||
|
|
@ -166,6 +166,7 @@ Code Seq#(hex) Include File Comments
|
|||
'P' all linux/soundcard.h conflict!
|
||||
'P' 60-6F sound/sscape_ioctl.h conflict!
|
||||
'P' 00-0F drivers/usb/class/usblp.c conflict!
|
||||
'P' 01-09 drivers/misc/pci_endpoint_test.c conflict!
|
||||
'Q' all linux/soundcard.h
|
||||
'R' 00-1F linux/random.h conflict!
|
||||
'R' 01 linux/rfkill.h conflict!
|
||||
|
|
|
|||
|
|
@ -10,6 +10,7 @@ The PCI driver for the test device performs the following tests
|
|||
*) verifying addresses programmed in BAR
|
||||
*) raise legacy IRQ
|
||||
*) raise MSI IRQ
|
||||
*) raise MSI-X IRQ
|
||||
*) read data
|
||||
*) write data
|
||||
*) copy data
|
||||
|
|
@ -25,6 +26,11 @@ ioctl
|
|||
PCITEST_LEGACY_IRQ: Tests legacy IRQ
|
||||
PCITEST_MSI: Tests message signalled interrupts. The MSI number
|
||||
to be tested should be passed as argument.
|
||||
PCITEST_MSIX: Tests message signalled interrupts. The MSI-X number
|
||||
to be tested should be passed as argument.
|
||||
PCITEST_SET_IRQTYPE: Changes driver IRQ type configuration. The IRQ type
|
||||
should be passed as argument (0: Legacy, 1:MSI, 2:MSI-X).
|
||||
PCITEST_GET_IRQTYPE: Gets driver IRQ type configuration.
|
||||
PCITEST_WRITE: Perform write tests. The size of the buffer should be passed
|
||||
as argument.
|
||||
PCITEST_READ: Perform read tests. The size of the buffer should be passed
|
||||
|
|
|
|||
|
|
@ -357,9 +357,6 @@ EXPORT_SYMBOL_GPL(dma_get_required_mask);
|
|||
|
||||
static int __init dma_init(void)
|
||||
{
|
||||
#ifdef CONFIG_PCI
|
||||
dma_debug_add_bus(&pci_bus_type);
|
||||
#endif
|
||||
#ifdef CONFIG_IBMVIO
|
||||
dma_debug_add_bus(&vio_bus_type);
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -160,8 +160,6 @@ static int __init pcibios_init(void)
|
|||
for (hose = hose_head; hose; hose = hose->next)
|
||||
pcibios_scanbus(hose);
|
||||
|
||||
dma_debug_add_bus(&pci_bus_type);
|
||||
|
||||
pci_initialized = 1;
|
||||
|
||||
return 0;
|
||||
|
|
|
|||
|
|
@ -15,8 +15,4 @@ extern void write_pci_config_byte(u8 bus, u8 slot, u8 func, u8 offset, u8 val);
|
|||
extern void write_pci_config_16(u8 bus, u8 slot, u8 func, u8 offset, u16 val);
|
||||
|
||||
extern int early_pci_allowed(void);
|
||||
|
||||
extern unsigned int pci_early_dump_regs;
|
||||
extern void early_dump_pci_device(u8 bus, u8 slot, u8 func);
|
||||
extern void early_dump_pci_devices(void);
|
||||
#endif /* _ASM_X86_PCI_DIRECT_H */
|
||||
|
|
|
|||
|
|
@ -155,9 +155,6 @@ static int __init pci_iommu_init(void)
|
|||
{
|
||||
struct iommu_table_entry *p;
|
||||
|
||||
#ifdef CONFIG_PCI
|
||||
dma_debug_add_bus(&pci_bus_type);
|
||||
#endif
|
||||
x86_init.iommu.iommu_init();
|
||||
|
||||
for (p = __iommu_table; p < __iommu_table_end; p++) {
|
||||
|
|
|
|||
|
|
@ -999,11 +999,6 @@ void __init setup_arch(char **cmdline_p)
|
|||
setup_clear_cpu_cap(X86_FEATURE_APIC);
|
||||
}
|
||||
|
||||
#ifdef CONFIG_PCI
|
||||
if (pci_early_dump_regs)
|
||||
early_dump_pci_devices();
|
||||
#endif
|
||||
|
||||
e820__reserve_setup_data();
|
||||
e820__finish_early_params();
|
||||
|
||||
|
|
|
|||
|
|
@ -22,7 +22,6 @@
|
|||
unsigned int pci_probe = PCI_PROBE_BIOS | PCI_PROBE_CONF1 | PCI_PROBE_CONF2 |
|
||||
PCI_PROBE_MMCONF;
|
||||
|
||||
unsigned int pci_early_dump_regs;
|
||||
static int pci_bf_sort;
|
||||
int pci_routeirq;
|
||||
int noioapicquirk;
|
||||
|
|
@ -599,9 +598,6 @@ char *__init pcibios_setup(char *str)
|
|||
pci_probe |= PCI_BIG_ROOT_WINDOW;
|
||||
return NULL;
|
||||
#endif
|
||||
} else if (!strcmp(str, "earlydump")) {
|
||||
pci_early_dump_regs = 1;
|
||||
return NULL;
|
||||
} else if (!strcmp(str, "routeirq")) {
|
||||
pci_routeirq = 1;
|
||||
return NULL;
|
||||
|
|
|
|||
|
|
@ -57,47 +57,3 @@ int early_pci_allowed(void)
|
|||
PCI_PROBE_CONF1;
|
||||
}
|
||||
|
||||
void early_dump_pci_device(u8 bus, u8 slot, u8 func)
|
||||
{
|
||||
u32 value[256 / 4];
|
||||
int i;
|
||||
|
||||
pr_info("pci 0000:%02x:%02x.%d config space:\n", bus, slot, func);
|
||||
|
||||
for (i = 0; i < 256; i += 4)
|
||||
value[i / 4] = read_pci_config(bus, slot, func, i);
|
||||
|
||||
print_hex_dump(KERN_INFO, "", DUMP_PREFIX_OFFSET, 16, 1, value, 256, false);
|
||||
}
|
||||
|
||||
void early_dump_pci_devices(void)
|
||||
{
|
||||
unsigned bus, slot, func;
|
||||
|
||||
if (!early_pci_allowed())
|
||||
return;
|
||||
|
||||
for (bus = 0; bus < 256; bus++) {
|
||||
for (slot = 0; slot < 32; slot++) {
|
||||
for (func = 0; func < 8; func++) {
|
||||
u32 class;
|
||||
u8 type;
|
||||
|
||||
class = read_pci_config(bus, slot, func,
|
||||
PCI_CLASS_REVISION);
|
||||
if (class == 0xffffffff)
|
||||
continue;
|
||||
|
||||
early_dump_pci_device(bus, slot, func);
|
||||
|
||||
if (func == 0) {
|
||||
type = read_pci_config_byte(bus, slot,
|
||||
func,
|
||||
PCI_HEADER_TYPE);
|
||||
if (!(type & 0x80))
|
||||
break;
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
|
|
|||
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