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sound updates for 4.12-rc1

It was a relatively calm development cycle, and no scaring changes are
 seen in both core and driver sides.  Here are some highlights:
 
 ASoC:
 - A new API for hooking up jacks more generically and easily
 - Card longname is set based on DMI for a unique UCM profile
 - Lots of Intel driver fixes: Atom, Broxton, Skylake and newer chips
 - New drivers for Cirrus CS35L35, DIO DIO2125, Everest ES7132,
   HiSilicon hi6210, Maxim MAX98927, MT2701 systems with WM8960, Nuvoton
   NAU8824, Odroid systems, ST STM32 SAI controllers and x86 systems with
   DA7213
 
 HD-audio:
 - Many new quirks to support headset for various devices (mostly ASUS
   ones) as usual
 - Support for dual codecs on some Gigabyte mobos and Lenovo laptop
 - Improvement on PCM position reporting for Skylake and newer
 
 FireWire:
 - New drivers for MOTU and RME Fireface series
 - Updates for Digidesign Digi00x and TASCAM series
 - Support for tracepoints
 
 Others:
 - USB-audio: improved support for quirk_alias option
 - Cleanups, constification allover the places
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Merge tag 'sound-4.12-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/tiwai/sound

Pull sound updates from Takashi Iwai:
 "It was a relatively calm development cycle, and no scaring changes are
  seen in both core and driver sides. Here are some highlights:

  ASoC:
   - A new API for hooking up jacks more generically and easily

   - Card longname is set based on DMI for a unique UCM profile

   - Lots of Intel driver fixes: Atom, Broxton, Skylake and newer chips

   - New drivers for Cirrus CS35L35, DIO DIO2125, Everest ES7132,
     HiSilicon hi6210, Maxim MAX98927, MT2701 systems with WM8960,
     Nuvoton NAU8824, Odroid systems, ST STM32 SAI controllers and x86
     systems with DA7213

  HD-audio:
   - Many new quirks to support headset for various devices (mostly ASUS
     ones) as usual

   - Support for dual codecs on some Gigabyte mobos and Lenovo laptop

   - Improvement on PCM position reporting for Skylake and newer

  FireWire:
   - New drivers for MOTU and RME Fireface series

   - Updates for Digidesign Digi00x and TASCAM series

   - Support for tracepoints

  Others:
   - USB-audio: improved support for quirk_alias option

   - Cleanups, constification allover the places"

* tag 'sound-4.12-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/tiwai/sound: (299 commits)
  ASoC: codec: wm8960: Relax bit clock computation when using PLL
  ASoC: codec: wm9860: avoid maybe-uninitialized warning
  ASoC: nau8824: leave Class D gain at chip default
  ASoC: nau8824: rename controls to match DAPM controls
  ASoC: Intel: Skylake: Return negative error code
  ASoC: Intel: Skylake: Fix unused variable warning
  ASoC: Intel: Skylake: fix uninitialized pointer use
  ASoC: sti: Fix error handling if of_clk_get() fails
  ASoC: cs4271: configure reset GPIO as output
  ASoC: dwc: Disallow building designware_pcm as a module
  ALSA: ali5451: fix spelling mistake in "ali_capture_preapre"
  ASoC: stm32: add SAI driver
  ASoC: stm32: add bindings for SAI
  ASoC: Intel: Skylake: Add loadable module support on KBL platform
  ASoC: Intel: Skylake: Modify load_lib_ipc arguments for a nowait version
  ASoC: Intel: Skylake: Register dsp_fw_ops for kabylake
  ASoC: Intel: Skylake: Modify arguments to reuse module transfer function
  ASoC: Intel: Skylake: Commonize library load
  ASoC: Intel: Skylake: Move sst common initialization to a helper function
  ASoC: nau8824: new driver
  ...
This commit is contained in:
Linus Torvalds 2017-05-03 11:58:59 -07:00
commit 221656e7c4
306 changed files with 19287 additions and 2691 deletions

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@ -0,0 +1,180 @@
CS35L35 Boosted Speaker Amplifier
Required properties:
- compatible : "cirrus,cs35l35"
- reg : the I2C address of the device for I2C
- VA-supply, VP-supply : power supplies for the device,
as covered in
Documentation/devicetree/bindings/regulator/regulator.txt.
- interrupt-parent : Specifies the phandle of the interrupt controller to
which the IRQs from CS35L35 are delivered to.
- interrupts : IRQ line info CS35L35.
(See Documentation/devicetree/bindings/interrupt-controller/interrupts.txt
for further information relating to interrupt properties)
Optional properties:
- reset-gpios : gpio used to reset the amplifier
- cirrus,stereo-config : Boolean to determine if there are 2 AMPs for a
Stereo configuration
- cirrus,audio-channel : Set Location of Audio Signal on Serial Port
0 = Data Packet received on Left I2S Channel
1 = Data Packet received on Right I2S Channel
- cirrus,advisory-channel : Set Location of Advisory Signal on Serial Port
0 = Data Packet received on Left I2S Channel
1 = Data Packet received on Right I2S Channel
- cirrus,shared-boost : Boolean to enable ClassH tracking of Advisory Signal
if 2 Devices share Boost BST_CTL
- cirrus,external-boost : Boolean to specify the device is using an external
boost supply, note that sharing a boost from another cs35l35 would constitute
using an external supply for the slave device
- cirrus,sp-drv-strength : Value for setting the Serial Port drive strength
Table 3-10 of the datasheet lists drive-strength specifications
0 = 1x (Default)
1 = .5x
- cirrus,sp-drv-unused : Determines how unused slots should be driven on the
Serial Port.
0 - Hi-Z
2 - Drive 0's (Default)
3 - Drive 1's
- cirrus,bst-pdn-fet-on : Boolean to determine if the Boost PDN control
powers down with a rectification FET On or Off. If VSPK is supplied
externally then FET is off.
- cirrus,boost-ctl-millivolt : Boost Voltage Value. Configures the boost
converter's output voltage in mV. The range is from 2600mV to 9000mV with
increments of 100mV.
(Default) VP
- cirrus,boost-peak-milliamp : Boost-converter peak current limit in mA.
Configures the peak current by monitoring the current through the boost FET.
Range starts at 1680mA and goes to a maximum of 4480mA with increments of
110mA.
(Default) 2.46 Amps
- cirrus,amp-gain-zc : Boolean to determine if to use Amplifier gain-change
zero-cross
Optional H/G Algorithm sub-node:
The cs35l35 node can have a single "cirrus,classh-internal-algo" sub-node
that will disable automatic control of the internal H/G Algorithm.
It is strongly recommended that the Datasheet be referenced when adjusting
or using these Class H Algorithm controls over the internal Algorithm.
Serious damage can occur to the Device and surrounding components.
- cirrus,classh-internal-algo : Sub-node for the Internal Class H Algorithm
See Section 4.3 Internal Class H Algorithm in the Datasheet.
If not used, the device manages the ClassH Algorithm internally.
Optional properties for the "cirrus,classh-internal-algo" Sub-node
Section 7.29 Class H Control
- cirrus,classh-bst-overide : Boolean
- cirrus,classh-bst-max-limit
- cirrus,classh-mem-depth
Section 7.30 Class H Headroom Control
- cirrus,classh-headroom
Section 7.31 Class H Release Rate
- cirrus,classh-release-rate
Section 7.32 Class H Weak FET Drive Control
- cirrus,classh-wk-fet-disable
- cirrus,classh-wk-fet-delay
- cirrus,classh-wk-fet-thld
Section 7.34 Class H VP Control
- cirrus,classh-vpch-auto
- cirrus,classh-vpch-rate
- cirrus,classh-vpch-man
Optional Monitor Signal Format sub-node:
The cs35l35 node can have a single "cirrus,monitor-signal-format" sub-node
for adjusting the Depth, Location and Frame of the Monitoring Signals
for Algorithms.
See Sections 4.8.2 through 4.8.4 Serial-Port Control in the Datasheet
-cirrus,monitor-signal-format : Sub-node for the Monitor Signaling Formating
on the I2S Port. Each of the 3 8 bit values in the array contain the settings
for depth, location, and frame.
If not used, the defaults for the 6 monitor signals is used.
Sections 7.44 - 7.53 lists values for the depth, location, and frame
for each monitoring signal.
- cirrus,imon : 4 8 bit values to set the depth, location, frame and ADC
scale of the IMON monitor signal.
- cirrus,vmon : 3 8 bit values to set the depth, location, and frame
of the VMON monitor signal.
- cirrus,vpmon : 3 8 bit values to set the depth, location, and frame
of the VPMON monitor signal.
- cirrus,vbstmon : 3 8 bit values to set the depth, location, and frame
of the VBSTMON monitor signal
- cirrus,vpbrstat : 3 8 bit values to set the depth, location, and frame
of the VPBRSTAT monitor signal
- cirrus,zerofill : 3 8 bit values to set the depth, location, and frame\
of the ZEROFILL packet in the monitor signal
Example:
cs35l35: cs35l35@20 {
compatible = "cirrus,cs35l35";
reg = <0x20>;
VA-supply = <&dummy_vreg>;
VP-supply = <&dummy_vreg>;
reset-gpios = <&axi_gpio 54 0>;
interrupt-parent = <&gpio8>;
interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
cirrus,boost-ctl-millivolt = <9000>;
cirrus,stereo-config;
cirrus,audio-channel = <0x00>;
cirrus,advisory-channel = <0x01>;
cirrus,shared-boost;
cirrus,classh-internal-algo {
cirrus,classh-bst-overide;
cirrus,classh-bst-max-limit = <0x01>;
cirrus,classh-mem-depth = <0x01>;
cirrus,classh-release-rate = <0x08>;
cirrus,classh-headroom-millivolt = <0x0B>;
cirrus,classh-wk-fet-disable = <0x01>;
cirrus,classh-wk-fet-delay = <0x04>;
cirrus,classh-wk-fet-thld = <0x01>;
cirrus,classh-vpch-auto = <0x01>;
cirrus,classh-vpch-rate = <0x02>;
cirrus,classh-vpch-man = <0x05>;
};
/* Depth, Location, Frame */
cirrus,monitor-signal-format {
cirrus,imon = /bits/ 8 <0x03 0x00 0x01>;
cirrus,vmon = /bits/ 8 <0x03 0x00 0x00>;
cirrus,vpmon = /bits/ 8 <0x03 0x04 0x00>;
cirrus,vbstmon = /bits/ 8 <0x03 0x04 0x01>;
cirrus,vpbrstat = /bits/ 8 <0x00 0x04 0x00>;
cirrus,zerofill = /bits/ 8 <0x00 0x00 0x00>;
};
};

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@ -0,0 +1,12 @@
DIO2125 Audio Driver
Required properties:
- compatible : "dioo,dio2125"
- enable-gpios : the gpio connected to the enable pin of the dio2125
Example:
amp: analog-amplifier {
compatible = "dioo,dio2125";
enable-gpios = <&gpio GPIOH_3 0>;
};

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@ -0,0 +1,10 @@
ES7134 i2s DA converter
Required properties:
- compatible : "everest,es7134" or "everest,es7144"
Example:
i2s_codec: external-codec {
compatible = "everest,es7134";
};

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@ -20,24 +20,8 @@ Required properties:
have.
- interrupt-parent: The phandle for the interrupt controller that
services interrupts for this device.
- fsl,playback-dma: Phandle to a node for the DMA channel to use for
playback of audio. This is typically dictated by SOC
design. See the notes below.
- fsl,capture-dma: Phandle to a node for the DMA channel to use for
capture (recording) of audio. This is typically dictated
by SOC design. See the notes below.
- fsl,fifo-depth: The number of elements in the transmit and receive FIFOs.
This number is the maximum allowed value for SFCSR[TFWM0].
- fsl,ssi-asynchronous:
If specified, the SSI is to be programmed in asynchronous
mode. In this mode, pins SRCK, STCK, SRFS, and STFS must
all be connected to valid signals. In synchronous mode,
SRCK and SRFS are ignored. Asynchronous mode allows
playback and capture to use different sample sizes and
sample rates. Some drivers may require that SRCK and STCK
be connected together, and SRFS and STFS be connected
together. This would still allow different sample sizes,
but not different sample rates.
- clocks: "ipg" - Required clock for the SSI unit
"baud" - Required clock for SSI master mode. Otherwise this
clock is not used
@ -61,6 +45,24 @@ Optional properties:
- fsl,mode: The operating mode for the AC97 interface only.
"ac97-slave" - AC97 mode, SSI is clock slave
"ac97-master" - AC97 mode, SSI is clock master
- fsl,ssi-asynchronous:
If specified, the SSI is to be programmed in asynchronous
mode. In this mode, pins SRCK, STCK, SRFS, and STFS must
all be connected to valid signals. In synchronous mode,
SRCK and SRFS are ignored. Asynchronous mode allows
playback and capture to use different sample sizes and
sample rates. Some drivers may require that SRCK and STCK
be connected together, and SRFS and STFS be connected
together. This would still allow different sample sizes,
but not different sample rates.
- fsl,playback-dma: Phandle to a node for the DMA channel to use for
playback of audio. This is typically dictated by SOC
design. See the notes below.
Only used on Power Architecture.
- fsl,capture-dma: Phandle to a node for the DMA channel to use for
capture (recording) of audio. This is typically dictated
by SOC design. See the notes below.
Only used on Power Architecture.
Child 'codec' node required properties:
- compatible: Compatible list, contains the name of the codec

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@ -0,0 +1,42 @@
* Hisilicon 6210 i2s controller
Required properties:
- compatible: should be one of the following:
- "hisilicon,hi6210-i2s"
- reg: physical base address of the i2s controller unit and length of
memory mapped region.
- interrupts: should contain the i2s interrupt.
- clocks: a list of phandle + clock-specifier pairs, one for each entry
in clock-names.
- clock-names: should contain following:
- "dacodec"
- "i2s-base"
- dmas: DMA specifiers for tx dma. See the DMA client binding,
Documentation/devicetree/bindings/dma/dma.txt
- dma-names: should be "tx" and "rx"
- hisilicon,sysctrl-syscon: phandle to sysctrl syscon
- #sound-dai-cells: Should be set to 1 (for multi-dai)
- The dai cell indexes reference the following interfaces:
0: S2 interface
(Currently that is the only one available, but more may be
supported in the future)
Example for the hi6210 i2s controller:
i2s0: i2s@f7118000{
compatible = "hisilicon,hi6210-i2s";
reg = <0x0 0xf7118000 0x0 0x8000>; /* i2s unit */
interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>; /* 155 "DigACodec_intr"-32 */
clocks = <&sys_ctrl HI6220_DACODEC_PCLK>,
<&sys_ctrl HI6220_BBPPLL0_DIV>;
clock-names = "dacodec", "i2s-base";
dmas = <&dma0 15 &dma0 14>;
dma-names = "rx", "tx";
hisilicon,sysctrl-syscon = <&sys_ctrl>;
#sound-dai-cells = <1>;
};
Then when referencing the i2s controller:
sound-dai = <&i2s0 0>; /* index 0 => S2 interface */

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@ -1,22 +0,0 @@
max98925 audio CODEC
This device supports I2C.
Required properties:
- compatible : "maxim,max98925"
- vmon-slot-no : slot number used to send voltage information
- imon-slot-no : slot number used to send current information
- reg : the I2C address of the device for I2C
Example:
codec: max98925@1a {
compatible = "maxim,max98925";
vmon-slot-no = <0>;
imon-slot-no = <2>;
reg = <0x1a>;
};

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@ -1,32 +0,0 @@
max98926 audio CODEC
This device supports I2C.
Required properties:
- compatible : "maxim,max98926"
- vmon-slot-no : slot number used to send voltage information
or in inteleave mode this will be used as
interleave slot.
- imon-slot-no : slot number used to send current information
- interleave-mode : When using two MAX98926 in a system it is
possible to create ADC data that that will
overflow the frame size. Digital Audio Interleave
mode provides a means to output VMON and IMON data
from two devices on a single DOUT line when running
smaller frames sizes such as 32 BCLKS per LRCLK or
48 BCLKS per LRCLK.
- reg : the I2C address of the device for I2C
Example:
codec: max98926@1a {
compatible = "maxim,max98926";
vmon-slot-no = <0>;
imon-slot-no = <2>;
reg = <0x1a>;
};

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@ -0,0 +1,41 @@
Maxim Integrated MAX98925/MAX98926/MAX98927 Speaker Amplifier
This device supports I2C.
Required properties:
- compatible : should be one of the following
- "maxim,max98925"
- "maxim,max98926"
- "maxim,max98927"
- vmon-slot-no : slot number used to send voltage information
or in inteleave mode this will be used as
interleave slot.
MAX98925/MAX98926 slot range : 0 ~ 30, Default : 0
MAX98927 slot range : 0 ~ 15, Default : 0
- imon-slot-no : slot number used to send current information
MAX98925/MAX98926 slot range : 0 ~ 30, Default : 0
MAX98927 slot range : 0 ~ 15, Default : 0
- interleave-mode : When using two MAX9892X in a system it is
possible to create ADC data that that will
overflow the frame size. Digital Audio Interleave
mode provides a means to output VMON and IMON data
from two devices on a single DOUT line when running
smaller frames sizes such as 32 BCLKS per LRCLK or
48 BCLKS per LRCLK.
Range : 0 (off), 1 (on), Default : 0
- reg : the I2C address of the device for I2C
Example:
codec: max98927@3a {
compatible = "maxim,max98927";
vmon-slot-no = <0>;
imon-slot-no = <1>;
interleave-mode = <0>;
reg = <0x3a>;
};

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@ -0,0 +1,24 @@
MT2701 with WM8960 CODEC
Required properties:
- compatible: "mediatek,mt2701-wm8960-machine"
- mediatek,platform: the phandle of MT2701 ASoC platform
- audio-routing: a list of the connections between audio
- mediatek,audio-codec: the phandles of wm8960 codec
- pinctrl-names: Should contain only one value - "default"
- pinctrl-0: Should specify pin control groups used for this controller.
Example:
sound:sound {
compatible = "mediatek,mt2701-wm8960-machine";
mediatek,platform = <&afe>;
audio-routing =
"Headphone", "HP_L",
"Headphone", "HP_R",
"LINPUT1", "AMIC",
"RINPUT1", "AMIC";
mediatek,audio-codec = <&wm8960>;
pinctrl-names = "default";
pinctrl-0 = <&aud_pins_default>;
};

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@ -0,0 +1,88 @@
Nuvoton NAU8824 audio codec
This device supports I2C only.
Required properties:
- compatible : Must be "nuvoton,nau8824"
- reg : the I2C address of the device. This is either 0x1a (CSB=0) or 0x1b (CSB=1).
Optional properties:
- nuvoton,jkdet-polarity: JKDET pin polarity. 0 - active high, 1 - active low.
- nuvoton,vref-impedance: VREF Impedance selection
0 - Open
1 - 25 kOhm
2 - 125 kOhm
3 - 2.5 kOhm
- nuvoton,micbias-voltage: Micbias voltage level.
0 - VDDA
1 - VDDA
2 - VDDA * 1.1
3 - VDDA * 1.2
4 - VDDA * 1.3
5 - VDDA * 1.4
6 - VDDA * 1.53
7 - VDDA * 1.53
- nuvoton,sar-threshold-num: Number of buttons supported
- nuvoton,sar-threshold: Impedance threshold for each button. Array that contains up to 8 buttons configuration. SAR value is calculated as
SAR = 255 * MICBIAS / SAR_VOLTAGE * R / (2000 + R)
where MICBIAS is configured by 'nuvoton,micbias-voltage', SAR_VOLTAGE is configured by 'nuvoton,sar-voltage', R - button impedance.
Refer datasheet section 10.2 for more information about threshold calculation.
- nuvoton,sar-hysteresis: Button impedance measurement hysteresis.
- nuvoton,sar-voltage: Reference voltage for button impedance measurement.
0 - VDDA
1 - VDDA
2 - VDDA * 1.1
3 - VDDA * 1.2
4 - VDDA * 1.3
5 - VDDA * 1.4
6 - VDDA * 1.53
7 - VDDA * 1.53
- nuvoton,sar-compare-time: SAR compare time
0 - 500 ns
1 - 1 us
2 - 2 us
3 - 4 us
- nuvoton,sar-sampling-time: SAR sampling time
0 - 2 us
1 - 4 us
2 - 8 us
3 - 16 us
- nuvoton,short-key-debounce: Button short key press debounce time.
0 - 30 ms
1 - 50 ms
2 - 100 ms
- nuvoton,jack-eject-debounce: Jack ejection debounce time.
0 - 0 ms
1 - 1 ms
2 - 10 ms
Example:
headset: nau8824@1a {
compatible = "nuvoton,nau8824";
reg = <0x1a>;
interrupt-parent = <&gpio>;
interrupts = <TEGRA_GPIO(E, 6) IRQ_TYPE_LEVEL_LOW>;
nuvoton,vref-impedance = <2>;
nuvoton,micbias-voltage = <6>;
// Setup 4 buttons impedance according to Android specification
nuvoton,sar-threshold-num = <4>;
nuvoton,sar-threshold = <0xc 0x1e 0x38 0x60>;
nuvoton,sar-hysteresis = <0>;
nuvoton,sar-voltage = <6>;
nuvoton,sar-compare-time = <1>;
nuvoton,sar-sampling-time = <1>;
nuvoton,short-key-debounce = <0>;
nuvoton,jack-eject-debounce = <1>;
};

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@ -9,6 +9,7 @@ Required properties:
- "rockchip,rk3066-i2s": for rk3066
- "rockchip,rk3188-i2s", "rockchip,rk3066-i2s": for rk3188
- "rockchip,rk3288-i2s", "rockchip,rk3066-i2s": for rk3288
- "rockchip,rk3368-i2s", "rockchip,rk3066-i2s": for rk3368
- "rockchip,rk3399-i2s", "rockchip,rk3066-i2s": for rk3399
- reg: physical base address of the controller and length of memory mapped
region.

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@ -0,0 +1,57 @@
Samsung Exynos Odroid XU3/XU4 audio complex with MAX98090 codec
Required properties:
- compatible - "samsung,odroidxu3-audio" - for Odroid XU3 board,
"samsung,odroidxu4-audio" - for Odroid XU4 board
- model - the user-visible name of this sound complex
- 'cpu' subnode with a 'sound-dai' property containing the phandle of the I2S
controller
- 'codec' subnode with a 'sound-dai' property containing list of phandles
to the CODEC nodes, first entry must be corresponding to the MAX98090
CODEC and the second entry must be the phandle of the HDMI IP block node
- clocks - should contain entries matching clock names in the clock-names
property
- clock-names - should contain following entries:
- "epll" - indicating the EPLL output clock
- "i2s_rclk" - indicating the RCLK (root) clock of the I2S0 controller
- samsung,audio-widgets - this property specifies off-codec audio elements
like headphones or speakers, for details see widgets.txt
- samsung,audio-routing - a list of the connections between audio
components; each entry is a pair of strings, the first being the
connection's sink, the second being the connection's source;
valid names for sources and sinks are the MAX98090's pins (as
documented in its binding), and the jacks on the board
For Odroid X2:
"Headphone Jack", "Mic Jack", "DMIC"
For Odroid U3, XU3:
"Headphone Jack", "Speakers"
For Odroid XU4:
no entries
Example:
sound {
compatible = "samsung,odroidxu3-audio";
samsung,cpu-dai = <&i2s0>;
samsung,codec-dai = <&max98090>;
model = "Odroid-XU3";
samsung,audio-routing =
"Headphone Jack", "HPL",
"Headphone Jack", "HPR",
"IN1", "Mic Jack",
"Mic Jack", "MICBIAS";
clocks = <&clock CLK_FOUT_EPLL>, <&i2s0 CLK_I2S_RCLK_SRC>;
clock-names = "epll", "sclk_i2s";
cpu {
sound-dai = <&i2s0 0>;
};
codec {
sound-dai = <&hdmi>, <&max98090>;
};
};

View file

@ -26,6 +26,15 @@ Optional properties:
If this node is not mentioned or the value is unknown, then
the value is set to 1.25V.
- lrclk-strength: the LRCLK pad strength. Possible values are:
0, 1, 2 and 3 as per the table below:
VDDIO 1.8V 2.5V 3.3V
0 = Disable
1 = 1.66 mA 2.87 mA 4.02 mA
2 = 3.33 mA 5.74 mA 8.03 mA
3 = 4.99 mA 8.61 mA 12.05 mA
Example:
codec: sgtl5000@0a {

View file

@ -0,0 +1,89 @@
STMicroelectronics STM32 Serial Audio Interface (SAI).
The SAI interface (Serial Audio Interface) offers a wide set of audio protocols
as I2S standards, LSB or MSB-justified, PCM/DSP, TDM, and AC'97.
The SAI contains two independent audio sub-blocks. Each sub-block has
its own clock generator and I/O lines controller.
Required properties:
- compatible: Should be "st,stm32f4-sai"
- reg: Base address and size of SAI common register set.
- clocks: Must contain phandle and clock specifier pairs for each entry
in clock-names.
- clock-names: Must contain "x8k" and "x11k"
"x8k": SAI parent clock for sampling rates multiple of 8kHz.
"x11k": SAI parent clock for sampling rates multiple of 11.025kHz.
- interrupts: cpu DAI interrupt line shared by SAI sub-blocks
Optional properties:
- resets: Reference to a reset controller asserting the SAI
SAI subnodes:
Two subnodes corresponding to SAI sub-block instances A et B can be defined.
Subnode can be omitted for unsused sub-block.
SAI subnodes required properties:
- compatible: Should be "st,stm32-sai-sub-a" or "st,stm32-sai-sub-b"
for SAI sub-block A or B respectively.
- reg: Base address and size of SAI sub-block register set.
- clocks: Must contain one phandle and clock specifier pair
for sai_ck which feeds the internal clock generator.
- clock-names: Must contain "sai_ck".
- dmas: see Documentation/devicetree/bindings/dma/stm32-dma.txt
- dma-names: identifier string for each DMA request line
"tx": if sai sub-block is configured as playback DAI
"rx": if sai sub-block is configured as capture DAI
- pinctrl-names: should contain only value "default"
- pinctrl-0: see Documentation/devicetree/bindings/pinctrl/pinctrl-stm32.txt
Example:
sound_card {
compatible = "audio-graph-card";
dais = <&sai1b_port>;
};
sai1: sai1@40015800 {
compatible = "st,stm32f4-sai";
#address-cells = <1>;
#size-cells = <1>;
ranges;
reg = <0x40015800 0x4>;
clocks = <&rcc 1 CLK_SAIQ_PDIV>, <&rcc 1 CLK_I2SQ_PDIV>;
clock-names = "x8k", "x11k";
interrupts = <87>;
sai1b: audio-controller@40015824 {
#sound-dai-cells = <0>;
compatible = "st,stm32-sai-sub-b";
reg = <0x40015824 0x1C>;
clocks = <&rcc 1 CLK_SAI2>;
clock-names = "sai_ck";
dmas = <&dma2 5 0 0x400 0x0>;
dma-names = "tx";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_sai1b>;
ports {
#address-cells = <1>;
#size-cells = <0>;
sai1b_port: port@0 {
reg = <0>;
cpu_endpoint: endpoint {
remote-endpoint = <&codec_endpoint>;
audio-graph-card,format = "i2s";
audio-graph-card,bitclock-master = <&codec_endpoint>;
audio-graph-card,frame-master = <&codec_endpoint>;
};
};
};
};
};
audio-codec {
codec_port: port {
codec_endpoint: endpoint {
remote-endpoint = <&cpu_endpoint>;
};
};
};

View file

@ -5,7 +5,8 @@ The tas2552 serial control bus communicates through I2C protocols
Required properties:
- compatible - One of:
"ti,tas2552" - TAS2552
- reg - I2C slave address
- reg - I2C slave address: it can be 0x40 if ADDR pin is 0
or 0x41 if ADDR pin is 1.
- supply-*: Required supply regulators are:
"vbat" battery voltage
"iovdd" I/O Voltage
@ -14,17 +15,20 @@ Required properties:
Optional properties:
- enable-gpio - gpio pin to enable/disable the device
tas2552 can receive it's reference clock via MCLK, BCLK, IVCLKIN pin or use the
tas2552 can receive its reference clock via MCLK, BCLK, IVCLKIN pin or use the
internal 1.8MHz. This CLKIN is used by the PLL. In addition to PLL, the PDM
reference clock is also selectable: PLL, IVCLKIN, BCLK or MCLK.
For system integration the dt-bindings/sound/tas2552.h header file provides
defined values to selct and configure the PLL and PDM reference clocks.
defined values to select and configure the PLL and PDM reference clocks.
Example:
tas2552: tas2552@41 {
compatible = "ti,tas2552";
reg = <0x41>;
vbat-supply = <&reg_vbat>;
iovdd-supply = <&reg_iovdd>;
avdd-supply = <&reg_avdd>;
enable-gpio = <&gpio4 2 GPIO_ACTIVE_HIGH>;
};

View file

@ -28,6 +28,14 @@ Optional properties:
performed. If any entry has the value 0xffffffff, that GPIO's
configuration will not be modified.
- AVDD-supply : Analog power supply regulator on the AVDD pin.
- CPVDD-supply : Charge pump supply regulator on the CPVDD pin.
- DBVDD-supply : Digital buffer supply regulator for the DBVDD pin.
- DCVDD-supply : Digital core supply regulator for the DCVDD pin.
Pins on the device (for linking into audio routes):
* IN1L
@ -54,6 +62,11 @@ codec: wm8903@1a {
reg = <0x1a>;
interrupts = < 347 >;
AVDD-supply = <&fooreg_a>;
CPVDD-supply = <&fooreg_b>;
DBVDD-supply = <&fooreg_c>;
DCVDC-supply = <&fooreg_d>;
gpio-controller;
#gpio-cells = <2>;

View file

@ -0,0 +1,30 @@
ZTE TDM DAI driver
Required properties:
- compatible : should be one of the following.
* zte,zx296718-tdm
- reg : physical base address of the controller and length of memory mapped
region.
- clocks : Pairs of phandle and specifier referencing the controller's clocks.
- clock-names: "wclk" for the wclk.
"pclk" for the pclk.
-#clock-cells: should be 1.
- zte,tdm-dma-sysctrl : Reference to the sysctrl controller controlling
the dma. includes:
phandle of sysctrl.
register offset in sysctrl for control dma.
mask of the register that be written to sysctrl.
Example:
tdm: tdm@1487000 {
compatible = "zte,zx296718-tdm";
reg = <0x01487000 0x1000>;
clocks = <&audiocrm AUDIO_TDM_WCLK>, <&audiocrm AUDIO_TDM_PCLK>;
clock-names = "wclk", "pclk";
#clock-cells = <1>;
pinctrl-names = "default";
pinctrl-0 = <&tdm_global_pin>;
zte,tdm-dma-sysctrl = <&sysctrl 0x10c 4>;
};

View file

@ -494,6 +494,8 @@ add_hp_mic (bool)
hp_mic_detect (bool)
enable/disable the hp/mic shared input for a single built-in mic
case; default true
vmaster (bool)
enable/disable the virtual Master control; default true
mixer_nid (int)
specifies the widget NID of the analog-loopback mixer

108
include/sound/cs35l35.h Normal file
View file

@ -0,0 +1,108 @@
/*
* linux/sound/cs35l35.h -- Platform data for CS35l35
*
* Copyright (c) 2016 Cirrus Logic Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef __CS35L35_H
#define __CS35L35_H
struct classh_cfg {
/*
* Class H Algorithm Control Variables
* You can either have it done
* automatically or you can adjust
* these variables for tuning
*
* if you do not enable the internal algorithm
* you will get a set of mixer controls for
* Class H tuning
*
* Section 4.3 of the datasheet
*/
bool classh_bst_override;
bool classh_algo_enable;
int classh_bst_max_limit;
int classh_mem_depth;
int classh_release_rate;
int classh_headroom;
int classh_wk_fet_disable;
int classh_wk_fet_delay;
int classh_wk_fet_thld;
int classh_vpch_auto;
int classh_vpch_rate;
int classh_vpch_man;
};
struct monitor_cfg {
/*
* Signal Monitor Data
* highly configurable signal monitoring
* data positioning and different types of
* monitoring data.
*
* Section 4.8.2 - 4.8.4 of the datasheet
*/
bool is_present;
bool imon_specs;
bool vmon_specs;
bool vpmon_specs;
bool vbstmon_specs;
bool vpbrstat_specs;
bool zerofill_specs;
u8 imon_dpth;
u8 imon_loc;
u8 imon_frm;
u8 imon_scale;
u8 vmon_dpth;
u8 vmon_loc;
u8 vmon_frm;
u8 vpmon_dpth;
u8 vpmon_loc;
u8 vpmon_frm;
u8 vbstmon_dpth;
u8 vbstmon_loc;
u8 vbstmon_frm;
u8 vpbrstat_dpth;
u8 vpbrstat_loc;
u8 vpbrstat_frm;
u8 zerofill_dpth;
u8 zerofill_loc;
u8 zerofill_frm;
};
struct cs35l35_platform_data {
/* Stereo (2 Device) */
bool stereo;
/* serial port drive strength */
int sp_drv_str;
/* serial port drive in unused slots */
int sp_drv_unused;
/* Boost Power Down with FET */
bool bst_pdn_fet_on;
/* Boost Voltage : used if ClassH Algo Enabled */
int bst_vctl;
/* Boost Converter Peak Current CTRL */
int bst_ipk;
/* Amp Gain Zero Cross */
bool gain_zc;
/* Audio Input Location */
int aud_channel;
/* Advisory Input Location */
int adv_channel;
/* Shared Boost for stereo */
bool shared_bst;
/* Specifies this amp is using an external boost supply */
bool ext_bst;
/* ClassH Algorithm */
struct classh_cfg classh_algo;
/* Monitor Config */
struct monitor_cfg mon_cfg;
};
#endif /* __CS35L35_H */

View file

@ -106,8 +106,26 @@ enum { SDI0, SDI1, SDI2, SDI3, SDO0, SDO1, SDO2, SDO3 };
#define AZX_REG_HSW_EM4 0x100c
#define AZX_REG_HSW_EM5 0x1010
/* Skylake/Broxton display HD-A controller Extended Mode registers */
#define AZX_REG_SKL_EM4L 0x1040
/* Skylake/Broxton vendor-specific registers */
#define AZX_REG_VS_EM1 0x1000
#define AZX_REG_VS_INRC 0x1004
#define AZX_REG_VS_OUTRC 0x1008
#define AZX_REG_VS_FIFOTRK 0x100C
#define AZX_REG_VS_FIFOTRK2 0x1010
#define AZX_REG_VS_EM2 0x1030
#define AZX_REG_VS_EM3L 0x1038
#define AZX_REG_VS_EM3U 0x103C
#define AZX_REG_VS_EM4L 0x1040
#define AZX_REG_VS_EM4U 0x1044
#define AZX_REG_VS_LTRC 0x1048
#define AZX_REG_VS_D0I3C 0x104A
#define AZX_REG_VS_PCE 0x104B
#define AZX_REG_VS_L2MAGC 0x1050
#define AZX_REG_VS_L2LAHPT 0x1054
#define AZX_REG_VS_SDXDPIB_XBASE 0x1084
#define AZX_REG_VS_SDXDPIB_XINTERVAL 0x20
#define AZX_REG_VS_SDXEFIFOS_XBASE 0x1094
#define AZX_REG_VS_SDXEFIFOS_XINTERVAL 0x20
/* PCI space */
#define AZX_PCIREG_TCSEL 0x44
@ -243,9 +261,11 @@ enum { SDI0, SDI1, SDI2, SDI3, SDO0, SDO1, SDO2, SDO3 };
#define AZX_REG_ML_LOUTPAY 0x20
#define AZX_REG_ML_LINPAY 0x30
#define AZX_MLCTL_SPA (1<<16)
#define AZX_MLCTL_CPA 23
#define ML_LCTL_SCF_MASK 0xF
#define AZX_MLCTL_SPA (0x1 << 16)
#define AZX_MLCTL_CPA (0x1 << 23)
#define AZX_MLCTL_SPA_SHIFT 16
#define AZX_MLCTL_CPA_SHIFT 23
/* registers for DMA Resume Capability Structure */
#define AZX_DRSM_CAP_ID 0x5

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