I've wasted half a day hunting a bug that could easily be spotted by
gcc. Prevent this from reoccurring.
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Signed-off-by: Eric Anholt <eric@anholt.net>
Daniel Vetterauthored and Eric Anholtcommited 2009-11-05 14:47:06 -08:00
Render standy allows the GPU to power down the render unit when idle.
In order for this to work, it needs a page of graphics memory to save
state. This patch allocates that page and enables the feature on
supported chipsets.
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Eric Anholt <eric@anholt.net>
Jesse Barnesauthored and Eric Anholtcommited 2009-11-05 14:47:06 -08:00
This brings some hardware workaround for HDMI port on PCH (Ibex Peak),
which fixes unstable issues like during rotation.
Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
Signed-off-by: Eric Anholt <eric@anholt.net>
Zhenyu Wangauthored and Eric Anholtcommited 2009-11-05 14:03:28 -08:00
When the ideal error range can't be reached, this will safely use
a most closed one. Clean up some dumb codes in DPLL function too.
This fixes DPLL clock issue against one monitor at 1680x1050@60hz.
Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
Signed-off-by: Eric Anholt <eric@anholt.net>
Zhenyu Wangauthored and Eric Anholtcommited 2009-11-05 14:00:32 -08:00
Miles Lane reported the following error:
2 locks held by cat/4179:
#0: (&p->lock){+.+.+.}, at: [<c10a3884>] seq_read+0x25/0x315
#1: (&dev_priv->mm.active_list_lock){+.+...}, at: [<c119a854>]
i915_batchbuffer_info+0x2b/0x124
Pid: 4179, comm: cat Not tainted 2.6.32-rc5-git1 #2
Call Trace:
[<c104874f>] ? __debug_show_held_locks+0x1e/0x20
[<c1023fb0>] __might_sleep+0xf0/0xf7
[<c101c393>] kmap+0x17/0x58
[<c119a8d6>] i915_batchbuffer_info+0xad/0x124
[<c10a39bf>] seq_read+0x160/0x315
[<c108fb8c>] ? rw_verify_area+0x98/0xbb
[<c10a385f>] ? seq_read+0x0/0x315
[<c1090331>] vfs_read+0x75/0xa9
[<c10903f9>] sys_read+0x3b/0x5d
[<c1002a8f>] sysenter_do_call+0x12/0x36
The fix is relatively simple, use the atomic variants of kmap() that
avoid the potential sleep.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Miles Lane <miles.lane@gmail.com>
Signed-off-by: Eric Anholt <eric@anholt.net>
Chris Wilsonauthored and Eric Anholtcommited 2009-11-05 13:33:22 -08:00
* 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/anholt/drm-intel:
drm/i915: Ironlake suspend/resume support
drm/i915: kill warning in intel_find_pll_g4x_dp
drm/i915: update watermarks before enabling PLLs
drm/i915: add FIFO watermark support for G4x
drm/i915: quiet DP i2c init
drm/i915: fix panel fitting filter coefficient select for Ironlake
drm/i915: fix to setup display reference clock control on Ironlake
drm/i915: Install a fence register for fbc on g4x
drm/i915: save/restore BLC histogram control reg across suspend/resume
drm/i915: Fix FDI M/N setting according with correct color depth
drm/i915: disable powersave feature for Ironlake currently
drm/i915: Fix render reclock availability detection.
drm/i915: Save and restore the GM45 FBC regs on suspend and resume.
drm/i915: Set the LVDS_BORDER when using LVDS scaling mode
drm/i915: disable FBC for Pineview, fixing a boot hang.
In commit c1c7af6089 ("drm/i915: force
mode set at lid open time") the intel graphics driver was taught to
restore the LVDS mode on lid open.
That caused problems with interaction with the suspend/resume code,
which commonly runs at the same time (suspend is often caused by the lid
close event, while lid open is commonly a resume event), which was
worked around with in commit 06891e27a9
("drm/i915: fix suspend/resume breakage in lid notifier").
However, in the meantime the lid event code had also grown a user event
notifier (commit 06324194ee: "drm/i915:
generate a KMS uevent at lid open/close time"), and now _that_ causes
problems with suspend/resume and some versions of Xorg reacting to those
uevents by setting the mode.
So this effectively reverts that commit 06324194ee, and makes the lid
open protection logic against suspend/resume more explicit. This fixes
at least one laptop. See
http://bugzilla.kernel.org/show_bug.cgi?id=14484
for more details.
Acked-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Cc: Riccardo Magliocchetti <riccardo.magliocchetti@gmail.com>
Cc: Eric Anholt <eric@anholt.net>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
This sets the fbcon to use TRUECOLOR by default, it then
only modifies the pseudo palette for fbcon, and only touches
the real palette when in 8-bit pseudo color mode.
Signed-off-by: Dave Airlie <airlied@redhat.com>
Sometimes we will get the incorrect display modeline when parsing the detailed
timing in EDID. For example:
>hsync/vsync width is zero
>sync is beyond the blank.
So add the basic check for the detailed timing in EDID to avoid the incorrect
display modeline.
Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Zhao Yakuiauthored and Dave Airliecommited 2009-10-28 11:23:39 +10:00
Since we register all radeon devices, and the arbiter only cares about
VGA class ones, we will fail to startup on display controller class devices.
We don't gain anything by using the return value here.
this helps kms on sparc64 get started.
Reported-by: David S. Miller <davem@davemloft.net>
Signed-off-by: Dave Airlie <airlied@redhat.com>
This adds registers save/restore for Ironlake to make suspend work.
Signed-off-by: Guo, Chaohong <chaohong.guo@intel.com>
[zhenyuw: some code re-orgnization, and add more save/restore for
FDI link and transcoder registers, also fix palette register for Ironlake]
Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
Signed-off-by: Eric Anholt <eric@anholt.net>
Zhenyu Wangauthored and Eric Anholtcommited 2009-10-23 11:31:26 -07:00
When coming back from DPMS or turning on a display, make sure we have
the watermarks set up before turning on the display plane, otherwise we
may get underruns.
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Tested-by: Dirk Hohndel <hohndel@infradead.org>
Signed-off-by: Eric Anholt <eric@anholt.net>
Jesse Barnesauthored and Eric Anholtcommited 2009-10-23 11:31:18 -07:00
Turns out G4x needs to have sensible watermarks set, especially for
self-refresh enabled modes. Add support for it.
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Tested-by: Dirk Hohndel <hohndel@infradead.org>
Signed-off-by: Eric Anholt <eric@anholt.net>
Jesse Barnesauthored and Eric Anholtcommited 2009-10-23 11:31:08 -07:00
Must set filter selection as hardcoded coefficients for medium 3x3
filtering, which matches vbios setting for Ironlake.
This fixes display corrupt issue on HP arrandale with new vbios.
Cc: Stable Team <stable@kernel.org>
Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
Signed-off-by: Eric Anholt <eric@anholt.net>
Zhenyu Wangauthored and Eric Anholtcommited 2009-10-19 11:03:43 -07:00
For new stepping of PCH, the display reference clock
is fully under driver's control. This one trys to setup
all needed reference clock for different outputs. Older
stepping of PCH chipset should be ignoring this.
This fixes output failure issue on newer PCH which requires
driver to take control of reference clock enabling.
Cc: Stable Team <stable@kernel.org>
Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
Signed-off-by: Eric Anholt <eric@anholt.net>
Zhenyu Wangauthored and Eric Anholtcommited 2009-10-19 11:03:37 -07:00
To enable framebuffer compression on a g4x, we not only need the buffer
to tiled (X only), we also need to hold a fence register for the buffer.
Currently we only install a fence register for pre-i965s when setting up
the scanout buffer. Rather than adding some convoluted logic to
g4x_enable_fbc() to acquire a fence register, and perhaps to
g4x_disable_fbc() to release it again, we can extend the acquisition
during setup to all chipsets.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Eric Anholt <eric@anholt.net>
Chris Wilsonauthored and Eric Anholtcommited 2009-10-15 09:20:58 -07:00
Turns out some machines, like the ThinkPad X40 don't come back if you
don't save/restore this register.
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Eric Anholt <eric@anholt.net>
Jesse Barnesauthored and Eric Anholtcommited 2009-10-15 09:20:48 -07:00
FDI M/N calculation hasn't taken the current pipe color depth into account,
but always set as 24bpp. This one checks current pipe color depth setting,
and change FDI M/N calculation a little to use bits_per_pixel first, then
convert to bytes_per_pixel later.
This fixes display corrupt issue on Arrandle LVDS with 1600x900 panel
in 18bpp dual-channel mode.
Cc: Stable Team <stable@kernel.org>
Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
Signed-off-by: Eric Anholt <eric@anholt.net>
Zhenyu Wangauthored and Eric Anholtcommited 2009-10-13 10:57:10 -07:00
Until we figure out the right setting for powersave features on
Ironlake, disable it for now. Also disable watermark update,
which has new registers for it on Ironlake too.
Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org>
[anholt: Resolved against the Pineview FBC changes]
Signed-off-by: Eric Anholt <eric@anholt.net>
Zhenyu Wangauthored and Eric Anholtcommited 2009-10-13 10:56:57 -07:00
If the device didn't support EDP, we would bail out too soon.
Signed-off-by: Andy Lutomirski <luto@mit.edu>
[anholt: Pulled this patch out of the patch for adding quirks to
enable reclocking.]
Signed-off-by: Eric Anholt <eric@anholt.net>
Andy Lutomirskiauthored and Eric Anholtcommited 2009-10-13 10:41:58 -07:00
This hasn't fixed the regressions we were testing against, but clearly
should be required.
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Eric Anholt <eric@anholt.net>
Jesse Barnesauthored and Eric Anholtcommited 2009-10-13 10:36:20 -07:00
According to the spec the LVDS_BORDER_ENABLE bit decides whether the border
data should be included in the active display and data sent to the panel.
Border should be used when in VGA centered (un-scaled) mode or when scaling
a 4:3 source image to a wide screen panel (typical 16:9).
So when the LVDS scaling is used, decide whether the LVDS_BORDER should be
enabled or not according to the current scaling mode.
At the same time fix the typo error in LVDS center scaling mode.
https://bugs.freedesktop.org/show_bug.cgi?id=23789
Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>
tested-by: Zhao Jian <jian.zhao@intel.com>
Signed-off-by: Eric Anholt <eric@anholt.net>
Zhao Yakuiauthored and Eric Anholtcommited 2009-10-13 10:13:19 -07:00
Pineview doesn't have this FBC mechanism, so this code doesn't apply.
Signed-off-by: Shaohua Li <shaohua.li@intel.com>
Signed-off-by: Eric Anholt <eric@anholt.net>
Shaohua Liauthored and Eric Anholtcommited 2009-10-13 10:09:26 -07:00
* 'drm-intel-next' of git://git.kernel.org/pub/scm/linux/kernel/git/anholt/drm-intel:
drm/i915: Initialize HDMI outputs as HDMI connectors, not DVI.
drm/i915: Multiply the refresh by 1000 in TV mode validatiion
drm/i915: Enable irq to trace batch buffer completion.
drm/i915: batch submit seqno off-by-one.
drm/i915: Record device minor rather than pointer in TRACE_EVENT
drm/i915: Don't call intel_update_fbc from intel_crtc_cursor_set
conflict in radeon since new init path merged with vga arb code.
Conflicts:
drivers/gpu/drm/radeon/radeon.h
drivers/gpu/drm/radeon/radeon_asic.h
drivers/gpu/drm/radeon/radeon_device.c
There is no need to assign vb before you know that space is available.
[agd5f: adapted for kernel tree.]
Signed-off-by: Alex Deucher <alexdeucher@gmail.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Robert Nolandauthored and Dave Airliecommited 2009-10-08 09:56:27 +10:00
For AGP to work unmapped access must cover VRAM & AGP as
AGP is treated like VRAM by the GPU (ie physical address).
This patch properly setup the virtual memory system aperture
to cover AGP if AGP is enabled. It seems that there is memory
corruption after resume when using AGP (RV770 seems unaffected
thought). Version 2 just fix merge issue with updated AGP
fallback patch.
Signed-off-by: Jerome Glisse <jglisse@redhat.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Jerome Glisseauthored and Dave Airliecommited 2009-10-08 09:40:04 +10:00
When GPU acceleration is not working with AGP try to fallback to non
AGP GART (either PCI or PCIE GART). This should make KMS failure on
AGP less painfull. We still need to find out what is wrong when AGP
fails but at least user have a lot of more chances to get a working
configuration with acceleration. This patch also cleanup R600/RV770
fallback path so they use same code as others asics. Version 2
factorize agp disabling logic to avoid code duplication and bugs.
Signed-off-by: Jerome Glisse <jglisse@redhat.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Jerome Glisseauthored and Dave Airliecommited 2009-10-08 09:40:04 +10:00
Bad generated header file leaded to use wrong register
to check IRQ status and acknowledge them. Fix the header
and use proper registers.
Signed-off-by: Jerome Glisse <jglisse@redhat.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Jerome Glisseauthored and Dave Airliecommited 2009-10-08 09:40:04 +10:00
the global refcount wasn't being increased after the first reference.
this caused an oops on unload on a multi-gpu card.
Signed-off-by: Dave Airlie <airlied@redhat.com>
The previous patches had some unwanted side effects, I've fixed
the lack of 32bpp working, and fixed up 16bpp so it should also work.
this also adds the interface to allow the driver to set a preferred
console depth so for example low memory rn50 can set it to 8bpp.
It also catches 24bpp on cards that can't do it and forces 32bpp.
Tested on r100/r600/i945.
Signed-off-by: Dave Airlie <airlied@redhat.com>
This adds support for the setcmap api and fixes the 8bpp
support at least on radeon hardware. It adds a new load_lut
hook which can be called once the color map is setup.
Signed-off-by: Dave Airlie <airlied@redhat.com>
Also add single crtc for RN50 chips.
changes in v2:
fix vblank init to respect single crtc flag
fix r100 mode bandwidth to respect single crtc flag
Signed-off-by: Dave Airlie <airlied@redhat.com>
We can get the corresponding info by adding the boot option of "drm.debug=
0x07". But On some boxes it will print the following message many times in
course of moving mouse. In such case the useful DRM debug info will be flushed.
>[drm:drm_mode_cursor_ioctl],
Avoid using the DRM_DEBUG_KMS in drm_mode_cursor_ioctl.
Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Zhao Yakuiauthored and Dave Airliecommited 2009-10-05 10:00:57 +10:00
"Surround View" is an option in the system bios that
enables the AMD IGP chip in conjunction with a
discrete AMD card. However, since the IGP vbios is
part of the system bios it is not accessible via the
rom bar or the legacy vga location. When "Surround View"
is enabled in the system bios, the system bios puts a
copy of the IGP vbios image at the start of vram.
This patch adds support for reading the vbios image out
of vram on IGP cards.
Signed-off-by: Alex Deucher <alexdeucher@gmail.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Alex Deucherauthored and Dave Airliecommited 2009-10-05 10:00:56 +10:00
Even if the physical output connector is DVI, calling it HDMI
tells the user that there's HDMI audio signaling support.
Signed-off-by: Adam Jackson <ajax@redhat.com>
Signed-off-by: Eric Anholt <eric@anholt.net>
Adam Jacksonauthored and Eric Anholtcommited 2009-10-02 14:53:42 -07:00
As of 559ee21d26 the actual refresh rate
is returned by the function of drm_mode_vrefresh, so multiply the refresh
rate by 1000 in TV mode validation.
At the same time the error is expanded from 10 to 1000.
Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>
Signed-off-by: Eric Anholt <eric@anholt.net>
Zhao Yakuiauthored and Eric Anholtcommited 2009-10-02 12:12:31 -07:00
Avivo hw have vblank interrupt in different place, fixes
irq handling (especialy irq disabling while suspending or
shuting down the module).
Signed-off-by: Jerome Glisse <jglisse@redhat.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Jerome Glisseauthored and Dave Airliecommited 2009-10-02 09:39:23 +10:00
R600 & RV770 family are all using atombios so remove dead code and
print an error message if we fail to find a valid atombios.
Signed-off-by: Jerome Glisse <jglisse@redhat.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Jerome Glisseauthored and Dave Airliecommited 2009-10-02 09:34:14 +10:00
When acceleration doesn't work we should free associated memory
and stop GPU block responsible for hardware acceleration so we
don't waste resource or let think one component of the driver that
a GPU feature is working/running while it doesn't actualy work.
Signed-off-by: Jerome Glisse <jglisse@redhat.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Jerome Glisseauthored and Dave Airliecommited 2009-10-02 09:34:09 +10:00
We were calling reset unconditionaly in the startup path
this is bad we need to call GPU reset for a good reason
as after reset the GPU is in unknown states. To avoid any
more bad things to happen we now also unconditionaly
reinitialize the GPU after reset. This patch fix few issues
reported by different people regarding KMS & R6XX/RV7XX hw.
Signed-off-by: Jerome Glisse <jglisse@redhat.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Jerome Glisseauthored and Dave Airliecommited 2009-10-02 09:34:03 +10:00
This split write back buffer handling into 3 functions,
wb_fini for cleanup, wb_enable/wb_disable for enabling/disabling
write back used for suspend/resume. This should fix
potential issue of letting the write back active before
suspending. We need to allocate memory in wb_enable because
we can only allocate once GART is running.
Signed-off-by: Jerome Glisse <jglisse@redhat.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Jerome Glisseauthored and Dave Airliecommited 2009-10-02 09:33:52 +10:00
This remove old init path and allow code cleanup, now all hw
use the new init path, see top of radeon.h for description of
this.
Signed-off-by: Jerome Glisse <jglisse@redhat.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Jerome Glisseauthored and Dave Airliecommited 2009-10-02 09:33:46 +10:00
New init path allow to simply asic initialization and make easier
to trace what happen on each different asic. We are removing most
callback. Do a massive RS600 register cleanup to clarify RS600
register, we are still bit fuzy on some register and waiting for
more informations. I don't have hw to test, so this patch is a
best effort to not break anythings and to try to improve things.
Signed-off-by: Jerome Glisse <jglisse@redhat.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Jerome Glisseauthored and Dave Airliecommited 2009-10-02 09:25:50 +10:00
Daniel Vetter
authored and
Eric Anholt
commited 
Jesse Barnes
authored and
Zhenyu Wang
authored and
Chris Wilson
authored and
Linus Torvalds
commited 
Dave Airlie
commited 
Zhao Yakui
authored and
Andy Lutomirski
authored and
Shaohua Li
authored and
Robert Noland
authored and
Jerome Glisse
authored and
Roel Kluin
authored and
Dave Airlie
commited 
Alex Deucher
authored and
Adam Jackson
authored and