Message	SHA1
MIPS: Don't clobber CP0_STATUS value for CONFIG_MIPS_MT_SMTC ... Reported-by: Edgar E. Iglesias <edgar.iglesias@gmail.com> Signed-off-by: David Daney <david.daney@cavium.com> Patchwork: https://patchwork.linux-mips.org/patch/2753/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org> David Daney   authored and   Ralf Baechle   commited 2011-09-21 17:54:02 +02:00	d968275921
Fix common misspellings ... Fixes generated by 'codespell' and manually reviewed. Signed-off-by: Lucas De Marchi <lucas.demarchi@profusion.mobi> Lucas De Marchi   commited 2011-03-31 11:26:23 -03:00	25985edced
MIPS: Loongson-2F: Use CONFIG_CPU_JUMP_WORKAROUNDS to control workarounds. ... Signed-off-by: Wu Zhangjin <wuzhangjin@gmail.com> Cc: linux-mips <linux-mips@linux-mips.org> Patchwork: http://patchwork.linux-mips.org/patch/1106/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org> Wu Zhangjin   authored and   Ralf Baechle   commited 2010-04-30 20:52:58 +01:00	b197b62866
MIPS: Loongson-2F: Flush the branch target history in BTB and RAS ... As per chapter 15 "Errata: Issue of Out-of-order in loongson"[1] to work around the Loongson 2F erratum we need to do: "When switching from user mode to kernel mode, you should flush the branch target history such as BTB and RAS." [1] Chinese version: http://www.loongson.cn/uploadfile/file/200808211 [2] English version of chapter 15: http://groups.google.com.hk/group/loongson-dev/msg/e0d2e220958f10a6?dmode=source Signed-off-by: Wu Zhangjin <wuzhangjin@gmail.com> Cc: linux-mips@linux-mips.org Cc: Shinya Kuribayashi <shinya.kuribayashi@necel.com> Patchwork: http://patchwork.linux-mips.org/patch/1066/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org> Wu Zhangjin   authored and   Ralf Baechle   commited 2010-04-12 17:26:15 +01:00	f1df323924
MIPS: Put PGD in C0_CONTEXT for 64-bit R2 processors. ... Processors that support the mips64r2 ISA can in four instructions convert a shifted PGD pointer stored in the upper bits of c0_context into a usable pointer. By doing this we save a memory load and associated potential cache miss in the TLB exception handlers. Since the upper bits of c0_context were holding the CPU number, we move this to the upper bits of c0_xcontext which doesn't have enough bits to hold the PGD pointer, but has plenty for the CPU number. Signed-off-by: David Daney <ddaney@caviumnetworks.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org> David Daney   authored and   Ralf Baechle   commited 2009-12-17 01:57:01 +00:00	82622284dd
MIPS: Reorder operations in stackframe.h for better scheduling ... Reorder PT ops to avoid pipeline stalls. Signed-off-by: David Daney <ddaney@caviumnetworks.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org> David Daney   authored and   Ralf Baechle   commited 2009-12-17 01:56:57 +00:00	362e696428
MIPS: Cavium OCTEON multiplier state preservation. ... For OCTEON, implement a save and restore of the multiplier state across context switches. Signed-off-by: Tomaso Paoletti <tpaoletti@caviumnetworks.com> Signed-off-by: David Daney <ddaney@caviumnetworks.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org> David Daney   authored and   Ralf Baechle   commited 2009-01-11 09:57:24 +00:00	2a219b0eaa
MIPS: Move headfiles to new location below arch/mips/include ... Signed-off-by: Ralf Baechle <ralf@linux-mips.org> Ralf Baechle   commited 2008-10-11 16:18:52 +01:00	384740dc49

Renamed from include/asm-mips/stackframe.h (Browse further)