Message	SHA1
x86, mce, cmci: define MSR names and fields for new CMCI registers ... Impact: New register definitions only CMCI means support for raising an interrupt on a corrected machine check event instead of having to poll for it. It's a new feature in Intel Nehalem CPUs available on some machine check banks. For details see the IA32 SDM Vol3a 14.5 Define the registers for it as a preparation for further patches. Signed-off-by: Andi Kleen <ak@linux.intel.com> Signed-off-by: H. Peter Anvin <hpa@zytor.com> Andi Kleen   authored and   H. Peter Anvin   commited 2009-02-24 13:41:00 -08:00	03195c6b40
x86: Fix ASM_X86__ header guards ... Change header guards named "ASM_X86__*" to "_ASM_X86_*" since: a. the double underscore is ugly and pointless. b. no leading underscore violates namespace constraints. Signed-off-by: H. Peter Anvin <hpa@zytor.com> H. Peter Anvin   commited 2008-10-22 22:55:23 -07:00	1965aae3c9
x86, um: ... and asm-x86 move ... Signed-off-by: Al Viro <viro@zeniv.linux.org.uk> Signed-off-by: H. Peter Anvin <hpa@zytor.com> Al Viro   authored and   H. Peter Anvin   commited 2008-10-22 22:55:20 -07:00	bb8985586b

Renamed from include/asm-x86/apicdef.h (Browse further)