Message	SHA1
[XTENSA] Add support for cache-aliasing ... Add support for processors that have cache-aliasing issues, such as the Stretch S5000 processor. Cache-aliasing means that the size of the cache (for one way) is larger than the page size, thus, a page can end up in several places in cache depending on the virtual to physical translation. The method used here is to map a user page temporarily through the auto-refill way 0 and of of the DTLB. We probably will want to revisit this issue and use a better approach with kmap/kunmap. Signed-off-by: Chris Zankel <chris@zankel.net> Chris Zankel   commited 2007-08-27 13:54:16 -07:00	6656920b0b
Don't include linux/config.h from anywhere else in include/ ... Signed-off-by: David Woodhouse <dwmw2@infradead.org> David Woodhouse   commited 2006-04-26 12:56:16 +01:00	62c4f0a2d5
[PATCH] xtensa: Architecture support for Tensilica Xtensa Part 6 ... The attached patches provides part 6 of an architecture implementation for the Tensilica Xtensa CPU series. Signed-off-by: Chris Zankel <chris@zankel.net> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org> Chris Zankel   authored and   Linus Torvalds   commited 2005-06-24 00:05:22 -07:00	9a8fd55899