Message	SHA1
[POWERPC] Support setting affinity for U3/U4 MSI sources ... Hook up affinity-setting for U3/U4 MSI interrupt sources. Tested on Quad G5 with myri10ge. Signed-off-by: Olof Johansson <olof@lixom.net> Acked-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Acked-by: Michael Ellerman <michael@ellerman.id.au> Signed-off-by: Paul Mackerras <paulus@samba.org> Olof Johansson   authored and   Paul Mackerras   commited 2007-09-22 14:49:22 +10:00	17b5ee04c0
[POWERPC] MPIC U3/U4 MSI backend ... MPIC U3/U4 MSI backend. Based on code from Segher, heavily hacked by me. This only deals with MSI on U3/U4 MPICs, aka. CPC 9x5. If we find a U3/U4 then we enable this backend, ie. take over the ppc_md MSI hooks. We might need more elaborate logic in future to decide which backend is enabled. We need our own irq_chip so that we can do MSI masking/unmasking on the device itself. We also need to mask explicitly on shutdown to make sure we don't get bitten by lazy-disable semantics. Signed-off-by: Michael Ellerman <michael@ellerman.id.au> Signed-off-by: Paul Mackerras <paulus@samba.org> Michael Ellerman   authored and   Paul Mackerras   commited 2007-05-08 13:46:48 +10:00	05af7bd2d7
[POWERPC] MPIC MSI allocator ... To support MSI on MPIC we need a way to reserve and allocate hardware irq numbers, this patch implements an allocator for that purpose. New firmware platforms must define a "msi-available-ranges" property on their MPIC node for MSI to work. For U3/U4 we do a best-guess setup. Signed-off-by: Michael Ellerman <michael@ellerman.id.au> Signed-off-by: Paul Mackerras <paulus@samba.org> Michael Ellerman   authored and   Paul Mackerras   commited 2007-05-08 13:43:48 +10:00	a7de7c7422