The GPIO pins select which sub bus is connected to the master.
Initially tested with an sn74cbtlv3253 switch device wired into the
MDIO bus.
Signed-off-by: David Daney <david.daney@cavium.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
David Daneyauthored and David S. Millercommited 2012-05-07 22:58:09 -04:00
This patch adds a somewhat generic framework for MDIO bus
multiplexers. It is modeled on the I2C multiplexer.
The multiplexer is needed if there are multiple PHYs with the same
address connected to the same MDIO bus adepter, or if there is
insufficient electrical drive capability for all the connected PHY
devices.
Conceptually it could look something like this:
------------------
| Control Signal |
--------+---------
|
--------------- --------+------
| MDIO MASTER |---| Multiplexer |
--------------- --+-------+----
| |
C C
h h
i i
l l
d d
| |
--------- A B ---------
| | | | | |
| PHY@1 +-------+ +---+ PHY@1 |
| | | | | |
--------- | | ---------
--------- | | ---------
| | | | | |
| PHY@2 +-------+ +---+ PHY@2 |
| | | |
--------- ---------
This framework configures the bus topology from device tree data. The
mechanics of switching the multiplexer is left to device specific
drivers.
The follow-on patch contains a multiplexer driven by GPIO lines.
Signed-off-by: David Daney <david.daney@cavium.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
David Daneyauthored and David S. Millercommited 2012-05-07 22:58:09 -04:00
Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
Signed-off-by: Frederic Lambert <frdrc66@gmail.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Frederic LAMBERTauthored and David S. Millercommited 2011-12-19 16:30:40 -05:00
This patch adds support for the PTP clock found on the DP83640.
The basic clock operations and one external time stamp have
been implemented.
Signed-off-by: Richard Cochran <richard.cochran@omicron.at>
Signed-off-by: John Stultz <john.stultz@linaro.org>
Richard Cochranauthored and John Stultzcommited 2011-05-23 13:10:23 -07:00
This is the first version of phy driver from Micrel Inc.
Signed-off-by: David J. Choi <david.choi@micrel.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
David J. Choiauthored and David S. Millercommited 2010-05-03 15:43:26 -07:00
The Octeon SOC has two types of Ethernet ports, each type with its own
driver. However, the PHYs for all the ports are controlled by a
common MDIO bus. Because the mdio driver is not associated with a
particular driver, but is instead a system level resource, we create s
stand-alone driver for it.
As for the driver, we put the register definitions in
arch/mips/include/asm/octeon where most of the other Octeon register
definitions live. This is a platform driver with the platform device
for "mdio-octeon" being registered in the platform startup code.
Signed-off-by: David Daney <ddaney@caviumnetworks.com>
Acked-by: David S. Miller <davem@davemloft.net>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
David Daneyauthored and Ralf Baechlecommited 2009-12-17 01:56:58 +00:00
Adds LSI ET1011C PHY driver.
This driver is used by TI DM646x EVM.
Signed-off-by: Chaithrika U S <chaithrika@ti.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Chaithrika U Sauthored and David S. Millercommited 2008-12-09 22:21:25 -08:00
This patch adds the STMicroelectronics ste10xp PHY device driver.
It supports both the ste100p and the ste101p devices.
Suspend/resume alredy added.
Signed-off-by: Giuseppe Cavallaro <peppe.cavallaro@st.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Giuseppe Cavallaroauthored and David S. Millercommited 2008-11-28 16:42:41 -08:00
This patch adds the PHY device driver for the National Semiconductor
DP83865 Gig PHYTER.
Signed-off-by: Giuseppe Cavallaro <peppe.cavallaro@st.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Giuseppe Cavallaroauthored and David S. Millercommited 2008-11-28 16:14:12 -08:00
This patch adds an MDIO bitbang driver that uses the GPIO library and its
OF bindings to access the bus I/Os.
Signed-off-by: Laurent Pinchart <laurentp@cse-semaphore.com>
Signed-off-by: Jeff Garzik <jgarzik@redhat.com>
Laurent Pinchartauthored and Jeff Garzikcommited 2008-05-30 22:18:25 -04:00
this PHY present on the MPC8315E and MPC837xE RDB boards.
Signed-off-by: Johnson Leung <r58129@freescale.com>
Signed-off-by: Kevin Lam <r43770@freescale.com>
Signed-off-by: Joe D'Abbraccio <ljd015@freescale.com>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
Signed-off-by: Jeff Garzik <jeff@garzik.org>
Signed-off-by: David S. Miller <davem@davemloft.net>
Johnson Leungauthored and David S. Millercommited 2008-02-03 04:28:42 -08:00
Previously, bitbanged MDIO was only supported in individual
hardware-specific drivers. This code factors out the higher level
protocol implementation, reducing the hardware-specific portion to
functions setting direction, data, and clock.
Signed-off-by: Scott Wood <scottwood@freescale.com>
Signed-off-by: Jeff Garzik <jeff@garzik.org>
Scott Woodauthored and David S. Millercommited 2007-10-10 16:54:03 -07:00
The ICPlus IP175C sports a 100Mbit/s 4-port switch in addition
to a dedicated 100Mbit/s WAN port.
Signed-off-by: Michael Barkowski <michael.barkowski@freescale.com>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
Signed-off-by: Jeff Garzik <jeff@garzik.org>
Michael Barkowskiauthored and Jeff Garzikcommited 2007-07-08 22:16:38 -04:00
This patch adds support for interrupt-driven operation of the Broadcom
Gigabit Ethernet PHYs. I have included device IDs for the parts used on
Broadcom SiByte evaluation boards; more can be added as a need arises.
They are apparently generally software-compatible with one another.
Signed-off-by: Maciej W. Rozycki <macro@linux-mips.org>
patch-mips-2.6.18-20060920-broadcom-phy-15
Signed-off-by: Jeff Garzik <jeff@garzik.org>
Maciej W. Rozyckiauthored and Jeff Garzikcommited 2006-12-02 00:11:54 -05:00
This makes it possible for HW PHY-less boards to utilize PAL goodies. Generic
routines to connect to fixed PHY are provided, as well as ability to specify
software callback that fills up link, speed, etc. information into PHY
descriptor (the latter feature not tested so far).
Signed-off-by: Vitaly Bordug <vbordug@ru.mvista.com>
Signed-off-by: Andrew Morton <akpm@osdl.org>
Signed-off-by: Jeff Garzik <jeff@garzik.org>
Vitaly Bordugauthored and Jeff Garzikcommited 2006-08-19 17:44:31 -04:00
* git://git.kernel.org/pub/scm/linux/kernel/git/paulus/powerpc: (139 commits)
[POWERPC] re-enable OProfile for iSeries, using timer interrupt
[POWERPC] support ibm,extended-*-frequency properties
[POWERPC] Extra sanity check in EEH code
[POWERPC] Dont look for class-code in pci children
[POWERPC] Fix mdelay badness on shared processor partitions
[POWERPC] disable floating point exceptions for init
[POWERPC] Unify ppc syscall tables
[POWERPC] mpic: add support for serial mode interrupts
[POWERPC] pseries: Print PCI slot location code on failure
[POWERPC] spufs: one more fix for 64k pages
[POWERPC] spufs: fail spu_create with invalid flags
[POWERPC] spufs: clear class2 interrupt status before wakeup
[POWERPC] spufs: fix Makefile for "make clean"
[POWERPC] spufs: remove stop_code from struct spu
[POWERPC] spufs: fix spu irq affinity setting
[POWERPC] spufs: further abstract priv1 register access
[POWERPC] spufs: split the Cell BE support into generic and platform dependant parts
[POWERPC] spufs: dont try to access SPE channel 1 count
[POWERPC] spufs: use kzalloc in create_spu
[POWERPC] spufs: fix initial state of wbox file
...
Manually resolved conflicts in:
drivers/net/phy/Makefile
include/asm-powerpc/spu.h
new SMSC LAN83C185 10BaseT/100BaseTX PHY driver for the PHY subsystem
Signed-off-by: Herbert Valerio Riedel <hvr@gnu.org>
Signed-off-by: Jeff Garzik <jeff@garzik.org>
Herbert Valerio Riedelauthored and Jeff Garzikcommited 2006-05-24 02:51:33 -04:00
This patch adds back the code that was taken out, thus re-enabling:
* The PHY Layer to initialize without crashing
* Drivers to actually connect to PHYs
* The entire PHY Control Layer
This patch is used by the gianfar driver, and other drivers which are in
development.
Signed-off-by: Andy Fleming <afleming@freescale.com>
Signed-off-by: Jeff Garzik <jgarzik@pobox.com>
Andy Flemingauthored and Jeff Garzikcommited 2005-08-28 20:28:25 -04:00
ethernet drivers to remain as ignorant as is reasonable of the connected
PHY's design and operation details.
Signed-off-by: Andy Fleming <afleming@freescale.com>
Signed-off-by: Jeff Garzik <jgarzik@pobox.com>
Andy Flemingauthored and Jeff Garzikcommited 2005-07-30 19:31:23 -04:00
David Daney
authored and
David S. Miller
commited 
Heiko Schocher
authored and
Frederic LAMBERT
authored and
Richard Cochran
authored and
John Stultz
commited 
David J. Choi
authored and
David Daney
authored and
Ralf Baechle
commited 
Maxime Bizon
authored and
Chaithrika U S
authored and
Giuseppe Cavallaro
authored and
Paulius Zaleckas
authored and
Laurent Pinchart
authored and
Jeff Garzik
commited 
Johnson Leung
authored and
Scott Wood
authored and
David S. Miller
commited 
Michael Barkowski
authored and
Jeff Garzik
commited 
Maciej W. Rozycki
authored and
Vitaly Bordug
authored and
Linus Torvalds
commited 
Jon Loeliger
authored and
Paul Mackerras
commited 
Herbert Valerio Riedel
authored and
Andy Fleming
authored and
Jeff Garzik
commited