This patch adds SPEAr1310 and SPEAr1340's clock framework support. It is based
on earlier support for SPEAr3xx family.
Signed-off-by: Viresh Kumar <viresh.kumar@st.com>
Reviewed-by: Mike Turquette <mturquette@ti.com>
Viresh Kumarauthored and Arnd Bergmanncommited 2012-05-14 17:34:05 +02:00
SPEAr SoCs used its own clock framework since now. From now on they will move to
use common clock framework.
This patch updates existing SPEAr machine support to adapt for common clock
framework.
Signed-off-by: Viresh Kumar <viresh.kumar@st.com>
Reviewed-by: Mike Turquette <mturquette@linaro.org>
Acked-by: Arnd Bergmann <arnd@arndb.de>
Viresh Kumarauthored and Arnd Bergmanncommited 2012-05-12 21:44:12 +02:00
All SPEAr SoC's contain GPT Synthesizers. Their Fout is derived from
following equations:
Fout= Fin/((2 ^ (N+1)) * (M+1))
This patch adds in support for this type of clock.
Signed-off-by: Viresh Kumar <viresh.kumar@st.com>
Reviewed-by: Mike Turquette <mturquette@linaro.org>
Viresh Kumarauthored and Arnd Bergmanncommited 2012-05-12 21:19:27 +02:00
All SPEAr SoC's contain Fractional Synthesizers. Their Fout is derived from
following equations:
Fout = Fin / (2 * div) (division factor)
div is 17 bits:-
0-13 (fractional part)
14-16 (integer part)
div is (16-14 bits).(13-0 bits) (in binary)
Fout = Fin/(2 * div)
Fout = ((Fin / 10000)/(2 * div)) * 10000
Fout = (2^14 * (Fin / 10000)/(2^14 * (2 * div))) * 10000
Fout = (((Fin / 10000) << 14)/(2 * (div << 14))) * 10000
div << 14 is simply 17 bit value written at register.
This patch adds in support for this type of clock.
Signed-off-by: Viresh Kumar <viresh.kumar@st.com>
Reviewed-by: Mike Turquette <mturquette@linaro.org>
Viresh Kumarauthored and Arnd Bergmanncommited 2012-05-12 21:19:27 +02:00
All SPEAr SoC's contain Auxiliary Synthesizers. Their Fout is derived based on
values of eq, x and y.
Fout from synthesizer can be given from two equations:
Fout1 = (Fin * X/Y)/2 EQ1
Fout2 = Fin * X/Y EQ2
This patch adds in support for this type of clock.
Signed-off-by: Viresh Kumar <viresh.kumar@st.com>
Reviewed-by: Mike Turquette <mturquette@linaro.org>
Viresh Kumarauthored and Arnd Bergmanncommited 2012-05-12 21:19:26 +02:00
All SPEAr SoC's contain PLLs. Their Fout is derived based on following equations
- In normal mode
vco = (2 * M[15:8] * Fin)/N
- In Dithered mode
vco = (2 * M[15:0] * Fin)/(256 * N)
pll_rate = vco/2^p
vco and pll are very closely bound to each other,
"vco needs to program: mode, m & n" and "pll needs to program p",
both share common enable/disable logic and registers.
This patch adds in support for this type of clock.
Signed-off-by: Viresh Kumar <viresh.kumar@st.com>
Reviewed-by: Mike Turquette <mturquette@linaro.org>
Viresh Kumarauthored and Arnd Bergmanncommited 2012-05-12 21:19:23 +02:00
Viresh Kumar
authored and
Arnd Bergmann
commited