Message	SHA1
[POWERPC] 4xx: Add PPC4xx L2-cache support (440GX) ... This patch adds support for the 256k L2 cache found on some IBM/AMCC 4xx PPC's. It introduces a common 4xx SoC file (sysdev/ppc4xx_soc.c) which currently "only" adds the L2 cache init code. Other common 4xx stuff can be added later here. The L2 cache handling code is a copy of Eugene's code in arch/ppc with small modifications. Tested on AMCC Taishan 440GX. Signed-off-by: Stefan Roese <sr@denx.de> Signed-off-by: Josh Boyer <jwboyer@linux.vnet.ibm.com> Stefan Roese   authored and   Josh Boyer   commited 2008-03-26 07:27:54 -05:00	2a7069190e
[POWERPC] 4xx: Improve support for 4xx indirect DCRs ... Accessing indirect DCRs is done via a pair of address/data DCRs. Such accesses are thus inherently racy, vs. interrupts, preemption and possibly SMP if 4xx SMP cores are ever used. This updates the mfdcri/mtdcri macros in dcr-native.h (which were so far unused) to use a spinlock. In addition, add some common definitions to a new dcr-regs.h file. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Josh Boyer <jwboyer@linux.vnet.ibm.com> Benjamin Herrenschmidt   authored and   Josh Boyer   commited 2007-12-23 13:12:11 -06:00	0e6140a56f