Commit graph android_kernel_sony_sdm845/include/asm-mips/hazards.h
Message SHA1
[MIPS] R1: Fix hazard barriers to make kernels work on R2 also.
Tested with Malta; inflates malta_defconfig by 3932 bytes.  Ideally there
should be additional configuration to allow getting rid of this overhead
but that would be too much complexity at this stage of the release cycle.

Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

Ralf Baechle   commited 2007-10-11 23:46:19 +01:00
572afc248c
[MIPS] checkfiles: Fix "need space after that ','" errors.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

Ralf Baechle   commited 2007-10-11 23:46:15 +01:00
21a151d8ca
[MIPS] Provide empty irq_enable_hazard definition for legacy and R1 cores.
Following a strict interpretation the empty definition of irq_enable_hazard
has always been a bug - but an intentional one because it didn't bite.
This has now changed, for uniprocessor kernels mm/slab.c:do_drain()

[...]
        on_each_cpu(do_drain, cachep, 1, 1);
        check_irq_on();
[...]

may be compiled into a mtc0 c0_status; mfc0 c0_status sequence resulting
in a back-to-back hazard.

Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

Ralf Baechle   commited 2007-09-10 21:25:28 +01:00
7b0fdaa6a1
[MIPS] Add missing declaration for mips_ihb().
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

Ralf Baechle   commited 2007-07-31 21:35:26 +01:00
98de920a2a
[MIPS] SB1: Build fix.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

Ralf Baechle   commited 2007-05-11 14:28:31 +01:00
a1b53a7b22
[MIPS] FPU hazard handling
Move FPU hazard handling to hazards.h and provide proper support for
MIPSR2 processors

Signed-off-by: Chris Dearman <chris@mips.com>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

Chris Dearman   authored and   Ralf Baechle   commited 2007-05-11 14:28:31 +01:00
0b6249567b
[MIPS] Fix pipeline hazard.
In the the sequence:
        ei
        ..
        mfc0    $x, $status

the mfc0 may not see the SR_IE bit set. This was a deliberate bug in the
kernel code because we knew this was a safe thing to do on all R2 silicon
so far but new silicon is changing this.

Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

Ralf Baechle   commited 2007-03-24 17:01:49 +00:00
7605b39061
[MIPS] vr41xx: need one more nop with mtc0_tlbw_hazard()
NEC VR4111 and VR4121 need one more nop with mtc0_tlbw_hazard().

Signed-off-by: Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

Yoichi Yuasa   authored and   Ralf Baechle   commited 2007-01-24 19:23:21 +00:00
3f3183709f
[MIPS] s/__ASSEMBLER__/__ASSEMBLY__/ for clarity sake.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

Ralf Baechle   commited 2006-09-27 13:37:57 +01:00
36396f3c36
[MIPS] Cleanup hazard handling.
Mostly based on patch by Chris Dearman and cleanups from Yoichi.

Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

Ralf Baechle   commited 2006-09-27 13:37:53 +01:00
d7d86aa88a
[MIPS] Add missing backslashes to macro definitions.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

Ralf Baechle   commited 2006-06-29 21:10:55 +01:00
8db089c6b5
Don't include linux/config.h from anywhere else in include/
Signed-off-by: David Woodhouse <dwmw2@infradead.org>

David Woodhouse   commited 2006-04-26 12:56:16 +01:00
62c4f0a2d5
[MIPS] MT: Improved multithreading support.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

Ralf Baechle   commited 2006-04-19 04:14:28 +02:00
41c594ab65
[MIPS] SB1: Fix interrupt disable hazard.
The SB1 core has a three cycle interrupt disable hazard but we were
wrongly treating it as fully interlocked.
    
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

Ralf Baechle   commited 2006-03-18 16:59:26 +00:00
a3c4946db4
[MIPS] Fix C version of ssnop to use the right opcode.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

Ralf Baechle   commited 2006-02-07 13:30:21 +00:00
05faa7b758
MIPS: R2: Try to bulletproof instruction_hazard against miss-compilation.
Gcc has a tradition of misscompiling the previous construct using the
address of a label as argument to inline assembler.  Gas otoh has the
annoying difference between la and dla which are only usable for 32-bit
rsp. 64-bit code, so can't be used without conditional compilation.
The alterantive is switching the assembler to 64-bit code which happens
to work right even for 32-bit code ...
    
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

Ralf Baechle   authored and     commited 2006-01-10 13:39:08 +00:00
7043ad4f4c
Fixup a few lose ends in explicit support for MIPS R1/R2.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

Ralf Baechle   commited 2005-10-29 19:32:37 +01:00
ec917c2c1a
Use R4000 TLB routines for SB1 also.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

Ralf Baechle   commited 2005-10-29 19:32:31 +01:00
f5cfa980e5
Cleanups.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

Ralf Baechle   commited 2005-10-29 19:31:53 +01:00
86071b637d
MIPS R2 instruction hazard handling.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

Ralf Baechle   commited 2005-10-29 19:31:46 +01:00
cc61c1fede
One definition of back_to_back_c0_hazard too much.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

Ralf Baechle   commited 2005-10-29 19:30:50 +01:00
88d535b6b5
New hazard handling function back_to_back_c0_hazard() to handle back to
back mtc0 / mfc0 pairs from the same coprocessor register.

Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

Ralf Baechle   commited 2005-10-29 19:30:49 +01:00
5068debff2
Linux-2.6.12-rc2
Initial git repository build. I'm not bothering with the full history,
even though we have it. We can create a separate "historical" git
archive of that later if we want to, and in the meantime it's about
3.2GB when imported into git - space that would just make the early
git days unnecessarily complicated, when we don't have a lot of good
infrastructure for it.

Let it rip!

Linus Torvalds   commited 2005-04-16 15:20:36 -07:00
1da177e4c3