Commit graph android_kernel_sony_sdm845/include/asm-mips/barrier.h
Message SHA1
[MIPS] Make support for weakly ordered LL/SC a config option.
None of weakly ordered processor supported in tree need this but it seems
like this could change ...

Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

Ralf Baechle   commited 2007-07-20 18:57:39 +01:00
17099b1142
[MIPS] Cleanup memory barriers for weakly ordered systems.
Also the R4000 / R4600 LL/SC instructions imply a sync so no explicit sync
needed.

Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

Ralf Baechle   commited 2006-12-04 22:43:14 +00:00
0004a9dfea