This is the 4.9.67 stable release
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This commit is contained in:
Greg Kroah-Hartman
commit
f87ffb2f71
41 changed files with 249 additions and 121 deletions
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@ -34,6 +34,10 @@ Required properties:
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- reg: I2C address
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Optional properties:
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- smbus-timeout-disable: When set, the smbus timeout function will be disabled.
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This is not supported on all chips.
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Example:
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temp-sensor@1a {
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2
Makefile
2
Makefile
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@ -1,6 +1,6 @@
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VERSION = 4
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PATCHLEVEL = 9
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SUBLEVEL = 66
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SUBLEVEL = 67
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EXTRAVERSION =
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NAME = Roaring Lionus
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@ -192,7 +192,7 @@
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interrupts-extended = <&intc 83 &omap3_pmx_core 0x11a>;
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pinctrl-names = "default";
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pinctrl-0 = <&mmc1_pins &mmc1_cd>;
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cd-gpios = <&gpio4 31 IRQ_TYPE_LEVEL_LOW>; /* gpio127 */
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cd-gpios = <&gpio4 31 GPIO_ACTIVE_LOW>; /* gpio127 */
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vmmc-supply = <&vmmc1>;
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bus-width = <4>;
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cap-power-off-card;
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@ -249,9 +249,9 @@
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OMAP3_CORE1_IOPAD(0x2110, PIN_INPUT | MUX_MODE0) /* cam_xclka.cam_xclka */
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OMAP3_CORE1_IOPAD(0x2112, PIN_INPUT | MUX_MODE0) /* cam_pclk.cam_pclk */
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OMAP3_CORE1_IOPAD(0x2114, PIN_INPUT | MUX_MODE0) /* cam_d0.cam_d0 */
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OMAP3_CORE1_IOPAD(0x2116, PIN_INPUT | MUX_MODE0) /* cam_d1.cam_d1 */
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OMAP3_CORE1_IOPAD(0x2118, PIN_INPUT | MUX_MODE0) /* cam_d2.cam_d2 */
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OMAP3_CORE1_IOPAD(0x2116, PIN_INPUT | MUX_MODE0) /* cam_d0.cam_d0 */
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OMAP3_CORE1_IOPAD(0x2118, PIN_INPUT | MUX_MODE0) /* cam_d1.cam_d1 */
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OMAP3_CORE1_IOPAD(0x211a, PIN_INPUT | MUX_MODE0) /* cam_d2.cam_d2 */
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OMAP3_CORE1_IOPAD(0x211c, PIN_INPUT | MUX_MODE0) /* cam_d3.cam_d3 */
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OMAP3_CORE1_IOPAD(0x211e, PIN_INPUT | MUX_MODE0) /* cam_d4.cam_d4 */
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OMAP3_CORE1_IOPAD(0x2120, PIN_INPUT | MUX_MODE0) /* cam_d5.cam_d5 */
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@ -162,7 +162,7 @@ static struct ti_st_plat_data wilink7_pdata = {
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.nshutdown_gpio = 162,
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.dev_name = "/dev/ttyO1",
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.flow_cntrl = 1,
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.baud_rate = 300000,
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.baud_rate = 3000000,
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};
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static struct platform_device wl128x_device = {
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@ -54,19 +54,15 @@ ENTRY(native_usergs_sysret64)
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ENDPROC(native_usergs_sysret64)
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#endif /* CONFIG_PARAVIRT */
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.macro TRACE_IRQS_FLAGS flags:req
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.macro TRACE_IRQS_IRETQ
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#ifdef CONFIG_TRACE_IRQFLAGS
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bt $9, \flags /* interrupts off? */
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bt $9, EFLAGS(%rsp) /* interrupts off? */
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jnc 1f
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TRACE_IRQS_ON
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1:
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#endif
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.endm
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.macro TRACE_IRQS_IRETQ
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TRACE_IRQS_FLAGS EFLAGS(%rsp)
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.endm
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/*
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* When dynamic function tracer is enabled it will add a breakpoint
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* to all locations that it is about to modify, sync CPUs, update
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@ -872,13 +868,11 @@ idtentry simd_coprocessor_error do_simd_coprocessor_error has_error_code=0
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ENTRY(native_load_gs_index)
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pushfq
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DISABLE_INTERRUPTS(CLBR_ANY & ~CLBR_RDI)
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TRACE_IRQS_OFF
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SWAPGS
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.Lgs_change:
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movl %edi, %gs
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2: ALTERNATIVE "", "mfence", X86_BUG_SWAPGS_FENCE
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SWAPGS
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TRACE_IRQS_FLAGS (%rsp)
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popfq
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ret
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END(native_load_gs_index)
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@ -246,9 +246,14 @@ static inline void kvm_apic_set_ldr(struct kvm_lapic *apic, u32 id)
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recalculate_apic_map(apic->vcpu->kvm);
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}
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static inline u32 kvm_apic_calc_x2apic_ldr(u32 id)
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{
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return ((id >> 4) << 16) | (1 << (id & 0xf));
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}
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static inline void kvm_apic_set_x2apic_id(struct kvm_lapic *apic, u32 id)
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{
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u32 ldr = ((id >> 4) << 16) | (1 << (id & 0xf));
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u32 ldr = kvm_apic_calc_x2apic_ldr(id);
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kvm_lapic_set_reg(apic, APIC_ID, id);
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kvm_lapic_set_reg(apic, APIC_LDR, ldr);
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@ -2029,6 +2034,7 @@ static int kvm_apic_state_fixup(struct kvm_vcpu *vcpu,
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{
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if (apic_x2apic_mode(vcpu->arch.apic)) {
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u32 *id = (u32 *)(s->regs + APIC_ID);
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u32 *ldr = (u32 *)(s->regs + APIC_LDR);
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if (vcpu->kvm->arch.x2apic_format) {
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if (*id != vcpu->vcpu_id)
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@ -2039,6 +2045,10 @@ static int kvm_apic_state_fixup(struct kvm_vcpu *vcpu,
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else
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*id <<= 24;
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}
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/* In x2APIC mode, the LDR is fixed and based on the id */
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if (set)
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*ldr = kvm_apic_calc_x2apic_ldr(*id);
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}
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return 0;
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@ -2149,6 +2149,8 @@ static int ud_interception(struct vcpu_svm *svm)
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int er;
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er = emulate_instruction(&svm->vcpu, EMULTYPE_TRAP_UD);
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if (er == EMULATE_USER_EXIT)
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return 0;
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if (er != EMULATE_DONE)
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kvm_queue_exception(&svm->vcpu, UD_VECTOR);
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return 1;
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@ -5502,6 +5502,8 @@ static int handle_exception(struct kvm_vcpu *vcpu)
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return 1;
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}
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er = emulate_instruction(vcpu, EMULTYPE_TRAP_UD);
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if (er == EMULATE_USER_EXIT)
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return 0;
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if (er != EMULATE_DONE)
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kvm_queue_exception(vcpu, UD_VECTOR);
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return 1;
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@ -1797,6 +1797,9 @@ static void kvm_setup_pvclock_page(struct kvm_vcpu *v)
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*/
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BUILD_BUG_ON(offsetof(struct pvclock_vcpu_time_info, version) != 0);
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if (guest_hv_clock.version & 1)
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++guest_hv_clock.version; /* first time write, random junk */
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vcpu->hv_clock.version = guest_hv_clock.version + 1;
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kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
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&vcpu->hv_clock,
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@ -5576,6 +5579,8 @@ int x86_emulate_instruction(struct kvm_vcpu *vcpu,
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if (reexecute_instruction(vcpu, cr2, write_fault_to_spt,
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emulation_type))
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return EMULATE_DONE;
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if (ctxt->have_exception && inject_emulated_exception(vcpu))
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return EMULATE_DONE;
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if (emulation_type & EMULTYPE_SKIP)
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return EMULATE_FAIL;
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return handle_emulation_failure(vcpu);
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@ -1788,34 +1788,32 @@ void amdgpu_atombios_scratch_regs_restore(struct amdgpu_device *adev)
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WREG32(mmBIOS_SCRATCH_0 + i, adev->bios_scratch[i]);
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}
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/* Atom needs data in little endian format
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* so swap as appropriate when copying data to
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* or from atom. Note that atom operates on
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* dw units.
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/* Atom needs data in little endian format so swap as appropriate when copying
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* data to or from atom. Note that atom operates on dw units.
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*
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* Use to_le=true when sending data to atom and provide at least
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* ALIGN(num_bytes,4) bytes in the dst buffer.
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*
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* Use to_le=false when receiving data from atom and provide ALIGN(num_bytes,4)
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* byes in the src buffer.
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*/
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void amdgpu_atombios_copy_swap(u8 *dst, u8 *src, u8 num_bytes, bool to_le)
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{
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#ifdef __BIG_ENDIAN
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u8 src_tmp[20], dst_tmp[20]; /* used for byteswapping */
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u32 *dst32, *src32;
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u32 src_tmp[5], dst_tmp[5];
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int i;
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u8 align_num_bytes = ALIGN(num_bytes, 4);
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memcpy(src_tmp, src, num_bytes);
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src32 = (u32 *)src_tmp;
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dst32 = (u32 *)dst_tmp;
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if (to_le) {
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for (i = 0; i < ((num_bytes + 3) / 4); i++)
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dst32[i] = cpu_to_le32(src32[i]);
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memcpy(dst, dst_tmp, num_bytes);
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memcpy(src_tmp, src, num_bytes);
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for (i = 0; i < align_num_bytes / 4; i++)
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dst_tmp[i] = cpu_to_le32(src_tmp[i]);
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memcpy(dst, dst_tmp, align_num_bytes);
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} else {
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u8 dws = num_bytes & ~3;
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for (i = 0; i < ((num_bytes + 3) / 4); i++)
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dst32[i] = le32_to_cpu(src32[i]);
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memcpy(dst, dst_tmp, dws);
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if (num_bytes % 4) {
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for (i = 0; i < (num_bytes % 4); i++)
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dst[dws+i] = dst_tmp[dws+i];
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}
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memcpy(src_tmp, src, align_num_bytes);
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for (i = 0; i < align_num_bytes / 4; i++)
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dst_tmp[i] = le32_to_cpu(src_tmp[i]);
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memcpy(dst, dst_tmp, num_bytes);
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}
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#else
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memcpy(dst, src, num_bytes);
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@ -648,7 +648,7 @@ int amdgpu_vce_ring_parse_cs(struct amdgpu_cs_parser *p, uint32_t ib_idx)
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uint32_t allocated = 0;
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uint32_t tmp, handle = 0;
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uint32_t *size = &tmp;
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int i, r, idx = 0;
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int i, r = 0, idx = 0;
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r = amdgpu_cs_sysvm_access_required(p);
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if (r)
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@ -744,7 +744,7 @@ error_free:
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int amdgpu_vm_update_page_directory(struct amdgpu_device *adev,
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struct amdgpu_vm *vm)
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{
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int r;
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int r = 0;
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r = amdgpu_vm_update_pd_or_shadow(adev, vm, true);
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if (r)
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@ -850,9 +850,9 @@ static int init_over_drive_limits(
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const ATOM_Tonga_POWERPLAYTABLE *powerplay_table)
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{
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hwmgr->platform_descriptor.overdriveLimit.engineClock =
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le16_to_cpu(powerplay_table->ulMaxODEngineClock);
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le32_to_cpu(powerplay_table->ulMaxODEngineClock);
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hwmgr->platform_descriptor.overdriveLimit.memoryClock =
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le16_to_cpu(powerplay_table->ulMaxODMemoryClock);
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le32_to_cpu(powerplay_table->ulMaxODMemoryClock);
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hwmgr->platform_descriptor.minOverdriveVDDC = 0;
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hwmgr->platform_descriptor.maxOverdriveVDDC = 0;
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@ -521,9 +521,12 @@ static void ade_crtc_atomic_begin(struct drm_crtc *crtc,
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{
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struct ade_crtc *acrtc = to_ade_crtc(crtc);
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struct ade_hw_ctx *ctx = acrtc->ctx;
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struct drm_display_mode *mode = &crtc->state->mode;
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struct drm_display_mode *adj_mode = &crtc->state->adjusted_mode;
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if (!ctx->power_on)
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(void)ade_power_up(ctx);
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ade_ldi_set_mode(acrtc, mode, adj_mode);
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}
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static void ade_crtc_atomic_flush(struct drm_crtc *crtc,
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@ -430,7 +430,9 @@ static bool
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gmbus_is_index_read(struct i2c_msg *msgs, int i, int num)
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{
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return (i + 1 < num &&
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!(msgs[i].flags & I2C_M_RD) && msgs[i].len <= 2 &&
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msgs[i].addr == msgs[i + 1].addr &&
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!(msgs[i].flags & I2C_M_RD) &&
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(msgs[i].len == 1 || msgs[i].len == 2) &&
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(msgs[i + 1].flags & I2C_M_RD));
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}
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@ -369,6 +369,7 @@ static int panel_simple_remove(struct device *dev)
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drm_panel_remove(&panel->base);
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panel_simple_disable(&panel->base);
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panel_simple_unprepare(&panel->base);
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if (panel->ddc)
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put_device(&panel->ddc->dev);
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|
|
@ -384,6 +385,7 @@ static void panel_simple_shutdown(struct device *dev)
|
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struct panel_simple *panel = dev_get_drvdata(dev);
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panel_simple_disable(&panel->base);
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panel_simple_unprepare(&panel->base);
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}
|
||||
|
||||
static const struct drm_display_mode ampire_am800480r3tmqwa1h_mode = {
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|
|
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|
|
@ -45,34 +45,32 @@ static char *pre_emph_names[] = {
|
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|
||||
/***** radeon AUX functions *****/
|
||||
|
||||
/* Atom needs data in little endian format
|
||||
* so swap as appropriate when copying data to
|
||||
* or from atom. Note that atom operates on
|
||||
* dw units.
|
||||
/* Atom needs data in little endian format so swap as appropriate when copying
|
||||
* data to or from atom. Note that atom operates on dw units.
|
||||
*
|
||||
* Use to_le=true when sending data to atom and provide at least
|
||||
* ALIGN(num_bytes,4) bytes in the dst buffer.
|
||||
*
|
||||
* Use to_le=false when receiving data from atom and provide ALIGN(num_bytes,4)
|
||||
* byes in the src buffer.
|
||||
*/
|
||||
void radeon_atom_copy_swap(u8 *dst, u8 *src, u8 num_bytes, bool to_le)
|
||||
{
|
||||
#ifdef __BIG_ENDIAN
|
||||
u8 src_tmp[20], dst_tmp[20]; /* used for byteswapping */
|
||||
u32 *dst32, *src32;
|
||||
u32 src_tmp[5], dst_tmp[5];
|
||||
int i;
|
||||
u8 align_num_bytes = ALIGN(num_bytes, 4);
|
||||
|
||||
memcpy(src_tmp, src, num_bytes);
|
||||
src32 = (u32 *)src_tmp;
|
||||
dst32 = (u32 *)dst_tmp;
|
||||
if (to_le) {
|
||||
for (i = 0; i < ((num_bytes + 3) / 4); i++)
|
||||
dst32[i] = cpu_to_le32(src32[i]);
|
||||
memcpy(dst, dst_tmp, num_bytes);
|
||||
memcpy(src_tmp, src, num_bytes);
|
||||
for (i = 0; i < align_num_bytes / 4; i++)
|
||||
dst_tmp[i] = cpu_to_le32(src_tmp[i]);
|
||||
memcpy(dst, dst_tmp, align_num_bytes);
|
||||
} else {
|
||||
u8 dws = num_bytes & ~3;
|
||||
for (i = 0; i < ((num_bytes + 3) / 4); i++)
|
||||
dst32[i] = le32_to_cpu(src32[i]);
|
||||
memcpy(dst, dst_tmp, dws);
|
||||
if (num_bytes % 4) {
|
||||
for (i = 0; i < (num_bytes % 4); i++)
|
||||
dst[dws+i] = dst_tmp[dws+i];
|
||||
}
|
||||
memcpy(src_tmp, src, align_num_bytes);
|
||||
for (i = 0; i < align_num_bytes / 4; i++)
|
||||
dst_tmp[i] = le32_to_cpu(src_tmp[i]);
|
||||
memcpy(dst, dst_tmp, num_bytes);
|
||||
}
|
||||
#else
|
||||
memcpy(dst, src, num_bytes);
|
||||
|
|
|
|||
|
|
@ -252,7 +252,6 @@ static int radeonfb_create(struct drm_fb_helper *helper,
|
|||
}
|
||||
|
||||
info->par = rfbdev;
|
||||
info->skip_vt_switch = true;
|
||||
|
||||
ret = radeon_framebuffer_init(rdev->ddev, &rfbdev->rfb, &mode_cmd, gobj);
|
||||
if (ret) {
|
||||
|
|
|
|||
|
|
@ -473,6 +473,7 @@ static int ttm_buffer_object_transfer(struct ttm_buffer_object *bo,
|
|||
INIT_LIST_HEAD(&fbo->lru);
|
||||
INIT_LIST_HEAD(&fbo->swap);
|
||||
INIT_LIST_HEAD(&fbo->io_reserve_lru);
|
||||
mutex_init(&fbo->wu_mutex);
|
||||
fbo->moving = NULL;
|
||||
drm_vma_node_reset(&fbo->vma_node);
|
||||
atomic_set(&fbo->cpu_writers, 0);
|
||||
|
|
|
|||
|
|
@ -22,6 +22,7 @@
|
|||
* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
|
||||
*/
|
||||
|
||||
#include <linux/bitops.h>
|
||||
#include <linux/module.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/slab.h>
|
||||
|
|
@ -45,6 +46,7 @@ static const unsigned short normal_i2c[] = {
|
|||
#define JC42_REG_TEMP 0x05
|
||||
#define JC42_REG_MANID 0x06
|
||||
#define JC42_REG_DEVICEID 0x07
|
||||
#define JC42_REG_SMBUS 0x22 /* NXP and Atmel, possibly others? */
|
||||
|
||||
/* Status bits in temperature register */
|
||||
#define JC42_ALARM_CRIT_BIT 15
|
||||
|
|
@ -73,6 +75,9 @@ static const unsigned short normal_i2c[] = {
|
|||
#define ONS_MANID 0x1b09 /* ON Semiconductor */
|
||||
#define STM_MANID 0x104a /* ST Microelectronics */
|
||||
|
||||
/* SMBUS register */
|
||||
#define SMBUS_STMOUT BIT(7) /* SMBus time-out, active low */
|
||||
|
||||
/* Supported chips */
|
||||
|
||||
/* Analog Devices */
|
||||
|
|
@ -476,6 +481,22 @@ static int jc42_probe(struct i2c_client *client, const struct i2c_device_id *id)
|
|||
|
||||
data->extended = !!(cap & JC42_CAP_RANGE);
|
||||
|
||||
if (device_property_read_bool(dev, "smbus-timeout-disable")) {
|
||||
int smbus;
|
||||
|
||||
/*
|
||||
* Not all chips support this register, but from a
|
||||
* quick read of various datasheets no chip appears
|
||||
* incompatible with the below attempt to disable
|
||||
* the timeout. And the whole thing is opt-in...
|
||||
*/
|
||||
smbus = i2c_smbus_read_word_swapped(client, JC42_REG_SMBUS);
|
||||
if (smbus < 0)
|
||||
return smbus;
|
||||
i2c_smbus_write_word_swapped(client, JC42_REG_SMBUS,
|
||||
smbus | SMBUS_STMOUT);
|
||||
}
|
||||
|
||||
config = i2c_smbus_read_word_swapped(client, JC42_REG_CONFIG);
|
||||
if (config < 0)
|
||||
return config;
|
||||
|
|
|
|||
Some files were not shown because too many files have changed in this diff Show more
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Reference in a new issue