ARM: remove ixp23xx and ixp2000 platforms
ixp2xxx platforms have had no real changes since ~2006 and the maintainer has said on irc that they can be removed: 13:05 < nico> do you still care about ixp2000? 13:22 < lennert> not really, no 13:58 < nico> do you think we could remove it from the kernel tree? 14:01 < lennert> go for it, and remove ixp23xx too while you're at it Removing will help simplify ARM consolidation in general and PCI re-work specifically. Signed-off-by: Rob Herring <rob.herring@calxeda.com> Cc: Randy Dunlap <rdunlap@xenotime.net> Acked-by: Lennert Buytenhek <buytenh@wantstofly.org>
This commit is contained in:
Rob Herring
parent
dd775ae254
commit
c65f2abf54
55 changed files with 0 additions and 6950 deletions
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@ -4,8 +4,6 @@ Booting
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- requirements for booting
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Interrupts
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- ARM Interrupt subsystem documentation
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IXP2000
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- Release Notes for Linux on Intel's IXP2000 Network Processor
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msm
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- MSM specific documentation
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Netwinder
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@ -1,69 +0,0 @@
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-------------------------------------------------------------------------
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Release Notes for Linux on Intel's IXP2000 Network Processor
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Maintained by Deepak Saxena <dsaxena@plexity.net>
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-------------------------------------------------------------------------
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1. Overview
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Intel's IXP2000 family of NPUs (IXP2400, IXP2800, IXP2850) is designed
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for high-performance network applications such high-availability
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telecom systems. In addition to an XScale core, it contains up to 8
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"MicroEngines" that run special code, several high-end networking
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interfaces (UTOPIA, SPI, etc), a PCI host bridge, one serial port,
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flash interface, and some other odds and ends. For more information, see:
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http://developer.intel.com
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2. Linux Support
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Linux currently supports the following features on the IXP2000 NPUs:
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- On-chip serial
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- PCI
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- Flash (MTD/JFFS2)
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- I2C through GPIO
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- Timers (watchdog, OS)
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That is about all we can support under Linux ATM b/c the core networking
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components of the chip are accessed via Intel's closed source SDK.
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Please contact Intel directly on issues with using those. There is
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also a mailing list run by some folks at Princeton University that might
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be of help: https://lists.cs.princeton.edu/mailman/listinfo/ixp2xxx
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WHATEVER YOU DO, DO NOT POST EMAIL TO THE LINUX-ARM OR LINUX-ARM-KERNEL
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MAILING LISTS REGARDING THE INTEL SDK.
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3. Supported Platforms
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- Intel IXDP2400 Reference Platform
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- Intel IXDP2800 Reference Platform
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- Intel IXDP2401 Reference Platform
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- Intel IXDP2801 Reference Platform
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- RadiSys ENP-2611
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4. Usage Notes
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- The IXP2000 platforms usually have rather complex PCI bus topologies
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with large memory space requirements. In addition, b/c of the way the
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Intel SDK is designed, devices are enumerated in a very specific
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way. B/c of this this, we use "pci=firmware" option in the kernel
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command line so that we do not re-enumerate the bus.
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- IXDP2x01 systems have variable clock tick rates that we cannot determine
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via HW registers. The "ixdp2x01_clk=XXX" cmd line options allow you
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to pass the clock rate to the board port.
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5. Thanks
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The IXP2000 work has been funded by Intel Corp. and MontaVista Software, Inc.
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The following people have contributed patches/comments/etc:
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Naeem F. Afzal
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Lennert Buytenhek
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Jeffrey Daly
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-------------------------------------------------------------------------
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Last Update: 8/09/2004
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17
MAINTAINERS
17
MAINTAINERS
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@ -640,13 +640,6 @@ S: Maintained
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F: drivers/amba/
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F: include/linux/amba/bus.h
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ARM/ADI ROADRUNNER MACHINE SUPPORT
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M: Lennert Buytenhek <kernel@wantstofly.org>
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L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
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S: Maintained
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F: arch/arm/mach-ixp23xx/
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F: arch/arm/mach-ixp23xx/include/mach/
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ARM/ADS SPHERE MACHINE SUPPORT
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M: Lennert Buytenhek <kernel@wantstofly.org>
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L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
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@ -859,21 +852,11 @@ M: Dan Williams <dan.j.williams@intel.com>
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L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
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S: Maintained
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ARM/INTEL IXP2000 ARM ARCHITECTURE
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M: Lennert Buytenhek <kernel@wantstofly.org>
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L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
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S: Maintained
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ARM/INTEL IXDP2850 MACHINE SUPPORT
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M: Lennert Buytenhek <kernel@wantstofly.org>
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L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
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S: Maintained
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ARM/INTEL IXP23XX ARM ARCHITECTURE
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M: Lennert Buytenhek <kernel@wantstofly.org>
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L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
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S: Maintained
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ARM/INTEL IXP4XX ARM ARCHITECTURE
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M: Imre Kaloz <kaloz@openwrt.org>
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M: Krzysztof Halasa <khc@pm.waw.pl>
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@ -527,28 +527,6 @@ config ARCH_IOP33X
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help
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Support for Intel's IOP33X (XScale) family of processors.
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config ARCH_IXP23XX
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bool "IXP23XX-based"
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depends on MMU
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select CPU_XSC3
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select PCI
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select ARCH_USES_GETTIMEOFFSET
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select NEED_MACH_IO_H
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select NEED_MACH_MEMORY_H
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help
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Support for Intel's IXP23xx (XScale) family of processors.
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config ARCH_IXP2000
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bool "IXP2400/2800-based"
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depends on MMU
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select CPU_XSCALE
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select PCI
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select ARCH_USES_GETTIMEOFFSET
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select NEED_MACH_IO_H
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select NEED_MACH_MEMORY_H
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help
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Support for Intel's IXP2400/2800 (XScale) family of processors.
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config ARCH_IXP4XX
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bool "IXP4xx-based"
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depends on MMU
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@ -1045,10 +1023,6 @@ source "arch/arm/mach-iop13xx/Kconfig"
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source "arch/arm/mach-ixp4xx/Kconfig"
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source "arch/arm/mach-ixp2000/Kconfig"
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source "arch/arm/mach-ixp23xx/Kconfig"
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source "arch/arm/mach-kirkwood/Kconfig"
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source "arch/arm/mach-ks8695/Kconfig"
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@ -149,8 +149,6 @@ machine-$(CONFIG_ARCH_INTEGRATOR) := integrator
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machine-$(CONFIG_ARCH_IOP13XX) := iop13xx
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machine-$(CONFIG_ARCH_IOP32X) := iop32x
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machine-$(CONFIG_ARCH_IOP33X) := iop33x
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machine-$(CONFIG_ARCH_IXP2000) := ixp2000
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machine-$(CONFIG_ARCH_IXP23XX) := ixp23xx
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machine-$(CONFIG_ARCH_IXP4XX) := ixp4xx
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machine-$(CONFIG_ARCH_KIRKWOOD) := kirkwood
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machine-$(CONFIG_ARCH_KS8695) := ks8695
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@ -32,10 +32,3 @@ __XScale_start:
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bic r0, r0, #0x1000 @ clear Icache
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mcr p15, 0, r0, c1, c0, 0
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#ifdef CONFIG_ARCH_IXP2000
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mov r1, #-1
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mov r0, #0xd6000000
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str r1, [r0, #0x14]
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str r1, [r0, #0x18]
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#endif
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@ -11,7 +11,5 @@ obj-$(CONFIG_DMABOUNCE) += dmabounce.o
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obj-$(CONFIG_SHARP_LOCOMO) += locomo.o
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obj-$(CONFIG_SHARP_PARAM) += sharpsl_param.o
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obj-$(CONFIG_SHARP_SCOOP) += scoop.o
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obj-$(CONFIG_ARCH_IXP2000) += uengine.o
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obj-$(CONFIG_ARCH_IXP23XX) += uengine.o
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obj-$(CONFIG_PCI_HOST_ITE8152) += it8152.o
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obj-$(CONFIG_ARM_TIMER_SP804) += timer-sp.o
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@ -1,507 +0,0 @@
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/*
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* Generic library functions for the microengines found on the Intel
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* IXP2000 series of network processors.
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*
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* Copyright (C) 2004, 2005 Lennert Buytenhek <buytenh@wantstofly.org>
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* Dedicated to Marija Kulikova.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU Lesser General Public License as
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* published by the Free Software Foundation; either version 2.1 of the
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* License, or (at your option) any later version.
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*/
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/slab.h>
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#include <linux/module.h>
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#include <linux/string.h>
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#include <linux/io.h>
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#include <mach/hardware.h>
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#include <asm/hardware/uengine.h>
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#if defined(CONFIG_ARCH_IXP2000)
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#define IXP_UENGINE_CSR_VIRT_BASE IXP2000_UENGINE_CSR_VIRT_BASE
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#define IXP_PRODUCT_ID IXP2000_PRODUCT_ID
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#define IXP_MISC_CONTROL IXP2000_MISC_CONTROL
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#define IXP_RESET1 IXP2000_RESET1
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#else
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#if defined(CONFIG_ARCH_IXP23XX)
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#define IXP_UENGINE_CSR_VIRT_BASE IXP23XX_UENGINE_CSR_VIRT_BASE
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#define IXP_PRODUCT_ID IXP23XX_PRODUCT_ID
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#define IXP_MISC_CONTROL IXP23XX_MISC_CONTROL
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#define IXP_RESET1 IXP23XX_RESET1
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#else
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#error unknown platform
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#endif
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#endif
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#define USTORE_ADDRESS 0x000
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#define USTORE_DATA_LOWER 0x004
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#define USTORE_DATA_UPPER 0x008
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#define CTX_ENABLES 0x018
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#define CC_ENABLE 0x01c
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#define CSR_CTX_POINTER 0x020
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#define INDIRECT_CTX_STS 0x040
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#define ACTIVE_CTX_STS 0x044
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#define INDIRECT_CTX_SIG_EVENTS 0x048
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#define INDIRECT_CTX_WAKEUP_EVENTS 0x050
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#define NN_PUT 0x080
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#define NN_GET 0x084
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#define TIMESTAMP_LOW 0x0c0
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#define TIMESTAMP_HIGH 0x0c4
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#define T_INDEX_BYTE_INDEX 0x0f4
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#define LOCAL_CSR_STATUS 0x180
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u32 ixp2000_uengine_mask;
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static void *ixp2000_uengine_csr_area(int uengine)
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{
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return ((void *)IXP_UENGINE_CSR_VIRT_BASE) + (uengine << 10);
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}
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/*
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* LOCAL_CSR_STATUS=1 after a read or write to a microengine's CSR
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* space means that the microengine we tried to access was also trying
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* to access its own CSR space on the same clock cycle as we did. When
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* this happens, we lose the arbitration process by default, and the
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* read or write we tried to do was not actually performed, so we try
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* again until it succeeds.
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*/
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u32 ixp2000_uengine_csr_read(int uengine, int offset)
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{
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void *uebase;
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u32 *local_csr_status;
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u32 *reg;
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u32 value;
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uebase = ixp2000_uengine_csr_area(uengine);
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local_csr_status = (u32 *)(uebase + LOCAL_CSR_STATUS);
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reg = (u32 *)(uebase + offset);
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do {
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value = ixp2000_reg_read(reg);
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} while (ixp2000_reg_read(local_csr_status) & 1);
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return value;
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}
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EXPORT_SYMBOL(ixp2000_uengine_csr_read);
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void ixp2000_uengine_csr_write(int uengine, int offset, u32 value)
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{
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void *uebase;
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u32 *local_csr_status;
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u32 *reg;
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uebase = ixp2000_uengine_csr_area(uengine);
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local_csr_status = (u32 *)(uebase + LOCAL_CSR_STATUS);
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reg = (u32 *)(uebase + offset);
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do {
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ixp2000_reg_write(reg, value);
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} while (ixp2000_reg_read(local_csr_status) & 1);
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}
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EXPORT_SYMBOL(ixp2000_uengine_csr_write);
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void ixp2000_uengine_reset(u32 uengine_mask)
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{
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u32 value;
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value = ixp2000_reg_read(IXP_RESET1) & ~ixp2000_uengine_mask;
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uengine_mask &= ixp2000_uengine_mask;
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ixp2000_reg_wrb(IXP_RESET1, value | uengine_mask);
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ixp2000_reg_wrb(IXP_RESET1, value);
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}
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EXPORT_SYMBOL(ixp2000_uengine_reset);
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void ixp2000_uengine_set_mode(int uengine, u32 mode)
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{
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/*
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* CTL_STR_PAR_EN: unconditionally enable parity checking on
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* control store.
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*/
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mode |= 0x10000000;
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ixp2000_uengine_csr_write(uengine, CTX_ENABLES, mode);
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/*
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* Enable updating of condition codes.
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*/
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ixp2000_uengine_csr_write(uengine, CC_ENABLE, 0x00002000);
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/*
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* Initialise other per-microengine registers.
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*/
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ixp2000_uengine_csr_write(uengine, NN_PUT, 0x00);
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ixp2000_uengine_csr_write(uengine, NN_GET, 0x00);
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ixp2000_uengine_csr_write(uengine, T_INDEX_BYTE_INDEX, 0);
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}
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EXPORT_SYMBOL(ixp2000_uengine_set_mode);
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static int make_even_parity(u32 x)
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{
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return hweight32(x) & 1;
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}
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static void ustore_write(int uengine, u64 insn)
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{
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/*
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* Generate even parity for top and bottom 20 bits.
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*/
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insn |= (u64)make_even_parity((insn >> 20) & 0x000fffff) << 41;
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insn |= (u64)make_even_parity(insn & 0x000fffff) << 40;
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/*
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* Write to microstore. The second write auto-increments
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* the USTORE_ADDRESS index register.
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*/
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ixp2000_uengine_csr_write(uengine, USTORE_DATA_LOWER, (u32)insn);
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ixp2000_uengine_csr_write(uengine, USTORE_DATA_UPPER, (u32)(insn >> 32));
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}
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void ixp2000_uengine_load_microcode(int uengine, u8 *ucode, int insns)
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{
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int i;
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/*
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* Start writing to microstore at address 0.
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*/
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ixp2000_uengine_csr_write(uengine, USTORE_ADDRESS, 0x80000000);
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for (i = 0; i < insns; i++) {
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u64 insn;
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insn = (((u64)ucode[0]) << 32) |
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(((u64)ucode[1]) << 24) |
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(((u64)ucode[2]) << 16) |
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(((u64)ucode[3]) << 8) |
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((u64)ucode[4]);
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ucode += 5;
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ustore_write(uengine, insn);
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}
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/*
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* Pad with a few NOPs at the end (to avoid the microengine
|
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* aborting as it prefetches beyond the last instruction), unless
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* we run off the end of the instruction store first, at which
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* point the address register will wrap back to zero.
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*/
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for (i = 0; i < 4; i++) {
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u32 addr;
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addr = ixp2000_uengine_csr_read(uengine, USTORE_ADDRESS);
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if (addr == 0x80000000)
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break;
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ustore_write(uengine, 0xf0000c0300ULL);
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}
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/*
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* End programming.
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*/
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ixp2000_uengine_csr_write(uengine, USTORE_ADDRESS, 0x00000000);
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}
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EXPORT_SYMBOL(ixp2000_uengine_load_microcode);
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void ixp2000_uengine_init_context(int uengine, int context, int pc)
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{
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/*
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* Select the right context for indirect access.
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*/
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ixp2000_uengine_csr_write(uengine, CSR_CTX_POINTER, context);
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/*
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* Initialise signal masks to immediately go to Ready state.
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*/
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ixp2000_uengine_csr_write(uengine, INDIRECT_CTX_SIG_EVENTS, 1);
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ixp2000_uengine_csr_write(uengine, INDIRECT_CTX_WAKEUP_EVENTS, 1);
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/*
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* Set program counter.
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*/
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ixp2000_uengine_csr_write(uengine, INDIRECT_CTX_STS, pc);
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}
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EXPORT_SYMBOL(ixp2000_uengine_init_context);
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void ixp2000_uengine_start_contexts(int uengine, u8 ctx_mask)
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{
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u32 mask;
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/*
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* Enable the specified context to go to Executing state.
|
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*/
|
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mask = ixp2000_uengine_csr_read(uengine, CTX_ENABLES);
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mask |= ctx_mask << 8;
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ixp2000_uengine_csr_write(uengine, CTX_ENABLES, mask);
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}
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EXPORT_SYMBOL(ixp2000_uengine_start_contexts);
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void ixp2000_uengine_stop_contexts(int uengine, u8 ctx_mask)
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{
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u32 mask;
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/*
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* Disable the Ready->Executing transition. Note that this
|
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* does not stop the context until it voluntarily yields.
|
||||
*/
|
||||
mask = ixp2000_uengine_csr_read(uengine, CTX_ENABLES);
|
||||
mask &= ~(ctx_mask << 8);
|
||||
ixp2000_uengine_csr_write(uengine, CTX_ENABLES, mask);
|
||||
}
|
||||
EXPORT_SYMBOL(ixp2000_uengine_stop_contexts);
|
||||
|
||||
static int check_ixp_type(struct ixp2000_uengine_code *c)
|
||||
{
|
||||
u32 product_id;
|
||||
u32 rev;
|
||||
|
||||
product_id = ixp2000_reg_read(IXP_PRODUCT_ID);
|
||||
if (((product_id >> 16) & 0x1f) != 0)
|
||||
return 0;
|
||||
|
||||
switch ((product_id >> 8) & 0xff) {
|
||||
#ifdef CONFIG_ARCH_IXP2000
|
||||
case 0: /* IXP2800 */
|
||||
if (!(c->cpu_model_bitmask & 4))
|
||||
return 0;
|
||||
break;
|
||||
|
||||
case 1: /* IXP2850 */
|
||||
if (!(c->cpu_model_bitmask & 8))
|
||||
return 0;
|
||||
break;
|
||||
|
||||
case 2: /* IXP2400 */
|
||||
if (!(c->cpu_model_bitmask & 2))
|
||||
return 0;
|
||||
break;
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_ARCH_IXP23XX
|
||||
case 4: /* IXP23xx */
|
||||
if (!(c->cpu_model_bitmask & 0x3f0))
|
||||
return 0;
|
||||
break;
|
||||
#endif
|
||||
|
||||
default:
|
||||
return 0;
|
||||
}
|
||||
|
||||
rev = product_id & 0xff;
|
||||
if (rev < c->cpu_min_revision || rev > c->cpu_max_revision)
|
||||
return 0;
|
||||
|
||||
return 1;
|
||||
}
|
||||
|
||||
static void generate_ucode(u8 *ucode, u32 *gpr_a, u32 *gpr_b)
|
||||
{
|
||||
int offset;
|
||||
int i;
|
||||
|
||||
offset = 0;
|
||||
|
||||
for (i = 0; i < 128; i++) {
|
||||
u8 b3;
|
||||
u8 b2;
|
||||
u8 b1;
|
||||
u8 b0;
|
||||
|
||||
b3 = (gpr_a[i] >> 24) & 0xff;
|
||||
b2 = (gpr_a[i] >> 16) & 0xff;
|
||||
b1 = (gpr_a[i] >> 8) & 0xff;
|
||||
b0 = gpr_a[i] & 0xff;
|
||||
|
||||
/* immed[@ai, (b1 << 8) | b0] */
|
||||
/* 11110000 0000VVVV VVVV11VV VVVVVV00 1IIIIIII */
|
||||
ucode[offset++] = 0xf0;
|
||||
ucode[offset++] = (b1 >> 4);
|
||||
ucode[offset++] = (b1 << 4) | 0x0c | (b0 >> 6);
|
||||
ucode[offset++] = (b0 << 2);
|
||||
ucode[offset++] = 0x80 | i;
|
||||
|
||||
/* immed_w1[@ai, (b3 << 8) | b2] */
|
||||
/* 11110100 0100VVVV VVVV11VV VVVVVV00 1IIIIIII */
|
||||
ucode[offset++] = 0xf4;
|
||||
ucode[offset++] = 0x40 | (b3 >> 4);
|
||||
ucode[offset++] = (b3 << 4) | 0x0c | (b2 >> 6);
|
||||
ucode[offset++] = (b2 << 2);
|
||||
ucode[offset++] = 0x80 | i;
|
||||
}
|
||||
|
||||
for (i = 0; i < 128; i++) {
|
||||
u8 b3;
|
||||
u8 b2;
|
||||
u8 b1;
|
||||
u8 b0;
|
||||
|
||||
b3 = (gpr_b[i] >> 24) & 0xff;
|
||||
b2 = (gpr_b[i] >> 16) & 0xff;
|
||||
b1 = (gpr_b[i] >> 8) & 0xff;
|
||||
b0 = gpr_b[i] & 0xff;
|
||||
|
||||
/* immed[@bi, (b1 << 8) | b0] */
|
||||
/* 11110000 0000VVVV VVVV001I IIIIII11 VVVVVVVV */
|
||||
ucode[offset++] = 0xf0;
|
||||
ucode[offset++] = (b1 >> 4);
|
||||
ucode[offset++] = (b1 << 4) | 0x02 | (i >> 6);
|
||||
ucode[offset++] = (i << 2) | 0x03;
|
||||
ucode[offset++] = b0;
|
||||
|
||||
/* immed_w1[@bi, (b3 << 8) | b2] */
|
||||
/* 11110100 0100VVVV VVVV001I IIIIII11 VVVVVVVV */
|
||||
ucode[offset++] = 0xf4;
|
||||
ucode[offset++] = 0x40 | (b3 >> 4);
|
||||
ucode[offset++] = (b3 << 4) | 0x02 | (i >> 6);
|
||||
ucode[offset++] = (i << 2) | 0x03;
|
||||
ucode[offset++] = b2;
|
||||
}
|
||||
|
||||
/* ctx_arb[kill] */
|
||||
ucode[offset++] = 0xe0;
|
||||
ucode[offset++] = 0x00;
|
||||
ucode[offset++] = 0x01;
|
||||
ucode[offset++] = 0x00;
|
||||
ucode[offset++] = 0x00;
|
||||
}
|
||||
|
||||
static int set_initial_registers(int uengine, struct ixp2000_uengine_code *c)
|
||||
{
|
||||
int per_ctx_regs;
|
||||
u32 *gpr_a;
|
||||
u32 *gpr_b;
|
||||
u8 *ucode;
|
||||
int i;
|
||||
|
||||
gpr_a = kzalloc(128 * sizeof(u32), GFP_KERNEL);
|
||||
gpr_b = kzalloc(128 * sizeof(u32), GFP_KERNEL);
|
||||
ucode = kmalloc(513 * 5, GFP_KERNEL);
|
||||
if (gpr_a == NULL || gpr_b == NULL || ucode == NULL) {
|
||||
kfree(ucode);
|
||||
kfree(gpr_b);
|
||||
kfree(gpr_a);
|
||||
return 1;
|
||||
}
|
||||
|
||||
per_ctx_regs = 16;
|
||||
if (c->uengine_parameters & IXP2000_UENGINE_4_CONTEXTS)
|
||||
per_ctx_regs = 32;
|
||||
|
||||
for (i = 0; i < 256; i++) {
|
||||
struct ixp2000_reg_value *r = c->initial_reg_values + i;
|
||||
u32 *bank;
|
||||
int inc;
|
||||
int j;
|
||||
|
||||
if (r->reg == -1)
|
||||
break;
|
||||
|
||||
bank = (r->reg & 0x400) ? gpr_b : gpr_a;
|
||||
inc = (r->reg & 0x80) ? 128 : per_ctx_regs;
|
||||
|
||||
j = r->reg & 0x7f;
|
||||
while (j < 128) {
|
||||
bank[j] = r->value;
|
||||
j += inc;
|
||||
}
|
||||
}
|
||||
|
||||
generate_ucode(ucode, gpr_a, gpr_b);
|
||||
ixp2000_uengine_load_microcode(uengine, ucode, 513);
|
||||
ixp2000_uengine_init_context(uengine, 0, 0);
|
||||
ixp2000_uengine_start_contexts(uengine, 0x01);
|
||||
for (i = 0; i < 100; i++) {
|
||||
u32 status;
|
||||
|
||||
status = ixp2000_uengine_csr_read(uengine, ACTIVE_CTX_STS);
|
||||
if (!(status & 0x80000000))
|
||||
break;
|
||||
}
|
||||
ixp2000_uengine_stop_contexts(uengine, 0x01);
|
||||
|
||||
kfree(ucode);
|
||||
kfree(gpr_b);
|
||||
kfree(gpr_a);
|
||||
|
||||
return !!(i == 100);
|
||||
}
|
||||
|
||||
int ixp2000_uengine_load(int uengine, struct ixp2000_uengine_code *c)
|
||||
{
|
||||
int ctx;
|
||||
|
||||
if (!check_ixp_type(c))
|
||||
return 1;
|
||||
|
||||
if (!(ixp2000_uengine_mask & (1 << uengine)))
|
||||
return 1;
|
||||
|
||||
ixp2000_uengine_reset(1 << uengine);
|
||||
ixp2000_uengine_set_mode(uengine, c->uengine_parameters);
|
||||
if (set_initial_registers(uengine, c))
|
||||
return 1;
|
||||
ixp2000_uengine_load_microcode(uengine, c->insns, c->num_insns);
|
||||
|
||||
for (ctx = 0; ctx < 8; ctx++)
|
||||
ixp2000_uengine_init_context(uengine, ctx, 0);
|
||||
|
||||
return 0;
|
||||
}
|
||||
EXPORT_SYMBOL(ixp2000_uengine_load);
|
||||
|
||||
|
||||
static int __init ixp2000_uengine_init(void)
|
||||
{
|
||||
int uengine;
|
||||
u32 value;
|
||||
|
||||
/*
|
||||
* Determine number of microengines present.
|
||||
*/
|
||||
switch ((ixp2000_reg_read(IXP_PRODUCT_ID) >> 8) & 0x1fff) {
|
||||
#ifdef CONFIG_ARCH_IXP2000
|
||||
case 0: /* IXP2800 */
|
||||
case 1: /* IXP2850 */
|
||||
ixp2000_uengine_mask = 0x00ff00ff;
|
||||
break;
|
||||
|
||||
case 2: /* IXP2400 */
|
||||
ixp2000_uengine_mask = 0x000f000f;
|
||||
break;
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_ARCH_IXP23XX
|
||||
case 4: /* IXP23xx */
|
||||
ixp2000_uengine_mask = (*IXP23XX_EXP_CFG_FUSE >> 8) & 0xf;
|
||||
break;
|
||||
#endif
|
||||
|
||||
default:
|
||||
printk(KERN_INFO "Detected unknown IXP2000 model (%.8x)\n",
|
||||
(unsigned int)ixp2000_reg_read(IXP_PRODUCT_ID));
|
||||
ixp2000_uengine_mask = 0x00000000;
|
||||
break;
|
||||
}
|
||||
|
||||
/*
|
||||
* Reset microengines.
|
||||
*/
|
||||
ixp2000_uengine_reset(ixp2000_uengine_mask);
|
||||
|
||||
/*
|
||||
* Synchronise timestamp counters across all microengines.
|
||||
*/
|
||||
value = ixp2000_reg_read(IXP_MISC_CONTROL);
|
||||
ixp2000_reg_wrb(IXP_MISC_CONTROL, value & ~0x80);
|
||||
for (uengine = 0; uengine < 32; uengine++) {
|
||||
if (ixp2000_uengine_mask & (1 << uengine)) {
|
||||
ixp2000_uengine_csr_write(uengine, TIMESTAMP_LOW, 0);
|
||||
ixp2000_uengine_csr_write(uengine, TIMESTAMP_HIGH, 0);
|
||||
}
|
||||
}
|
||||
ixp2000_reg_wrb(IXP_MISC_CONTROL, value | 0x80);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
subsys_initcall(ixp2000_uengine_init);
|
||||
|
|
@ -1,99 +0,0 @@
|
|||
CONFIG_EXPERIMENTAL=y
|
||||
CONFIG_SYSVIPC=y
|
||||
CONFIG_BSD_PROCESS_ACCT=y
|
||||
CONFIG_LOG_BUF_SHIFT=14
|
||||
CONFIG_BLK_DEV_INITRD=y
|
||||
CONFIG_EXPERT=y
|
||||
# CONFIG_HOTPLUG is not set
|
||||
CONFIG_SLAB=y
|
||||
CONFIG_MODULES=y
|
||||
CONFIG_MODULE_UNLOAD=y
|
||||
CONFIG_ARCH_IXP2000=y
|
||||
CONFIG_ARCH_ENP2611=y
|
||||
CONFIG_ARCH_IXDP2400=y
|
||||
CONFIG_ARCH_IXDP2800=y
|
||||
CONFIG_ARCH_IXDP2401=y
|
||||
CONFIG_ARCH_IXDP2801=y
|
||||
# CONFIG_IXP2000_SUPPORT_BROKEN_PCI_IO is not set
|
||||
# CONFIG_ARM_THUMB is not set
|
||||
CONFIG_CPU_BIG_ENDIAN=y
|
||||
CONFIG_ZBOOT_ROM_TEXT=0x0
|
||||
CONFIG_ZBOOT_ROM_BSS=0x0
|
||||
CONFIG_CMDLINE="console=ttyS0,57600 root=/dev/nfs ip=bootp mem=64M@0x0"
|
||||
CONFIG_FPE_NWFPE=y
|
||||
CONFIG_FPE_NWFPE_XP=y
|
||||
CONFIG_NET=y
|
||||
CONFIG_PACKET=y
|
||||
CONFIG_UNIX=y
|
||||
CONFIG_INET=y
|
||||
CONFIG_IP_PNP=y
|
||||
CONFIG_IP_PNP_DHCP=y
|
||||
CONFIG_IP_PNP_BOOTP=y
|
||||
CONFIG_SYN_COOKIES=y
|
||||
CONFIG_IPV6=y
|
||||
# CONFIG_INET6_XFRM_MODE_TRANSPORT is not set
|
||||
# CONFIG_INET6_XFRM_MODE_TUNNEL is not set
|
||||
# CONFIG_INET6_XFRM_MODE_BEET is not set
|
||||
# CONFIG_IPV6_SIT is not set
|
||||
# CONFIG_PREVENT_FIRMWARE_BUILD is not set
|
||||
CONFIG_MTD=y
|
||||
CONFIG_MTD_PARTITIONS=y
|
||||
CONFIG_MTD_REDBOOT_PARTS=y
|
||||
CONFIG_MTD_REDBOOT_PARTS_UNALLOCATED=y
|
||||
CONFIG_MTD_REDBOOT_PARTS_READONLY=y
|
||||
CONFIG_MTD_CHAR=y
|
||||
CONFIG_MTD_BLOCK=y
|
||||
CONFIG_MTD_CFI=y
|
||||
CONFIG_MTD_CFI_INTELEXT=y
|
||||
CONFIG_MTD_COMPLEX_MAPPINGS=y
|
||||
CONFIG_MTD_IXP2000=y
|
||||
CONFIG_BLK_DEV_LOOP=y
|
||||
CONFIG_BLK_DEV_NBD=y
|
||||
CONFIG_BLK_DEV_RAM=y
|
||||
CONFIG_BLK_DEV_RAM_SIZE=8192
|
||||
CONFIG_EEPROM_LEGACY=y
|
||||
CONFIG_NETDEVICES=y
|
||||
CONFIG_DUMMY=y
|
||||
CONFIG_NET_ETHERNET=y
|
||||
CONFIG_NET_PCI=y
|
||||
CONFIG_CS89x0=y
|
||||
CONFIG_E100=y
|
||||
CONFIG_ENP2611_MSF_NET=y
|
||||
CONFIG_WAN=y
|
||||
CONFIG_HDLC=y
|
||||
CONFIG_HDLC_RAW=y
|
||||
CONFIG_HDLC_CISCO=y
|
||||
CONFIG_HDLC_FR=y
|
||||
CONFIG_HDLC_PPP=y
|
||||
CONFIG_DLCI=y
|
||||
# CONFIG_INPUT_KEYBOARD is not set
|
||||
# CONFIG_INPUT_MOUSE is not set
|
||||
# CONFIG_SERIO is not set
|
||||
# CONFIG_VT is not set
|
||||
CONFIG_SERIAL_8250=y
|
||||
CONFIG_SERIAL_8250_CONSOLE=y
|
||||
CONFIG_SERIAL_8250_NR_UARTS=3
|
||||
# CONFIG_HW_RANDOM is not set
|
||||
CONFIG_I2C=y
|
||||
CONFIG_I2C_CHARDEV=y
|
||||
CONFIG_I2C_IXP2000=y
|
||||
CONFIG_WATCHDOG=y
|
||||
CONFIG_IXP2000_WATCHDOG=y
|
||||
CONFIG_EXT2_FS=y
|
||||
CONFIG_EXT2_FS_XATTR=y
|
||||
CONFIG_EXT2_FS_POSIX_ACL=y
|
||||
CONFIG_EXT3_FS=y
|
||||
CONFIG_EXT3_FS_POSIX_ACL=y
|
||||
CONFIG_INOTIFY=y
|
||||
CONFIG_TMPFS=y
|
||||
CONFIG_JFFS2_FS=y
|
||||
CONFIG_NFS_FS=y
|
||||
CONFIG_NFS_V3=y
|
||||
CONFIG_ROOT_NFS=y
|
||||
CONFIG_PARTITION_ADVANCED=y
|
||||
CONFIG_MAGIC_SYSRQ=y
|
||||
CONFIG_DEBUG_KERNEL=y
|
||||
CONFIG_DEBUG_MUTEXES=y
|
||||
CONFIG_DEBUG_USER=y
|
||||
CONFIG_DEBUG_ERRORS=y
|
||||
CONFIG_DEBUG_LL=y
|
||||
|
|
@ -1,105 +0,0 @@
|
|||
CONFIG_EXPERIMENTAL=y
|
||||
CONFIG_SYSVIPC=y
|
||||
CONFIG_BSD_PROCESS_ACCT=y
|
||||
CONFIG_LOG_BUF_SHIFT=14
|
||||
CONFIG_BLK_DEV_INITRD=y
|
||||
CONFIG_EXPERT=y
|
||||
CONFIG_SLAB=y
|
||||
CONFIG_MODULES=y
|
||||
CONFIG_MODULE_UNLOAD=y
|
||||
CONFIG_ARCH_IXP23XX=y
|
||||
CONFIG_MACH_ESPRESSO=y
|
||||
CONFIG_MACH_IXDP2351=y
|
||||
CONFIG_MACH_ROADRUNNER=y
|
||||
# CONFIG_ARM_THUMB is not set
|
||||
CONFIG_CPU_BIG_ENDIAN=y
|
||||
CONFIG_ZBOOT_ROM_TEXT=0x0
|
||||
CONFIG_ZBOOT_ROM_BSS=0x0
|
||||
CONFIG_CMDLINE="console=ttyS0,115200 root=/dev/nfs ip=bootp"
|
||||
CONFIG_FPE_NWFPE=y
|
||||
CONFIG_FPE_NWFPE_XP=y
|
||||
CONFIG_NET=y
|
||||
CONFIG_PACKET=y
|
||||
CONFIG_UNIX=y
|
||||
CONFIG_INET=y
|
||||
CONFIG_IP_PNP=y
|
||||
CONFIG_IP_PNP_DHCP=y
|
||||
CONFIG_IP_PNP_BOOTP=y
|
||||
CONFIG_SYN_COOKIES=y
|
||||
CONFIG_IPV6=y
|
||||
# CONFIG_INET6_XFRM_MODE_TRANSPORT is not set
|
||||
# CONFIG_INET6_XFRM_MODE_TUNNEL is not set
|
||||
# CONFIG_INET6_XFRM_MODE_BEET is not set
|
||||
# CONFIG_IPV6_SIT is not set
|
||||
# CONFIG_PREVENT_FIRMWARE_BUILD is not set
|
||||
# CONFIG_FW_LOADER is not set
|
||||
CONFIG_MTD=y
|
||||
CONFIG_MTD_PARTITIONS=y
|
||||
CONFIG_MTD_REDBOOT_PARTS=y
|
||||
CONFIG_MTD_REDBOOT_PARTS_UNALLOCATED=y
|
||||
CONFIG_MTD_REDBOOT_PARTS_READONLY=y
|
||||
CONFIG_MTD_CHAR=y
|
||||
CONFIG_MTD_BLOCK=y
|
||||
CONFIG_MTD_CFI=y
|
||||
CONFIG_MTD_CFI_INTELEXT=y
|
||||
CONFIG_MTD_COMPLEX_MAPPINGS=y
|
||||
CONFIG_MTD_PHYSMAP=y
|
||||
CONFIG_BLK_DEV_LOOP=y
|
||||
CONFIG_BLK_DEV_NBD=y
|
||||
CONFIG_BLK_DEV_RAM=y
|
||||
CONFIG_BLK_DEV_RAM_SIZE=8192
|
||||
CONFIG_EEPROM_LEGACY=y
|
||||
CONFIG_IDE=y
|
||||
CONFIG_BLK_DEV_SIIMAGE=y
|
||||
CONFIG_SCSI=y
|
||||
CONFIG_BLK_DEV_SD=y
|
||||
CONFIG_NETDEVICES=y
|
||||
CONFIG_DUMMY=y
|
||||
CONFIG_NET_ETHERNET=y
|
||||
CONFIG_NET_PCI=y
|
||||
CONFIG_E100=y
|
||||
CONFIG_E1000=y
|
||||
CONFIG_WAN=y
|
||||
CONFIG_HDLC=y
|
||||
CONFIG_HDLC_RAW=y
|
||||
CONFIG_HDLC_CISCO=y
|
||||
CONFIG_HDLC_FR=y
|
||||
CONFIG_HDLC_PPP=y
|
||||
CONFIG_DLCI=y
|
||||
# CONFIG_INPUT_KEYBOARD is not set
|
||||
# CONFIG_INPUT_MOUSE is not set
|
||||
# CONFIG_SERIO is not set
|
||||
# CONFIG_VT is not set
|
||||
CONFIG_SERIAL_8250=y
|
||||
CONFIG_SERIAL_8250_CONSOLE=y
|
||||
# CONFIG_HW_RANDOM is not set
|
||||
CONFIG_I2C=y
|
||||
CONFIG_I2C_CHARDEV=y
|
||||
CONFIG_WATCHDOG=y
|
||||
# CONFIG_USB_HID is not set
|
||||
CONFIG_USB=y
|
||||
CONFIG_USB_MON=y
|
||||
CONFIG_USB_EHCI_HCD=y
|
||||
CONFIG_USB_OHCI_HCD=y
|
||||
CONFIG_USB_UHCI_HCD=y
|
||||
CONFIG_USB_STORAGE=y
|
||||
CONFIG_EXT2_FS=y
|
||||
CONFIG_EXT2_FS_XATTR=y
|
||||
CONFIG_EXT2_FS_POSIX_ACL=y
|
||||
CONFIG_EXT3_FS=y
|
||||
CONFIG_EXT3_FS_POSIX_ACL=y
|
||||
CONFIG_INOTIFY=y
|
||||
CONFIG_MSDOS_FS=y
|
||||
CONFIG_TMPFS=y
|
||||
CONFIG_JFFS2_FS=y
|
||||
CONFIG_NFS_FS=y
|
||||
CONFIG_NFS_V3=y
|
||||
CONFIG_ROOT_NFS=y
|
||||
CONFIG_PARTITION_ADVANCED=y
|
||||
CONFIG_NLS_CODEPAGE_437=y
|
||||
CONFIG_MAGIC_SYSRQ=y
|
||||
CONFIG_DEBUG_KERNEL=y
|
||||
CONFIG_DEBUG_MUTEXES=y
|
||||
CONFIG_DEBUG_USER=y
|
||||
CONFIG_DEBUG_ERRORS=y
|
||||
CONFIG_DEBUG_LL=y
|
||||
|
|
@ -1,62 +0,0 @@
|
|||
/*
|
||||
* Generic library functions for the microengines found on the Intel
|
||||
* IXP2000 series of network processors.
|
||||
*
|
||||
* Copyright (C) 2004, 2005 Lennert Buytenhek <buytenh@wantstofly.org>
|
||||
* Dedicated to Marija Kulikova.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU Lesser General Public License as
|
||||
* published by the Free Software Foundation; either version 2.1 of the
|
||||
* License, or (at your option) any later version.
|
||||
*/
|
||||
|
||||
#ifndef __IXP2000_UENGINE_H
|
||||
#define __IXP2000_UENGINE_H
|
||||
|
||||
extern u32 ixp2000_uengine_mask;
|
||||
|
||||
struct ixp2000_uengine_code
|
||||
{
|
||||
u32 cpu_model_bitmask;
|
||||
u8 cpu_min_revision;
|
||||
u8 cpu_max_revision;
|
||||
|
||||
u32 uengine_parameters;
|
||||
|
||||
struct ixp2000_reg_value {
|
||||
int reg;
|
||||
u32 value;
|
||||
} *initial_reg_values;
|
||||
|
||||
int num_insns;
|
||||
u8 *insns;
|
||||
};
|
||||
|
||||
u32 ixp2000_uengine_csr_read(int uengine, int offset);
|
||||
void ixp2000_uengine_csr_write(int uengine, int offset, u32 value);
|
||||
void ixp2000_uengine_reset(u32 uengine_mask);
|
||||
void ixp2000_uengine_set_mode(int uengine, u32 mode);
|
||||
void ixp2000_uengine_load_microcode(int uengine, u8 *ucode, int insns);
|
||||
void ixp2000_uengine_init_context(int uengine, int context, int pc);
|
||||
void ixp2000_uengine_start_contexts(int uengine, u8 ctx_mask);
|
||||
void ixp2000_uengine_stop_contexts(int uengine, u8 ctx_mask);
|
||||
int ixp2000_uengine_load(int uengine, struct ixp2000_uengine_code *c);
|
||||
|
||||
#define IXP2000_UENGINE_8_CONTEXTS 0x00000000
|
||||
#define IXP2000_UENGINE_4_CONTEXTS 0x80000000
|
||||
#define IXP2000_UENGINE_PRN_UPDATE_EVERY 0x40000000
|
||||
#define IXP2000_UENGINE_PRN_UPDATE_ON_ACCESS 0x00000000
|
||||
#define IXP2000_UENGINE_NN_FROM_SELF 0x00100000
|
||||
#define IXP2000_UENGINE_NN_FROM_PREVIOUS 0x00000000
|
||||
#define IXP2000_UENGINE_ASSERT_EMPTY_AT_3 0x000c0000
|
||||
#define IXP2000_UENGINE_ASSERT_EMPTY_AT_2 0x00080000
|
||||
#define IXP2000_UENGINE_ASSERT_EMPTY_AT_1 0x00040000
|
||||
#define IXP2000_UENGINE_ASSERT_EMPTY_AT_0 0x00000000
|
||||
#define IXP2000_UENGINE_LM_ADDR1_GLOBAL 0x00020000
|
||||
#define IXP2000_UENGINE_LM_ADDR1_PER_CONTEXT 0x00000000
|
||||
#define IXP2000_UENGINE_LM_ADDR0_GLOBAL 0x00010000
|
||||
#define IXP2000_UENGINE_LM_ADDR0_PER_CONTEXT 0x00000000
|
||||
|
||||
|
||||
#endif
|
||||
|
|
@ -1,72 +0,0 @@
|
|||
|
||||
if ARCH_IXP2000
|
||||
|
||||
config ARCH_SUPPORTS_BIG_ENDIAN
|
||||
bool
|
||||
default y
|
||||
|
||||
menu "Intel IXP2400/2800 Implementation Options"
|
||||
|
||||
comment "IXP2400/2800 Platforms"
|
||||
|
||||
config ARCH_ENP2611
|
||||
bool "Support Radisys ENP-2611"
|
||||
help
|
||||
Say 'Y' here if you want your kernel to support the Radisys
|
||||
ENP2611 PCI network processing card. For more information on
|
||||
this card, see <file:Documentation/arm/IXP2000>.
|
||||
|
||||
config ARCH_IXDP2400
|
||||
bool "Support Intel IXDP2400"
|
||||
help
|
||||
Say 'Y' here if you want your kernel to support the Intel
|
||||
IXDP2400 reference platform. For more information on
|
||||
this platform, see <file:Documentation/arm/IXP2000>.
|
||||
|
||||
config ARCH_IXDP2800
|
||||
bool "Support Intel IXDP2800"
|
||||
help
|
||||
Say 'Y' here if you want your kernel to support the Intel
|
||||
IXDP2800 reference platform. For more information on
|
||||
this platform, see <file:Documentation/arm/IXP2000>.
|
||||
|
||||
config ARCH_IXDP2X00
|
||||
bool
|
||||
depends on ARCH_IXDP2400 || ARCH_IXDP2800
|
||||
default y
|
||||
|
||||
config ARCH_IXDP2401
|
||||
bool "Support Intel IXDP2401"
|
||||
help
|
||||
Say 'Y' here if you want your kernel to support the Intel
|
||||
IXDP2401 reference platform. For more information on
|
||||
this platform, see <file:Documentation/arm/IXP2000>.
|
||||
|
||||
config ARCH_IXDP2801
|
||||
bool "Support Intel IXDP2801 and IXDP28x5"
|
||||
help
|
||||
Say 'Y' here if you want your kernel to support the Intel
|
||||
IXDP2801/2805/2855 reference platforms. For more information on
|
||||
this platform, see <file:Documentation/arm/IXP2000>.
|
||||
|
||||
config MACH_IXDP28X5
|
||||
bool
|
||||
depends on ARCH_IXDP2801
|
||||
default y
|
||||
|
||||
config ARCH_IXDP2X01
|
||||
bool
|
||||
depends on ARCH_IXDP2401 || ARCH_IXDP2801
|
||||
default y
|
||||
|
||||
config IXP2000_SUPPORT_BROKEN_PCI_IO
|
||||
bool "Support broken PCI I/O on older IXP2000s"
|
||||
default y
|
||||
help
|
||||
Say 'N' here if you only intend to run your kernel on an
|
||||
IXP2000 B0 or later model and do not need the PCI I/O
|
||||
byteswap workaround. Say 'Y' otherwise.
|
||||
|
||||
endmenu
|
||||
|
||||
endif
|
||||
|
|
@ -1,14 +0,0 @@
|
|||
#
|
||||
# Makefile for the linux kernel.
|
||||
#
|
||||
obj-y := core.o pci.o
|
||||
obj-m :=
|
||||
obj-n :=
|
||||
obj- :=
|
||||
|
||||
obj-$(CONFIG_ARCH_ENP2611) += enp2611.o
|
||||
obj-$(CONFIG_ARCH_IXDP2400) += ixdp2400.o
|
||||
obj-$(CONFIG_ARCH_IXDP2800) += ixdp2800.o
|
||||
obj-$(CONFIG_ARCH_IXDP2X00) += ixdp2x00.o
|
||||
obj-$(CONFIG_ARCH_IXDP2X01) += ixdp2x01.o
|
||||
|
||||
|
|
@ -1,3 +0,0 @@
|
|||
zreladdr-y += 0x00008000
|
||||
params_phys-y := 0x00000100
|
||||
|
||||
|
|
@ -1,520 +0,0 @@
|
|||
/*
|
||||
* arch/arm/mach-ixp2000/core.c
|
||||
*
|
||||
* Common routines used by all IXP2400/2800 based platforms.
|
||||
*
|
||||
* Author: Deepak Saxena <dsaxena@plexity.net>
|
||||
*
|
||||
* Copyright 2004 (C) MontaVista Software, Inc.
|
||||
*
|
||||
* Based on work Copyright (C) 2002-2003 Intel Corporation
|
||||
*
|
||||
* This file is licensed under the terms of the GNU General Public
|
||||
* License version 2. This program is licensed "as is" without any
|
||||
* warranty of any kind, whether express or implied.
|
||||
*/
|
||||
#include <linux/gpio.h>
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/spinlock.h>
|
||||
#include <linux/sched.h>
|
||||
#include <linux/interrupt.h>
|
||||
#include <linux/irq.h>
|
||||
#include <linux/serial.h>
|
||||
#include <linux/tty.h>
|
||||
#include <linux/bitops.h>
|
||||
#include <linux/serial_8250.h>
|
||||
#include <linux/mm.h>
|
||||
#include <linux/export.h>
|
||||
|
||||
#include <asm/types.h>
|
||||
#include <asm/setup.h>
|
||||
#include <asm/memory.h>
|
||||
#include <mach/hardware.h>
|
||||
#include <asm/irq.h>
|
||||
#include <asm/tlbflush.h>
|
||||
#include <asm/pgtable.h>
|
||||
|
||||
#include <asm/mach/map.h>
|
||||
#include <asm/mach/time.h>
|
||||
#include <asm/mach/irq.h>
|
||||
|
||||
#include <mach/gpio-ixp2000.h>
|
||||
|
||||
static DEFINE_SPINLOCK(ixp2000_slowport_lock);
|
||||
static unsigned long ixp2000_slowport_irq_flags;
|
||||
|
||||
/*************************************************************************
|
||||
* Slowport access routines
|
||||
*************************************************************************/
|
||||
void ixp2000_acquire_slowport(struct slowport_cfg *new_cfg, struct slowport_cfg *old_cfg)
|
||||
{
|
||||
spin_lock_irqsave(&ixp2000_slowport_lock, ixp2000_slowport_irq_flags);
|
||||
|
||||
old_cfg->CCR = *IXP2000_SLOWPORT_CCR;
|
||||
old_cfg->WTC = *IXP2000_SLOWPORT_WTC2;
|
||||
old_cfg->RTC = *IXP2000_SLOWPORT_RTC2;
|
||||
old_cfg->PCR = *IXP2000_SLOWPORT_PCR;
|
||||
old_cfg->ADC = *IXP2000_SLOWPORT_ADC;
|
||||
|
||||
ixp2000_reg_write(IXP2000_SLOWPORT_CCR, new_cfg->CCR);
|
||||
ixp2000_reg_write(IXP2000_SLOWPORT_WTC2, new_cfg->WTC);
|
||||
ixp2000_reg_write(IXP2000_SLOWPORT_RTC2, new_cfg->RTC);
|
||||
ixp2000_reg_write(IXP2000_SLOWPORT_PCR, new_cfg->PCR);
|
||||
ixp2000_reg_wrb(IXP2000_SLOWPORT_ADC, new_cfg->ADC);
|
||||
}
|
||||
|
||||
void ixp2000_release_slowport(struct slowport_cfg *old_cfg)
|
||||
{
|
||||
ixp2000_reg_write(IXP2000_SLOWPORT_CCR, old_cfg->CCR);
|
||||
ixp2000_reg_write(IXP2000_SLOWPORT_WTC2, old_cfg->WTC);
|
||||
ixp2000_reg_write(IXP2000_SLOWPORT_RTC2, old_cfg->RTC);
|
||||
ixp2000_reg_write(IXP2000_SLOWPORT_PCR, old_cfg->PCR);
|
||||
ixp2000_reg_wrb(IXP2000_SLOWPORT_ADC, old_cfg->ADC);
|
||||
|
||||
spin_unlock_irqrestore(&ixp2000_slowport_lock,
|
||||
ixp2000_slowport_irq_flags);
|
||||
}
|
||||
|
||||
/*************************************************************************
|
||||
* Chip specific mappings shared by all IXP2000 systems
|
||||
*************************************************************************/
|
||||
static struct map_desc ixp2000_io_desc[] __initdata = {
|
||||
{
|
||||
.virtual = IXP2000_CAP_VIRT_BASE,
|
||||
.pfn = __phys_to_pfn(IXP2000_CAP_PHYS_BASE),
|
||||
.length = IXP2000_CAP_SIZE,
|
||||
.type = MT_DEVICE,
|
||||
}, {
|
||||
.virtual = IXP2000_INTCTL_VIRT_BASE,
|
||||
.pfn = __phys_to_pfn(IXP2000_INTCTL_PHYS_BASE),
|
||||
.length = IXP2000_INTCTL_SIZE,
|
||||
.type = MT_DEVICE,
|
||||
}, {
|
||||
.virtual = IXP2000_PCI_CREG_VIRT_BASE,
|
||||
.pfn = __phys_to_pfn(IXP2000_PCI_CREG_PHYS_BASE),
|
||||
.length = IXP2000_PCI_CREG_SIZE,
|
||||
.type = MT_DEVICE,
|
||||
}, {
|
||||
.virtual = IXP2000_PCI_CSR_VIRT_BASE,
|
||||
.pfn = __phys_to_pfn(IXP2000_PCI_CSR_PHYS_BASE),
|
||||
.length = IXP2000_PCI_CSR_SIZE,
|
||||
.type = MT_DEVICE,
|
||||
}, {
|
||||
.virtual = IXP2000_MSF_VIRT_BASE,
|
||||
.pfn = __phys_to_pfn(IXP2000_MSF_PHYS_BASE),
|
||||
.length = IXP2000_MSF_SIZE,
|
||||
.type = MT_DEVICE,
|
||||
}, {
|
||||
.virtual = IXP2000_SCRATCH_RING_VIRT_BASE,
|
||||
.pfn = __phys_to_pfn(IXP2000_SCRATCH_RING_PHYS_BASE),
|
||||
.length = IXP2000_SCRATCH_RING_SIZE,
|
||||
.type = MT_DEVICE,
|
||||
}, {
|
||||
.virtual = IXP2000_SRAM0_VIRT_BASE,
|
||||
.pfn = __phys_to_pfn(IXP2000_SRAM0_PHYS_BASE),
|
||||
.length = IXP2000_SRAM0_SIZE,
|
||||
.type = MT_DEVICE,
|
||||
}, {
|
||||
.virtual = IXP2000_PCI_IO_VIRT_BASE,
|
||||
.pfn = __phys_to_pfn(IXP2000_PCI_IO_PHYS_BASE),
|
||||
.length = IXP2000_PCI_IO_SIZE,
|
||||
.type = MT_DEVICE,
|
||||
}, {
|
||||
.virtual = IXP2000_PCI_CFG0_VIRT_BASE,
|
||||
.pfn = __phys_to_pfn(IXP2000_PCI_CFG0_PHYS_BASE),
|
||||
.length = IXP2000_PCI_CFG0_SIZE,
|
||||
.type = MT_DEVICE,
|
||||
}, {
|
||||
.virtual = IXP2000_PCI_CFG1_VIRT_BASE,
|
||||
.pfn = __phys_to_pfn(IXP2000_PCI_CFG1_PHYS_BASE),
|
||||
.length = IXP2000_PCI_CFG1_SIZE,
|
||||
.type = MT_DEVICE,
|
||||
}
|
||||
};
|
||||
|
||||
void __init ixp2000_map_io(void)
|
||||
{
|
||||
iotable_init(ixp2000_io_desc, ARRAY_SIZE(ixp2000_io_desc));
|
||||
|
||||
/* Set slowport to 8-bit mode. */
|
||||
ixp2000_reg_wrb(IXP2000_SLOWPORT_FRM, 1);
|
||||
}
|
||||
|
||||
|
||||
/*************************************************************************
|
||||
* Serial port support for IXP2000
|
||||
*************************************************************************/
|
||||
static struct plat_serial8250_port ixp2000_serial_port[] = {
|
||||
{
|
||||
.mapbase = IXP2000_UART_PHYS_BASE,
|
||||
.membase = (char *)(IXP2000_UART_VIRT_BASE + 3),
|
||||
.irq = IRQ_IXP2000_UART,
|
||||
.flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
|
||||
.iotype = UPIO_MEM,
|
||||
.regshift = 2,
|
||||
.uartclk = 50000000,
|
||||
},
|
||||
{ },
|
||||
};
|
||||
|
||||
static struct resource ixp2000_uart_resource = {
|
||||
.start = IXP2000_UART_PHYS_BASE,
|
||||
.end = IXP2000_UART_PHYS_BASE + 0x1f,
|
||||
.flags = IORESOURCE_MEM,
|
||||
};
|
||||
|
||||
static struct platform_device ixp2000_serial_device = {
|
||||
.name = "serial8250",
|
||||
.id = PLAT8250_DEV_PLATFORM,
|
||||
.dev = {
|
||||
.platform_data = ixp2000_serial_port,
|
||||
},
|
||||
.num_resources = 1,
|
||||
.resource = &ixp2000_uart_resource,
|
||||
};
|
||||
|
||||
void __init ixp2000_uart_init(void)
|
||||
{
|
||||
platform_device_register(&ixp2000_serial_device);
|
||||
}
|
||||
|
||||
|
||||
/*************************************************************************
|
||||
* Timer-tick functions for IXP2000
|
||||
*************************************************************************/
|
||||
static unsigned ticks_per_jiffy;
|
||||
static unsigned ticks_per_usec;
|
||||
static unsigned next_jiffy_time;
|
||||
static volatile unsigned long *missing_jiffy_timer_csr;
|
||||
|
||||
unsigned long ixp2000_gettimeoffset (void)
|
||||
{
|
||||
unsigned long offset;
|
||||
|
||||
offset = next_jiffy_time - *missing_jiffy_timer_csr;
|
||||
|
||||
return offset / ticks_per_usec;
|
||||
}
|
||||
|
||||
static irqreturn_t ixp2000_timer_interrupt(int irq, void *dev_id)
|
||||
{
|
||||
/* clear timer 1 */
|
||||
ixp2000_reg_wrb(IXP2000_T1_CLR, 1);
|
||||
|
||||
while ((signed long)(next_jiffy_time - *missing_jiffy_timer_csr)
|
||||
>= ticks_per_jiffy) {
|
||||
timer_tick();
|
||||
next_jiffy_time -= ticks_per_jiffy;
|
||||
}
|
||||
|
||||
return IRQ_HANDLED;
|
||||
}
|
||||
|
||||
static struct irqaction ixp2000_timer_irq = {
|
||||
.name = "IXP2000 Timer Tick",
|
||||
.flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
|
||||
.handler = ixp2000_timer_interrupt,
|
||||
};
|
||||
|
||||
void __init ixp2000_init_time(unsigned long tick_rate)
|
||||
{
|
||||
ticks_per_jiffy = (tick_rate + HZ/2) / HZ;
|
||||
ticks_per_usec = tick_rate / 1000000;
|
||||
|
||||
/*
|
||||
* We use timer 1 as our timer interrupt.
|
||||
*/
|
||||
ixp2000_reg_write(IXP2000_T1_CLR, 0);
|
||||
ixp2000_reg_write(IXP2000_T1_CLD, ticks_per_jiffy - 1);
|
||||
ixp2000_reg_write(IXP2000_T1_CTL, (1 << 7));
|
||||
|
||||
/*
|
||||
* We use a second timer as a monotonic counter for tracking
|
||||
* missed jiffies. The IXP2000 has four timers, but if we're
|
||||
* on an A-step IXP2800, timer 2 and 3 don't work, so on those
|
||||
* chips we use timer 4. Timer 4 is the only timer that can
|
||||
* be used for the watchdog, so we use timer 2 if we're on a
|
||||
* non-buggy chip.
|
||||
*/
|
||||
if ((*IXP2000_PRODUCT_ID & 0x001ffef0) == 0x00000000) {
|
||||
printk(KERN_INFO "Enabling IXP2800 erratum #25 workaround\n");
|
||||
|
||||
ixp2000_reg_write(IXP2000_T4_CLR, 0);
|
||||
ixp2000_reg_write(IXP2000_T4_CLD, -1);
|
||||
ixp2000_reg_wrb(IXP2000_T4_CTL, (1 << 7));
|
||||
missing_jiffy_timer_csr = IXP2000_T4_CSR;
|
||||
} else {
|
||||
ixp2000_reg_write(IXP2000_T2_CLR, 0);
|
||||
ixp2000_reg_write(IXP2000_T2_CLD, -1);
|
||||
ixp2000_reg_wrb(IXP2000_T2_CTL, (1 << 7));
|
||||
missing_jiffy_timer_csr = IXP2000_T2_CSR;
|
||||
}
|
||||
next_jiffy_time = 0xffffffff;
|
||||
|
||||
/* register for interrupt */
|
||||
setup_irq(IRQ_IXP2000_TIMER1, &ixp2000_timer_irq);
|
||||
}
|
||||
|
||||
/*************************************************************************
|
||||
* GPIO helpers
|
||||
*************************************************************************/
|
||||
static unsigned long GPIO_IRQ_falling_edge;
|
||||
static unsigned long GPIO_IRQ_rising_edge;
|
||||
static unsigned long GPIO_IRQ_level_low;
|
||||
static unsigned long GPIO_IRQ_level_high;
|
||||
|
||||
static void update_gpio_int_csrs(void)
|
||||
{
|
||||
ixp2000_reg_write(IXP2000_GPIO_FEDR, GPIO_IRQ_falling_edge);
|
||||
ixp2000_reg_write(IXP2000_GPIO_REDR, GPIO_IRQ_rising_edge);
|
||||
ixp2000_reg_write(IXP2000_GPIO_LSLR, GPIO_IRQ_level_low);
|
||||
ixp2000_reg_wrb(IXP2000_GPIO_LSHR, GPIO_IRQ_level_high);
|
||||
}
|
||||
|
||||
void gpio_line_config(int line, int direction)
|
||||
{
|
||||
unsigned long flags;
|
||||
|
||||
local_irq_save(flags);
|
||||
if (direction == GPIO_OUT) {
|
||||
/* if it's an output, it ain't an interrupt anymore */
|
||||
GPIO_IRQ_falling_edge &= ~(1 << line);
|
||||
GPIO_IRQ_rising_edge &= ~(1 << line);
|
||||
GPIO_IRQ_level_low &= ~(1 << line);
|
||||
GPIO_IRQ_level_high &= ~(1 << line);
|
||||
update_gpio_int_csrs();
|
||||
|
||||
ixp2000_reg_wrb(IXP2000_GPIO_PDSR, 1 << line);
|
||||
} else if (direction == GPIO_IN) {
|
||||
ixp2000_reg_wrb(IXP2000_GPIO_PDCR, 1 << line);
|
||||
}
|
||||
local_irq_restore(flags);
|
||||
}
|
||||
EXPORT_SYMBOL(gpio_line_config);
|
||||
|
||||
|
||||
/*************************************************************************
|
||||
* IRQ handling IXP2000
|
||||
*************************************************************************/
|
||||
static void ixp2000_GPIO_irq_handler(unsigned int irq, struct irq_desc *desc)
|
||||
{
|
||||
int i;
|
||||
unsigned long status = *IXP2000_GPIO_INST;
|
||||
|
||||
for (i = 0; i <= 7; i++) {
|
||||
if (status & (1<<i)) {
|
||||
generic_handle_irq(i + IRQ_IXP2000_GPIO0);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
static int ixp2000_GPIO_irq_type(struct irq_data *d, unsigned int type)
|
||||
{
|
||||
int line = d->irq - IRQ_IXP2000_GPIO0;
|
||||
|
||||
/*
|
||||
* First, configure this GPIO line as an input.
|
||||
*/
|
||||
ixp2000_reg_write(IXP2000_GPIO_PDCR, 1 << line);
|
||||
|
||||
/*
|
||||
* Then, set the proper trigger type.
|
||||
*/
|
||||
if (type & IRQ_TYPE_EDGE_FALLING)
|
||||
GPIO_IRQ_falling_edge |= 1 << line;
|
||||
else
|
||||
GPIO_IRQ_falling_edge &= ~(1 << line);
|
||||
if (type & IRQ_TYPE_EDGE_RISING)
|
||||
GPIO_IRQ_rising_edge |= 1 << line;
|
||||
else
|
||||
GPIO_IRQ_rising_edge &= ~(1 << line);
|
||||
if (type & IRQ_TYPE_LEVEL_LOW)
|
||||
GPIO_IRQ_level_low |= 1 << line;
|
||||
else
|
||||
GPIO_IRQ_level_low &= ~(1 << line);
|
||||
if (type & IRQ_TYPE_LEVEL_HIGH)
|
||||
GPIO_IRQ_level_high |= 1 << line;
|
||||
else
|
||||
GPIO_IRQ_level_high &= ~(1 << line);
|
||||
update_gpio_int_csrs();
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void ixp2000_GPIO_irq_mask_ack(struct irq_data *d)
|
||||
{
|
||||
unsigned int irq = d->irq;
|
||||
|
||||
ixp2000_reg_write(IXP2000_GPIO_INCR, (1 << (irq - IRQ_IXP2000_GPIO0)));
|
||||
|
||||
ixp2000_reg_write(IXP2000_GPIO_EDSR, (1 << (irq - IRQ_IXP2000_GPIO0)));
|
||||
ixp2000_reg_write(IXP2000_GPIO_LDSR, (1 << (irq - IRQ_IXP2000_GPIO0)));
|
||||
ixp2000_reg_wrb(IXP2000_GPIO_INST, (1 << (irq - IRQ_IXP2000_GPIO0)));
|
||||
}
|
||||
|
||||
static void ixp2000_GPIO_irq_mask(struct irq_data *d)
|
||||
{
|
||||
unsigned int irq = d->irq;
|
||||
|
||||
ixp2000_reg_wrb(IXP2000_GPIO_INCR, (1 << (irq - IRQ_IXP2000_GPIO0)));
|
||||
}
|
||||
|
||||
static void ixp2000_GPIO_irq_unmask(struct irq_data *d)
|
||||
{
|
||||
unsigned int irq = d->irq;
|
||||
|
||||
ixp2000_reg_write(IXP2000_GPIO_INSR, (1 << (irq - IRQ_IXP2000_GPIO0)));
|
||||
}
|
||||
|
||||
static struct irq_chip ixp2000_GPIO_irq_chip = {
|
||||
.irq_ack = ixp2000_GPIO_irq_mask_ack,
|
||||
.irq_mask = ixp2000_GPIO_irq_mask,
|
||||
.irq_unmask = ixp2000_GPIO_irq_unmask,
|
||||
.irq_set_type = ixp2000_GPIO_irq_type,
|
||||
};
|
||||
|
||||
static void ixp2000_pci_irq_mask(struct irq_data *d)
|
||||
{
|
||||
unsigned long temp = *IXP2000_PCI_XSCALE_INT_ENABLE;
|
||||
if (d->irq == IRQ_IXP2000_PCIA)
|
||||
ixp2000_reg_wrb(IXP2000_PCI_XSCALE_INT_ENABLE, (temp & ~(1 << 26)));
|
||||
else if (d->irq == IRQ_IXP2000_PCIB)
|
||||
ixp2000_reg_wrb(IXP2000_PCI_XSCALE_INT_ENABLE, (temp & ~(1 << 27)));
|
||||
}
|
||||
|
||||
static void ixp2000_pci_irq_unmask(struct irq_data *d)
|
||||
{
|
||||
unsigned long temp = *IXP2000_PCI_XSCALE_INT_ENABLE;
|
||||
if (d->irq == IRQ_IXP2000_PCIA)
|
||||
ixp2000_reg_write(IXP2000_PCI_XSCALE_INT_ENABLE, (temp | (1 << 26)));
|
||||
else if (d->irq == IRQ_IXP2000_PCIB)
|
||||
ixp2000_reg_write(IXP2000_PCI_XSCALE_INT_ENABLE, (temp | (1 << 27)));
|
||||
}
|
||||
|
||||
/*
|
||||
* Error interrupts. These are used extensively by the microengine drivers
|
||||
*/
|
||||
static void ixp2000_err_irq_handler(unsigned int irq, struct irq_desc *desc)
|
||||
{
|
||||
int i;
|
||||
unsigned long status = *IXP2000_IRQ_ERR_STATUS;
|
||||
|
||||
for(i = 31; i >= 0; i--) {
|
||||
if(status & (1 << i)) {
|
||||
generic_handle_irq(IRQ_IXP2000_DRAM0_MIN_ERR + i);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
static void ixp2000_err_irq_mask(struct irq_data *d)
|
||||
{
|
||||
ixp2000_reg_write(IXP2000_IRQ_ERR_ENABLE_CLR,
|
||||
(1 << (d->irq - IRQ_IXP2000_DRAM0_MIN_ERR)));
|
||||
}
|
||||
|
||||
static void ixp2000_err_irq_unmask(struct irq_data *d)
|
||||
{
|
||||
ixp2000_reg_write(IXP2000_IRQ_ERR_ENABLE_SET,
|
||||
(1 << (d->irq - IRQ_IXP2000_DRAM0_MIN_ERR)));
|
||||
}
|
||||
|
||||
static struct irq_chip ixp2000_err_irq_chip = {
|
||||
.irq_ack = ixp2000_err_irq_mask,
|
||||
.irq_mask = ixp2000_err_irq_mask,
|
||||
.irq_unmask = ixp2000_err_irq_unmask
|
||||
};
|
||||
|
||||
static struct irq_chip ixp2000_pci_irq_chip = {
|
||||
.irq_ack = ixp2000_pci_irq_mask,
|
||||
.irq_mask = ixp2000_pci_irq_mask,
|
||||
.irq_unmask = ixp2000_pci_irq_unmask
|
||||
};
|
||||
|
||||
static void ixp2000_irq_mask(struct irq_data *d)
|
||||
{
|
||||
ixp2000_reg_wrb(IXP2000_IRQ_ENABLE_CLR, (1 << d->irq));
|
||||
}
|
||||
|
||||
static void ixp2000_irq_unmask(struct irq_data *d)
|
||||
{
|
||||
ixp2000_reg_write(IXP2000_IRQ_ENABLE_SET, (1 << d->irq));
|
||||
}
|
||||
|
||||
static struct irq_chip ixp2000_irq_chip = {
|
||||
.irq_ack = ixp2000_irq_mask,
|
||||
.irq_mask = ixp2000_irq_mask,
|
||||
.irq_unmask = ixp2000_irq_unmask
|
||||
};
|
||||
|
||||
void __init ixp2000_init_irq(void)
|
||||
{
|
||||
int irq;
|
||||
|
||||
/*
|
||||
* Mask all sources
|
||||
*/
|
||||
ixp2000_reg_write(IXP2000_IRQ_ENABLE_CLR, 0xffffffff);
|
||||
ixp2000_reg_write(IXP2000_FIQ_ENABLE_CLR, 0xffffffff);
|
||||
|
||||
/* clear all GPIO edge/level detects */
|
||||
ixp2000_reg_write(IXP2000_GPIO_REDR, 0);
|
||||
ixp2000_reg_write(IXP2000_GPIO_FEDR, 0);
|
||||
ixp2000_reg_write(IXP2000_GPIO_LSHR, 0);
|
||||
ixp2000_reg_write(IXP2000_GPIO_LSLR, 0);
|
||||
ixp2000_reg_write(IXP2000_GPIO_INCR, -1);
|
||||
|
||||
/* clear PCI interrupt sources */
|
||||
ixp2000_reg_wrb(IXP2000_PCI_XSCALE_INT_ENABLE, 0);
|
||||
|
||||
/*
|
||||
* Certain bits in the IRQ status register of the
|
||||
* IXP2000 are reserved. Instead of trying to map
|
||||
* things non 1:1 from bit position to IRQ number,
|
||||
* we mark the reserved IRQs as invalid. This makes
|
||||
* our mask/unmask code much simpler.
|
||||
*/
|
||||
for (irq = IRQ_IXP2000_SOFT_INT; irq <= IRQ_IXP2000_THDB3; irq++) {
|
||||
if ((1 << irq) & IXP2000_VALID_IRQ_MASK) {
|
||||
irq_set_chip_and_handler(irq, &ixp2000_irq_chip,
|
||||
handle_level_irq);
|
||||
set_irq_flags(irq, IRQF_VALID);
|
||||
} else set_irq_flags(irq, 0);
|
||||
}
|
||||
|
||||
for (irq = IRQ_IXP2000_DRAM0_MIN_ERR; irq <= IRQ_IXP2000_SP_INT; irq++) {
|
||||
if((1 << (irq - IRQ_IXP2000_DRAM0_MIN_ERR)) &
|
||||
IXP2000_VALID_ERR_IRQ_MASK) {
|
||||
irq_set_chip_and_handler(irq, &ixp2000_err_irq_chip,
|
||||
handle_level_irq);
|
||||
set_irq_flags(irq, IRQF_VALID);
|
||||
}
|
||||
else
|
||||
set_irq_flags(irq, 0);
|
||||
}
|
||||
irq_set_chained_handler(IRQ_IXP2000_ERRSUM, ixp2000_err_irq_handler);
|
||||
|
||||
for (irq = IRQ_IXP2000_GPIO0; irq <= IRQ_IXP2000_GPIO7; irq++) {
|
||||
irq_set_chip_and_handler(irq, &ixp2000_GPIO_irq_chip,
|
||||
handle_level_irq);
|
||||
set_irq_flags(irq, IRQF_VALID);
|
||||
}
|
||||
irq_set_chained_handler(IRQ_IXP2000_GPIO, ixp2000_GPIO_irq_handler);
|
||||
|
||||
/*
|
||||
* Enable PCI irqs. The actual PCI[AB] decoding is done in
|
||||
* entry-macro.S, so we don't need a chained handler for the
|
||||
* PCI interrupt source.
|
||||
*/
|
||||
ixp2000_reg_write(IXP2000_IRQ_ENABLE_SET, (1 << IRQ_IXP2000_PCI));
|
||||
for (irq = IRQ_IXP2000_PCIA; irq <= IRQ_IXP2000_PCIB; irq++) {
|
||||
irq_set_chip_and_handler(irq, &ixp2000_pci_irq_chip,
|
||||
handle_level_irq);
|
||||
set_irq_flags(irq, IRQF_VALID);
|
||||
}
|
||||
}
|
||||
|
||||
void ixp2000_restart(char mode, const char *cmd)
|
||||
{
|
||||
ixp2000_reg_wrb(IXP2000_RESET0, RSTALL);
|
||||
}
|
||||
|
|
@ -1,265 +0,0 @@
|
|||
/*
|
||||
* arch/arm/mach-ixp2000/enp2611.c
|
||||
*
|
||||
* Radisys ENP-2611 support.
|
||||
*
|
||||
* Created 2004 by Lennert Buytenhek from the ixdp2x01 code. The
|
||||
* original version carries the following notices:
|
||||
*
|
||||
* Original Author: Andrzej Mialkowski <andrzej.mialkowski@intel.com>
|
||||
* Maintainer: Deepak Saxena <dsaxena@plexity.net>
|
||||
*
|
||||
* Copyright (C) 2002-2003 Intel Corp.
|
||||
* Copyright (C) 2003-2004 MontaVista Software, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of the GNU General Public License as published by the
|
||||
* Free Software Foundation; either version 2 of the License, or (at your
|
||||
* option) any later version.
|
||||
*/
|
||||
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/mm.h>
|
||||
#include <linux/sched.h>
|
||||
#include <linux/interrupt.h>
|
||||
#include <linux/bitops.h>
|
||||
#include <linux/pci.h>
|
||||
#include <linux/ioport.h>
|
||||
#include <linux/delay.h>
|
||||
#include <linux/serial.h>
|
||||
#include <linux/tty.h>
|
||||
#include <linux/serial_core.h>
|
||||
#include <linux/platform_device.h>
|
||||
#include <linux/io.h>
|
||||
|
||||
#include <asm/irq.h>
|
||||
#include <asm/pgtable.h>
|
||||
#include <asm/page.h>
|
||||
#include <mach/hardware.h>
|
||||
#include <asm/mach-types.h>
|
||||
|
||||
#include <asm/mach/pci.h>
|
||||
#include <asm/mach/map.h>
|
||||
#include <asm/mach/irq.h>
|
||||
#include <asm/mach/time.h>
|
||||
#include <asm/mach/arch.h>
|
||||
#include <asm/mach/flash.h>
|
||||
|
||||
/*************************************************************************
|
||||
* ENP-2611 timer tick configuration
|
||||
*************************************************************************/
|
||||
static void __init enp2611_timer_init(void)
|
||||
{
|
||||
ixp2000_init_time(50 * 1000 * 1000);
|
||||
}
|
||||
|
||||
static struct sys_timer enp2611_timer = {
|
||||
.init = enp2611_timer_init,
|
||||
.offset = ixp2000_gettimeoffset,
|
||||
};
|
||||
|
||||
|
||||
/*************************************************************************
|
||||
* ENP-2611 I/O
|
||||
*************************************************************************/
|
||||
static struct map_desc enp2611_io_desc[] __initdata = {
|
||||
{
|
||||
.virtual = ENP2611_CALEB_VIRT_BASE,
|
||||
.pfn = __phys_to_pfn(ENP2611_CALEB_PHYS_BASE),
|
||||
.length = ENP2611_CALEB_SIZE,
|
||||
.type = MT_DEVICE,
|
||||
}, {
|
||||
.virtual = ENP2611_PM3386_0_VIRT_BASE,
|
||||
.pfn = __phys_to_pfn(ENP2611_PM3386_0_PHYS_BASE),
|
||||
.length = ENP2611_PM3386_0_SIZE,
|
||||
.type = MT_DEVICE,
|
||||
}, {
|
||||
.virtual = ENP2611_PM3386_1_VIRT_BASE,
|
||||
.pfn = __phys_to_pfn(ENP2611_PM3386_1_PHYS_BASE),
|
||||
.length = ENP2611_PM3386_1_SIZE,
|
||||
.type = MT_DEVICE,
|
||||
}
|
||||
};
|
||||
|
||||
void __init enp2611_map_io(void)
|
||||
{
|
||||
ixp2000_map_io();
|
||||
iotable_init(enp2611_io_desc, ARRAY_SIZE(enp2611_io_desc));
|
||||
}
|
||||
|
||||
|
||||
/*************************************************************************
|
||||
* ENP-2611 PCI
|
||||
*************************************************************************/
|
||||
static int enp2611_pci_setup(int nr, struct pci_sys_data *sys)
|
||||
{
|
||||
sys->mem_offset = 0xe0000000;
|
||||
ixp2000_pci_setup(nr, sys);
|
||||
return 1;
|
||||
}
|
||||
|
||||
static void __init enp2611_pci_preinit(void)
|
||||
{
|
||||
ixp2000_reg_write(IXP2000_PCI_ADDR_EXT, 0x00100000);
|
||||
ixp2000_pci_preinit();
|
||||
pcibios_setup("firmware");
|
||||
}
|
||||
|
||||
static inline int enp2611_pci_valid_device(struct pci_bus *bus,
|
||||
unsigned int devfn)
|
||||
{
|
||||
/* The 82559 ethernet controller appears at both PCI:1:0:0 and
|
||||
* PCI:1:2:0, so let's pretend the second one isn't there.
|
||||
*/
|
||||
if (bus->number == 0x01 && devfn == 0x10)
|
||||
return 0;
|
||||
|
||||
return 1;
|
||||
}
|
||||
|
||||
static int enp2611_pci_read_config(struct pci_bus *bus, unsigned int devfn,
|
||||
int where, int size, u32 *value)
|
||||
{
|
||||
if (enp2611_pci_valid_device(bus, devfn))
|
||||
return ixp2000_pci_read_config(bus, devfn, where, size, value);
|
||||
|
||||
return PCIBIOS_DEVICE_NOT_FOUND;
|
||||
}
|
||||
|
||||
static int enp2611_pci_write_config(struct pci_bus *bus, unsigned int devfn,
|
||||
int where, int size, u32 value)
|
||||
{
|
||||
if (enp2611_pci_valid_device(bus, devfn))
|
||||
return ixp2000_pci_write_config(bus, devfn, where, size, value);
|
||||
|
||||
return PCIBIOS_DEVICE_NOT_FOUND;
|
||||
}
|
||||
|
||||
static struct pci_ops enp2611_pci_ops = {
|
||||
.read = enp2611_pci_read_config,
|
||||
.write = enp2611_pci_write_config
|
||||
};
|
||||
|
||||
static struct pci_bus * __init enp2611_pci_scan_bus(int nr,
|
||||
struct pci_sys_data *sys)
|
||||
{
|
||||
return pci_scan_root_bus(NULL, sys->busnr, &enp2611_pci_ops, sys,
|
||||
&sys->resources);
|
||||
}
|
||||
|
||||
static int __init enp2611_pci_map_irq(const struct pci_dev *dev, u8 slot,
|
||||
u8 pin)
|
||||
{
|
||||
int irq;
|
||||
|
||||
if (dev->bus->number == 0 && PCI_SLOT(dev->devfn) == 0) {
|
||||
/* IXP2400. */
|
||||
irq = IRQ_IXP2000_PCIA;
|
||||
} else if (dev->bus->number == 0 && PCI_SLOT(dev->devfn) == 1) {
|
||||
/* 21555 non-transparent bridge. */
|
||||
irq = IRQ_IXP2000_PCIB;
|
||||
} else if (dev->bus->number == 0 && PCI_SLOT(dev->devfn) == 4) {
|
||||
/* PCI2050B transparent bridge. */
|
||||
irq = -1;
|
||||
} else if (dev->bus->number == 1 && PCI_SLOT(dev->devfn) == 0) {
|
||||
/* 82559 ethernet. */
|
||||
irq = IRQ_IXP2000_PCIA;
|
||||
} else if (dev->bus->number == 1 && PCI_SLOT(dev->devfn) == 1) {
|
||||
/* SPI-3 option board. */
|
||||
irq = IRQ_IXP2000_PCIB;
|
||||
} else {
|
||||
printk(KERN_ERR "enp2611_pci_map_irq() called for unknown "
|
||||
"device PCI:%d:%d:%d\n", dev->bus->number,
|
||||
PCI_SLOT(dev->devfn), PCI_FUNC(dev->devfn));
|
||||
irq = -1;
|
||||
}
|
||||
|
||||
return irq;
|
||||
}
|
||||
|
||||
struct hw_pci enp2611_pci __initdata = {
|
||||
.nr_controllers = 1,
|
||||
.setup = enp2611_pci_setup,
|
||||
.preinit = enp2611_pci_preinit,
|
||||
.scan = enp2611_pci_scan_bus,
|
||||
.map_irq = enp2611_pci_map_irq,
|
||||
};
|
||||
|
||||
int __init enp2611_pci_init(void)
|
||||
{
|
||||
if (machine_is_enp2611())
|
||||
pci_common_init(&enp2611_pci);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
subsys_initcall(enp2611_pci_init);
|
||||
|
||||
|
||||
/*************************************************************************
|
||||
* ENP-2611 Machine Initialization
|
||||
*************************************************************************/
|
||||
static struct flash_platform_data enp2611_flash_platform_data = {
|
||||
.map_name = "cfi_probe",
|
||||
.width = 1,
|
||||
};
|
||||
|
||||
static struct ixp2000_flash_data enp2611_flash_data = {
|
||||
.platform_data = &enp2611_flash_platform_data,
|
||||
.nr_banks = 1
|
||||
};
|
||||
|
||||
static struct resource enp2611_flash_resource = {
|
||||
.start = 0xc4000000,
|
||||
.end = 0xc4000000 + 0x00ffffff,
|
||||
.flags = IORESOURCE_MEM,
|
||||
};
|
||||
|
||||
static struct platform_device enp2611_flash = {
|
||||
.name = "IXP2000-Flash",
|
||||
.id = 0,
|
||||
.dev = {
|
||||
.platform_data = &enp2611_flash_data,
|
||||
},
|
||||
.num_resources = 1,
|
||||
.resource = &enp2611_flash_resource,
|
||||
};
|
||||
|
||||
static struct ixp2000_i2c_pins enp2611_i2c_gpio_pins = {
|
||||
.sda_pin = ENP2611_GPIO_SDA,
|
||||
.scl_pin = ENP2611_GPIO_SCL,
|
||||
};
|
||||
|
||||
static struct platform_device enp2611_i2c_controller = {
|
||||
.name = "IXP2000-I2C",
|
||||
.id = 0,
|
||||
.dev = {
|
||||
.platform_data = &enp2611_i2c_gpio_pins
|
||||
},
|
||||
.num_resources = 0
|
||||
};
|
||||
|
||||
static struct platform_device *enp2611_devices[] __initdata = {
|
||||
&enp2611_flash,
|
||||
&enp2611_i2c_controller
|
||||
};
|
||||
|
||||
static void __init enp2611_init_machine(void)
|
||||
{
|
||||
platform_add_devices(enp2611_devices, ARRAY_SIZE(enp2611_devices));
|
||||
ixp2000_uart_init();
|
||||
}
|
||||
|
||||
|
||||
MACHINE_START(ENP2611, "Radisys ENP-2611 PCI network processor board")
|
||||
/* Maintainer: Lennert Buytenhek <buytenh@wantstofly.org> */
|
||||
.atag_offset = 0x100,
|
||||
.map_io = enp2611_map_io,
|
||||
.init_irq = ixp2000_init_irq,
|
||||
.timer = &enp2611_timer,
|
||||
.init_machine = enp2611_init_machine,
|
||||
.restart = ixp2000_restart,
|
||||
MACHINE_END
|
||||
|
||||
|
||||
|
|
@ -1,25 +0,0 @@
|
|||
/* arch/arm/mach-ixp2000/include/mach/debug-macro.S
|
||||
*
|
||||
* Debugging macro include header
|
||||
*
|
||||
* Copyright (C) 1994-1999 Russell King
|
||||
* Moved from linux/arch/arm/kernel/debug.S by Ben Dooks
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
*/
|
||||
|
||||
.macro addruart, rp, rv, tmp
|
||||
mov \rp, #0x00030000
|
||||
#ifdef __ARMEB__
|
||||
orr \rp, \rp, #0x00000003
|
||||
#endif
|
||||
orr \rv, \rp, #0xfe000000 @ virtual base
|
||||
orr \rv, \rv, #0x00f00000
|
||||
orr \rp, \rp, #0xc0000000 @ Physical base
|
||||
.endm
|
||||
|
||||
#define UART_SHIFT 2
|
||||
#include <asm/hardware/debug-8250.S>
|
||||
|
|
@ -1,46 +0,0 @@
|
|||
/*
|
||||
* arch/arm/mach-ixp2000/include/mach/enp2611.h
|
||||
*
|
||||
* Register and other defines for Radisys ENP-2611
|
||||
*
|
||||
* Created 2004 by Lennert Buytenhek from the ixdp2x01 code. The
|
||||
* original version carries the following notices:
|
||||
*
|
||||
* Original Author: Naeem Afzal <naeem.m.afzal@intel.com>
|
||||
* Maintainer: Deepak Saxena <dsaxena@plexity.net>
|
||||
*
|
||||
* Copyright (C) 2002 Intel Corp.
|
||||
* Copyright (C) 2003-2004 MontaVista Software, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of the GNU General Public License as published by the
|
||||
* Free Software Foundation; either version 2 of the License, or (at your
|
||||
* option) any later version.
|
||||
*/
|
||||
|
||||
#ifndef __ENP2611_H
|
||||
#define __ENP2611_H
|
||||
|
||||
#define ENP2611_CALEB_PHYS_BASE 0xc5000000
|
||||
#define ENP2611_CALEB_VIRT_BASE 0xfe000000
|
||||
#define ENP2611_CALEB_SIZE 0x00100000
|
||||
|
||||
#define ENP2611_PM3386_0_PHYS_BASE 0xc6000000
|
||||
#define ENP2611_PM3386_0_VIRT_BASE 0xfe100000
|
||||
#define ENP2611_PM3386_0_SIZE 0x00100000
|
||||
|
||||
#define ENP2611_PM3386_1_PHYS_BASE 0xc6400000
|
||||
#define ENP2611_PM3386_1_VIRT_BASE 0xfe200000
|
||||
#define ENP2611_PM3386_1_SIZE 0x00100000
|
||||
|
||||
#define ENP2611_GPIO_SCL 7
|
||||
#define ENP2611_GPIO_SDA 6
|
||||
|
||||
#define IRQ_ENP2611_THERMAL IRQ_IXP2000_GPIO4
|
||||
#define IRQ_ENP2611_OPTION_BOARD IRQ_IXP2000_GPIO3
|
||||
#define IRQ_ENP2611_CALEB IRQ_IXP2000_GPIO2
|
||||
#define IRQ_ENP2611_PM3386_1 IRQ_IXP2000_GPIO1
|
||||
#define IRQ_ENP2611_PM3386_0 IRQ_IXP2000_GPIO0
|
||||
|
||||
|
||||
#endif
|
||||
|
|
@ -1,54 +0,0 @@
|
|||
/*
|
||||
* arch/arm/mach-ixp2000/include/mach/entry-macro.S
|
||||
*
|
||||
* Low-level IRQ helper macros for IXP2000-based platforms
|
||||
*
|
||||
* This file is licensed under the terms of the GNU General Public
|
||||
* License version 2. This program is licensed "as is" without any
|
||||
* warranty of any kind, whether express or implied.
|
||||
*/
|
||||
#include <mach/irqs.h>
|
||||
|
||||
.macro get_irqnr_preamble, base, tmp
|
||||
.endm
|
||||
|
||||
.macro get_irqnr_and_base, irqnr, irqstat, base, tmp
|
||||
|
||||
mov \irqnr, #0x0 @clear out irqnr as default
|
||||
mov \base, #0xfe000000
|
||||
orr \base, \base, #0x00e00000
|
||||
orr \base, \base, #0x08
|
||||
ldr \irqstat, [\base] @ get interrupts
|
||||
|
||||
cmp \irqstat, #0
|
||||
beq 1001f
|
||||
|
||||
clz \irqnr, \irqstat
|
||||
mov \base, #31
|
||||
subs \irqnr, \base, \irqnr
|
||||
|
||||
/*
|
||||
* We handle PCIA and PCIB here so we don't have an
|
||||
* extra layer of code just to check these two bits.
|
||||
*/
|
||||
cmp \irqnr, #IRQ_IXP2000_PCI
|
||||
bne 1001f
|
||||
|
||||
mov \base, #0xfe000000
|
||||
orr \base, \base, #0x00c00000
|
||||
orr \base, \base, #0x00000100
|
||||
orr \base, \base, #0x00000058
|
||||
ldr \irqstat, [\base]
|
||||
|
||||
mov \tmp, #(1<<26)
|
||||
tst \irqstat, \tmp
|
||||
movne \irqnr, #IRQ_IXP2000_PCIA
|
||||
bne 1001f
|
||||
|
||||
mov \tmp, #(1<<27)
|
||||
tst \irqstat, \tmp
|
||||
movne \irqnr, #IRQ_IXP2000_PCIB
|
||||
|
||||
1001:
|
||||
.endm
|
||||
|
||||
|
|
@ -1,48 +0,0 @@
|
|||
/*
|
||||
* arch/arm/mach-ixp2000/include/mach/gpio.h
|
||||
*
|
||||
* Copyright (C) 2002 Intel Corporation.
|
||||
*
|
||||
* This program is free software, you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
/*
|
||||
* IXP2000 GPIO in/out, edge/level detection for IRQs:
|
||||
* IRQs are generated on Falling-edge, Rising-Edge, Level-low, Level-High
|
||||
* or both Falling-edge and Rising-edge.
|
||||
* This must be called *before* the corresponding IRQ is registerd.
|
||||
* Use this instead of directly setting the GPIO registers.
|
||||
* GPIOs may also be used as GPIOs (e.g. for emulating i2c/smb)
|
||||
*/
|
||||
#ifndef __ASM_ARCH_GPIO_H
|
||||
#define __ASM_ARCH_GPIO_H
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
|
||||
#define GPIO_IN 0
|
||||
#define GPIO_OUT 1
|
||||
|
||||
#define IXP2000_GPIO_LOW 0
|
||||
#define IXP2000_GPIO_HIGH 1
|
||||
|
||||
extern void gpio_line_config(int line, int direction);
|
||||
|
||||
static inline int gpio_line_get(int line)
|
||||
{
|
||||
return (((*IXP2000_GPIO_PLR) >> line) & 1);
|
||||
}
|
||||
|
||||
static inline void gpio_line_set(int line, int value)
|
||||
{
|
||||
if (value == IXP2000_GPIO_HIGH) {
|
||||
ixp2000_reg_write(IXP2000_GPIO_POSR, 1 << line);
|
||||
} else if (value == IXP2000_GPIO_LOW) {
|
||||
ixp2000_reg_write(IXP2000_GPIO_POCR, 1 << line);
|
||||
}
|
||||
}
|
||||
|
||||
#endif /* !__ASSEMBLY__ */
|
||||
|
||||
#endif /* ASM_ARCH_IXP2000_GPIO_H_ */
|
||||
Some files were not shown because too many files have changed in this diff Show more
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Reference in a new issue