Merge branch 'next' of git://git.kernel.org/pub/scm/linux/kernel/git/benh/powerpc
Pull powerpc updates from Ben Herrenschmidt: "Here is the bulk of the powerpc changes for this merge window. It got a bit delayed in part because I wasn't paying attention, and in part because I discovered I had a core PCI change without a PCI maintainer ack in it. Bjorn eventually agreed it was ok to merge it though we'll probably improve it later and I didn't want to rebase to add his ack. There is going to be a bit more next week, essentially fixes that I still want to sort through and test. The biggest item this time is the support to build the ppc64 LE kernel with our new v2 ABI. We previously supported v2 userspace but the kernel itself was a tougher nut to crack. This is now sorted mostly thanks to Anton and Rusty. We also have a fairly big series from Cedric that add support for 64-bit LE zImage boot wrapper. This was made harder by the fact that traditionally our zImage wrapper was always 32-bit, but our new LE toolchains don't really support 32-bit anymore (it's somewhat there but not really "supported") so we didn't want to rely on it. This meant more churn that just endian fixes. This brings some more LE bits as well, such as the ability to run in LE mode without a hypervisor (ie. under OPAL firmware) by doing the right OPAL call to reinitialize the CPU to take HV interrupts in the right mode and the usual pile of endian fixes. There's another series from Gavin adding EEH improvements (one day we *will* have a release with less than 20 EEH patches, I promise!). Another highlight is the support for the "Split core" functionality on P8 by Michael. This allows a P8 core to be split into "sub cores" of 4 threads which allows the subcores to run different guests under KVM (the HW still doesn't support a partition per thread). And then the usual misc bits and fixes ..." [ Further delayed by gmail deciding that BenH is a dirty spammer. Google knows. ] * 'next' of git://git.kernel.org/pub/scm/linux/kernel/git/benh/powerpc: (155 commits) powerpc/powernv: Add missing include to LPC code selftests/powerpc: Test the THP bug we fixed in the previous commit powerpc/mm: Check paca psize is up to date for huge mappings powerpc/powernv: Pass buffer size to OPAL validate flash call powerpc/pseries: hcall functions are exported to modules, need _GLOBAL_TOC() powerpc: Exported functions __clear_user and copy_page use r2 so need _GLOBAL_TOC() powerpc/powernv: Set memory_block_size_bytes to 256MB powerpc: Allow ppc_md platform hook to override memory_block_size_bytes powerpc/powernv: Fix endian issues in memory error handling code powerpc/eeh: Skip eeh sysfs when eeh is disabled powerpc: 64bit sendfile is capped at 2GB powerpc/powernv: Provide debugfs access to the LPC bus via OPAL powerpc/serial: Use saner flags when creating legacy ports powerpc: Add cpu family documentation powerpc/xmon: Fix up xmon format strings powerpc/powernv: Add calls to support little endian host powerpc: Document sysfs DSCR interface powerpc: Fix regression of per-CPU DSCR setting powerpc: Split __SYSFS_SPRSETUP macro arch: powerpc/fadump: Cleaning up inconsistent NULL checks ...
This commit is contained in:
Linus Torvalds
commit
c5aec4c76a
205 changed files with 6897 additions and 1772 deletions
25
Documentation/ABI/stable/sysfs-devices-system-cpu
Normal file
25
Documentation/ABI/stable/sysfs-devices-system-cpu
Normal file
|
|
@ -0,0 +1,25 @@
|
|||
What: /sys/devices/system/cpu/dscr_default
|
||||
Date: 13-May-2014
|
||||
KernelVersion: v3.15.0
|
||||
Contact:
|
||||
Description: Writes are equivalent to writing to
|
||||
/sys/devices/system/cpu/cpuN/dscr on all CPUs.
|
||||
Reads return the last written value or 0.
|
||||
This value is not a global default: it is a way to set
|
||||
all per-CPU defaults at the same time.
|
||||
Values: 64 bit unsigned integer (bit field)
|
||||
|
||||
What: /sys/devices/system/cpu/cpu[0-9]+/dscr
|
||||
Date: 13-May-2014
|
||||
KernelVersion: v3.15.0
|
||||
Contact:
|
||||
Description: Default value for the Data Stream Control Register (DSCR) on
|
||||
a CPU.
|
||||
This default value is used when the kernel is executing and
|
||||
for any process that has not set the DSCR itself.
|
||||
If a process ever sets the DSCR (via direct access to the
|
||||
SPR) that value will be persisted for that process and used
|
||||
on any CPU where it executes (overriding the value described
|
||||
here).
|
||||
If set by a process it will be inherited by child processes.
|
||||
Values: 64 bit unsigned integer (bit field)
|
||||
142
Documentation/devicetree/bindings/clock/qoriq-clock.txt
Normal file
142
Documentation/devicetree/bindings/clock/qoriq-clock.txt
Normal file
|
|
@ -0,0 +1,142 @@
|
|||
* Clock Block on Freescale CoreNet Platforms
|
||||
|
||||
Freescale CoreNet chips take primary clocking input from the external
|
||||
SYSCLK signal. The SYSCLK input (frequency) is multiplied using
|
||||
multiple phase locked loops (PLL) to create a variety of frequencies
|
||||
which can then be passed to a variety of internal logic, including
|
||||
cores and peripheral IP blocks.
|
||||
Please refer to the Reference Manual for details.
|
||||
|
||||
All references to "1.0" and "2.0" refer to the QorIQ chassis version to
|
||||
which the chip complies.
|
||||
|
||||
Chassis Version Example Chips
|
||||
--------------- -------------
|
||||
1.0 p4080, p5020, p5040
|
||||
2.0 t4240, b4860, t1040
|
||||
|
||||
1. Clock Block Binding
|
||||
|
||||
Required properties:
|
||||
- compatible: Should contain a specific clock block compatible string
|
||||
and a single chassis clock compatible string.
|
||||
Clock block strings include, but not limited to, one of the:
|
||||
* "fsl,p2041-clockgen"
|
||||
* "fsl,p3041-clockgen"
|
||||
* "fsl,p4080-clockgen"
|
||||
* "fsl,p5020-clockgen"
|
||||
* "fsl,p5040-clockgen"
|
||||
* "fsl,t4240-clockgen"
|
||||
* "fsl,b4420-clockgen"
|
||||
* "fsl,b4860-clockgen"
|
||||
Chassis clock strings include:
|
||||
* "fsl,qoriq-clockgen-1.0": for chassis 1.0 clocks
|
||||
* "fsl,qoriq-clockgen-2.0": for chassis 2.0 clocks
|
||||
- reg: Describes the address of the device's resources within the
|
||||
address space defined by its parent bus, and resource zero
|
||||
represents the clock register set
|
||||
- clock-frequency: Input system clock frequency
|
||||
|
||||
Recommended properties:
|
||||
- ranges: Allows valid translation between child's address space and
|
||||
parent's. Must be present if the device has sub-nodes.
|
||||
- #address-cells: Specifies the number of cells used to represent
|
||||
physical base addresses. Must be present if the device has
|
||||
sub-nodes and set to 1 if present
|
||||
- #size-cells: Specifies the number of cells used to represent
|
||||
the size of an address. Must be present if the device has
|
||||
sub-nodes and set to 1 if present
|
||||
|
||||
2. Clock Provider/Consumer Binding
|
||||
|
||||
Most of the bindings are from the common clock binding[1].
|
||||
[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
|
||||
|
||||
Required properties:
|
||||
- compatible : Should include one of the following:
|
||||
* "fsl,qoriq-core-pll-1.0" for core PLL clocks (v1.0)
|
||||
* "fsl,qoriq-core-pll-2.0" for core PLL clocks (v2.0)
|
||||
* "fsl,qoriq-core-mux-1.0" for core mux clocks (v1.0)
|
||||
* "fsl,qoriq-core-mux-2.0" for core mux clocks (v2.0)
|
||||
* "fsl,qoriq-sysclk-1.0": for input system clock (v1.0).
|
||||
It takes parent's clock-frequency as its clock.
|
||||
* "fsl,qoriq-sysclk-2.0": for input system clock (v2.0).
|
||||
It takes parent's clock-frequency as its clock.
|
||||
- #clock-cells: From common clock binding. The number of cells in a
|
||||
clock-specifier. Should be <0> for "fsl,qoriq-sysclk-[1,2].0"
|
||||
clocks, or <1> for "fsl,qoriq-core-pll-[1,2].0" clocks.
|
||||
For "fsl,qoriq-core-pll-[1,2].0" clocks, the single
|
||||
clock-specifier cell may take the following values:
|
||||
* 0 - equal to the PLL frequency
|
||||
* 1 - equal to the PLL frequency divided by 2
|
||||
* 2 - equal to the PLL frequency divided by 4
|
||||
|
||||
Recommended properties:
|
||||
- clocks: Should be the phandle of input parent clock
|
||||
- clock-names: From common clock binding, indicates the clock name
|
||||
- clock-output-names: From common clock binding, indicates the names of
|
||||
output clocks
|
||||
- reg: Should be the offset and length of clock block base address.
|
||||
The length should be 4.
|
||||
|
||||
Example for clock block and clock provider:
|
||||
/ {
|
||||
clockgen: global-utilities@e1000 {
|
||||
compatible = "fsl,p5020-clockgen", "fsl,qoriq-clockgen-1.0";
|
||||
ranges = <0x0 0xe1000 0x1000>;
|
||||
clock-frequency = <133333333>;
|
||||
reg = <0xe1000 0x1000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
sysclk: sysclk {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fsl,qoriq-sysclk-1.0";
|
||||
clock-output-names = "sysclk";
|
||||
};
|
||||
|
||||
pll0: pll0@800 {
|
||||
#clock-cells = <1>;
|
||||
reg = <0x800 0x4>;
|
||||
compatible = "fsl,qoriq-core-pll-1.0";
|
||||
clocks = <&sysclk>;
|
||||
clock-output-names = "pll0", "pll0-div2";
|
||||
};
|
||||
|
||||
pll1: pll1@820 {
|
||||
#clock-cells = <1>;
|
||||
reg = <0x820 0x4>;
|
||||
compatible = "fsl,qoriq-core-pll-1.0";
|
||||
clocks = <&sysclk>;
|
||||
clock-output-names = "pll1", "pll1-div2";
|
||||
};
|
||||
|
||||
mux0: mux0@0 {
|
||||
#clock-cells = <0>;
|
||||
reg = <0x0 0x4>;
|
||||
compatible = "fsl,qoriq-core-mux-1.0";
|
||||
clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
|
||||
clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2";
|
||||
clock-output-names = "cmux0";
|
||||
};
|
||||
|
||||
mux1: mux1@20 {
|
||||
#clock-cells = <0>;
|
||||
reg = <0x20 0x4>;
|
||||
compatible = "fsl,qoriq-core-mux-1.0";
|
||||
clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
|
||||
clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2";
|
||||
clock-output-names = "cmux1";
|
||||
};
|
||||
};
|
||||
}
|
||||
|
||||
Example for clock consumer:
|
||||
|
||||
/ {
|
||||
cpu0: PowerPC,e5500@0 {
|
||||
...
|
||||
clocks = <&mux0>;
|
||||
...
|
||||
};
|
||||
}
|
||||
25
Documentation/devicetree/bindings/mfd/bfticu.txt
Normal file
25
Documentation/devicetree/bindings/mfd/bfticu.txt
Normal file
|
|
@ -0,0 +1,25 @@
|
|||
KEYMILE bfticu Chassis Management FPGA
|
||||
|
||||
The bfticu is a multifunction device that manages the whole chassis.
|
||||
Its main functionality is to collect IRQs from the whole chassis and signals
|
||||
them to a single controller.
|
||||
|
||||
Required properties:
|
||||
- compatible: "keymile,bfticu"
|
||||
- interrupt-controller: the bfticu FPGA is an interrupt controller
|
||||
- interrupts: the main IRQ line to signal the collected IRQs
|
||||
- #interrupt-cells : is 2 and their usage is compliant to the 2 cells variant
|
||||
of Documentation/devicetree/bindings/interrupt-controller/interrupts.txt
|
||||
- interrupt-parent: the parent IRQ ctrl the main IRQ is connected to
|
||||
- reg: access on the parent local bus (chip select, offset in chip select, size)
|
||||
|
||||
Example:
|
||||
|
||||
chassis-mgmt@3,0 {
|
||||
compatible = "keymile,bfticu";
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
reg = <3 0 0x100>;
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <6 1 0 0>;
|
||||
};
|
||||
17
Documentation/devicetree/bindings/mfd/qriox.txt
Normal file
17
Documentation/devicetree/bindings/mfd/qriox.txt
Normal file
|
|
@ -0,0 +1,17 @@
|
|||
KEYMILE qrio Board Control CPLD
|
||||
|
||||
The qrio is a multifunction device that controls the KEYMILE boards based on
|
||||
the kmp204x design.
|
||||
It is consists of a reset controller, watchdog timer, LEDs, and 2 IRQ capable
|
||||
GPIO blocks.
|
||||
|
||||
Required properties:
|
||||
- compatible: "keymile,qriox"
|
||||
- reg: access on the parent local bus (chip select, offset in chip select, size)
|
||||
|
||||
Example:
|
||||
|
||||
board-control@1,0 {
|
||||
compatible = "keymile,qriox";
|
||||
reg = <1 0 0x80>;
|
||||
};
|
||||
54
Documentation/devicetree/bindings/powerpc/4xx/akebono.txt
Normal file
54
Documentation/devicetree/bindings/powerpc/4xx/akebono.txt
Normal file
|
|
@ -0,0 +1,54 @@
|
|||
|
||||
IBM Akebono board device tree
|
||||
=============================
|
||||
|
||||
The IBM Akebono board is a development board for the PPC476GTR SoC.
|
||||
|
||||
0) The root node
|
||||
|
||||
Required properties:
|
||||
|
||||
- model : "ibm,akebono".
|
||||
- compatible : "ibm,akebono" , "ibm,476gtr".
|
||||
|
||||
1.a) The Secure Digital Host Controller Interface (SDHCI) node
|
||||
|
||||
Represent the Secure Digital Host Controller Interfaces.
|
||||
|
||||
Required properties:
|
||||
|
||||
- compatible : should be "ibm,476gtr-sdhci","generic-sdhci".
|
||||
- reg : should contain the SDHCI registers location and length.
|
||||
- interrupt-parent : a phandle for the interrupt controller.
|
||||
- interrupts : should contain the SDHCI interrupt.
|
||||
|
||||
1.b) The Advanced Host Controller Interface (AHCI) SATA node
|
||||
|
||||
Represents the advanced host controller SATA interface.
|
||||
|
||||
Required properties:
|
||||
|
||||
- compatible : should be "ibm,476gtr-ahci".
|
||||
- reg : should contain the AHCI registers location and length.
|
||||
- interrupt-parent : a phandle for the interrupt controller.
|
||||
- interrupts : should contain the AHCI interrupt.
|
||||
|
||||
1.c) The FPGA node
|
||||
|
||||
The Akebono board stores some board information such as the revision
|
||||
number in an FPGA which is represented by this node.
|
||||
|
||||
Required properties:
|
||||
|
||||
- compatible : should be "ibm,akebono-fpga".
|
||||
- reg : should contain the FPGA registers location and length.
|
||||
|
||||
1.d) The AVR node
|
||||
|
||||
The Akebono board has an Atmel AVR microprocessor attached to the I2C
|
||||
bus as a power controller for the board.
|
||||
|
||||
Required properties:
|
||||
|
||||
- compatible : should be "ibm,akebono-avr".
|
||||
- reg : should contain the I2C bus address for the AVR.
|
||||
19
Documentation/devicetree/bindings/powerpc/4xx/hsta.txt
Normal file
19
Documentation/devicetree/bindings/powerpc/4xx/hsta.txt
Normal file
|
|
@ -0,0 +1,19 @@
|
|||
|
||||
ppc476gtr High Speed Serial Assist (HSTA) node
|
||||
==============================================
|
||||
|
||||
The 476gtr SoC contains a high speed serial assist module attached
|
||||
between the plb4 and plb6 system buses to provide high speed data
|
||||
transfer between memory and system peripherals as well as support for
|
||||
PCI message signalled interrupts.
|
||||
|
||||
Currently only the MSI support is used by Linux using the following
|
||||
device tree entries:
|
||||
|
||||
Require properties:
|
||||
- compatible : "ibm,476gtr-hsta-msi", "ibm,hsta-msi"
|
||||
- reg : register mapping for the HSTA MSI space
|
||||
- interrupt-parent : parent controller for mapping interrupts
|
||||
- interrupts : ordered interrupt mapping for each MSI in the register
|
||||
space. The first interrupt should be associated with a
|
||||
register offset of 0x00, the second to 0x10, etc.
|
||||
|
|
@ -67,3 +67,20 @@ Example:
|
|||
gpio-controller;
|
||||
};
|
||||
};
|
||||
|
||||
* Freescale on-board FPGA connected on I2C bus
|
||||
|
||||
Some Freescale boards like BSC9132QDS have on board FPGA connected on
|
||||
the i2c bus.
|
||||
|
||||
Required properties:
|
||||
- compatible: Should be a board-specific string followed by a string
|
||||
indicating the type of FPGA. Example:
|
||||
"fsl,<board>-fpga", "fsl,fpga-qixis-i2c"
|
||||
- reg: Should contain the address of the FPGA
|
||||
|
||||
Example:
|
||||
fpga: fpga@66 {
|
||||
compatible = "fsl,bsc9132qds-fpga", "fsl,fpga-qixis-i2c";
|
||||
reg = <0x66>;
|
||||
};
|
||||
|
|
|
|||
46
Documentation/devicetree/bindings/powerpc/fsl/ccf.txt
Normal file
46
Documentation/devicetree/bindings/powerpc/fsl/ccf.txt
Normal file
|
|
@ -0,0 +1,46 @@
|
|||
Freescale CoreNet Coherency Fabric(CCF) Device Tree Binding
|
||||
|
||||
DESCRIPTION
|
||||
|
||||
The CoreNet coherency fabric is a fabric-oriented, connectivity infrastructure
|
||||
that enables the implementation of coherent, multicore systems.
|
||||
|
||||
Required properties:
|
||||
|
||||
- compatible: <string list>
|
||||
fsl,corenet1-cf - CoreNet coherency fabric version 1.
|
||||
Example chips: T4240, B4860
|
||||
|
||||
fsl,corenet2-cf - CoreNet coherency fabric version 2.
|
||||
Example chips: P5040, P5020, P4080, P3041, P2041
|
||||
|
||||
fsl,corenet-cf - Used to represent the common registers
|
||||
between CCF version 1 and CCF version 2. This compatible
|
||||
is retained for compatibility reasons, as it was already
|
||||
used for both CCF version 1 chips and CCF version 2
|
||||
chips. It should be specified after either
|
||||
"fsl,corenet1-cf" or "fsl,corenet2-cf".
|
||||
|
||||
- reg: <prop-encoded-array>
|
||||
A standard property. Represents the CCF registers.
|
||||
|
||||
- interrupts: <prop-encoded-array>
|
||||
Interrupt mapping for CCF error interrupt.
|
||||
|
||||
- fsl,ccf-num-csdids: <u32>
|
||||
Specifies the number of Coherency Subdomain ID Port Mapping
|
||||
Registers that are supported by the CCF.
|
||||
|
||||
- fsl,ccf-num-snoopids: <u32>
|
||||
Specifies the number of Snoop ID Port Mapping Registers that
|
||||
are supported by CCF.
|
||||
|
||||
Example:
|
||||
|
||||
corenet-cf@18000 {
|
||||
compatible = "fsl,corenet2-cf", "fsl,corenet-cf";
|
||||
reg = <0x18000 0x1000>;
|
||||
interrupts = <16 2 1 31>;
|
||||
fsl,ccf-num-csdids = <32>;
|
||||
fsl,ccf-num-snoopids = <32>;
|
||||
};
|
||||
|
|
@ -20,3 +20,14 @@ PROPERTIES
|
|||
a property named fsl,eref-[CAT], where [CAT] is the abbreviated category
|
||||
name with all uppercase letters converted to lowercase, indicates that
|
||||
the category is supported by the implementation.
|
||||
|
||||
- fsl,portid-mapping
|
||||
Usage: optional
|
||||
Value type: <u32>
|
||||
Definition: The Coherency Subdomain ID Port Mapping Registers and
|
||||
Snoop ID Port Mapping registers, which are part of the CoreNet
|
||||
Coherency fabric (CCF), provide a CoreNet Coherency Subdomain
|
||||
ID/CoreNet Snoop ID to cpu mapping functions. Certain bits from
|
||||
these registers should be set if the coresponding CPU should be
|
||||
snooped. This property defines a bitmask which selects the bit
|
||||
that should be set if this cpu should be snooped.
|
||||
|
|
|
|||
|
|
@ -34,6 +34,15 @@ Optional properties:
|
|||
for legacy drivers.
|
||||
- interrupt-parent : <phandle>
|
||||
Phandle to interrupt controller
|
||||
- fsl,portid-mapping : <u32>
|
||||
The Coherency Subdomain ID Port Mapping Registers and
|
||||
Snoop ID Port Mapping registers, which are part of the
|
||||
CoreNet Coherency fabric (CCF), provide a CoreNet
|
||||
Coherency Subdomain ID/CoreNet Snoop ID to pamu mapping
|
||||
functions. Certain bits from these registers should be
|
||||
set if PAMUs should be snooped. This property defines
|
||||
a bitmask which selects the bits that should be set if
|
||||
PAMUs should be snooped.
|
||||
|
||||
Child nodes:
|
||||
|
||||
|
|
@ -88,6 +97,7 @@ Example:
|
|||
compatible = "fsl,pamu-v1.0", "fsl,pamu";
|
||||
reg = <0x20000 0x5000>;
|
||||
ranges = <0 0x20000 0x5000>;
|
||||
fsl,portid-mapping = <0xf80000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
interrupts = <
|
||||
|
|
|
|||
|
|
@ -142,3 +142,4 @@ wm Wondermedia Technologies, Inc.
|
|||
xes Extreme Engineering Solutions (X-ES)
|
||||
xlnx Xilinx
|
||||
zyxel ZyXEL Communications Corp.
|
||||
zarlink Zarlink Semiconductor
|
||||
|
|
|
|||
221
Documentation/powerpc/cpu_families.txt
Normal file
221
Documentation/powerpc/cpu_families.txt
Normal file
|
|
@ -0,0 +1,221 @@
|
|||
CPU Families
|
||||
============
|
||||
|
||||
This document tries to summarise some of the different cpu families that exist
|
||||
and are supported by arch/powerpc.
|
||||
|
||||
|
||||
Book3S (aka sPAPR)
|
||||
------------------
|
||||
|
||||
- Hash MMU
|
||||
- Mix of 32 & 64 bit
|
||||
|
||||
+--------------+ +----------------+
|
||||
| Old POWER | --------------> | RS64 (threads) |
|
||||
+--------------+ +----------------+
|
||||
|
|
||||
|
|
||||
v
|
||||
+--------------+ +----------------+ +------+
|
||||
| 601 | --------------> | 603 | ---> | e300 |
|
||||
+--------------+ +----------------+ +------+
|
||||
| |
|
||||
| |
|
||||
v v
|
||||
+--------------+ +----------------+ +-------+
|
||||
| 604 | | 750 (G3) | ---> | 750CX |
|
||||
+--------------+ +----------------+ +-------+
|
||||
| | |
|
||||
| | |
|
||||
v v v
|
||||
+--------------+ +----------------+ +-------+
|
||||
| 620 (64 bit) | | 7400 | | 750CL |
|
||||
+--------------+ +----------------+ +-------+
|
||||
| | |
|
||||
| | |
|
||||
v v v
|
||||
+--------------+ +----------------+ +-------+
|
||||
| POWER3/630 | | 7410 | | 750FX |
|
||||
+--------------+ +----------------+ +-------+
|
||||
| |
|
||||
| |
|
||||
v v
|
||||
+--------------+ +----------------+
|
||||
| POWER3+ | | 7450 |
|
||||
+--------------+ +----------------+
|
||||
| |
|
||||
| |
|
||||
v v
|
||||
+--------------+ +----------------+
|
||||
| POWER4 | | 7455 |
|
||||
+--------------+ +----------------+
|
||||
| |
|
||||
| |
|
||||
v v
|
||||
+--------------+ +-------+ +----------------+
|
||||
| POWER4+ | --> | 970 | | 7447 |
|
||||
+--------------+ +-------+ +----------------+
|
||||
| | |
|
||||
| | |
|
||||
v v v
|
||||
+--------------+ +-------+ +----------------+
|
||||
| POWER5 | | 970FX | | 7448 |
|
||||
+--------------+ +-------+ +----------------+
|
||||
| | |
|
||||
| | |
|
||||
v v v
|
||||
+--------------+ +-------+ +----------------+
|
||||
| POWER5+ | | 970MP | | e600 |
|
||||
+--------------+ +-------+ +----------------+
|
||||
|
|
||||
|
|
||||
v
|
||||
+--------------+
|
||||
| POWER5++ |
|
||||
+--------------+
|
||||
|
|
||||
|
|
||||
v
|
||||
+--------------+ +-------+
|
||||
| POWER6 | <-?-> | Cell |
|
||||
+--------------+ +-------+
|
||||
|
|
||||
|
|
||||
v
|
||||
+--------------+
|
||||
| POWER7 |
|
||||
+--------------+
|
||||
|
|
||||
|
|
||||
v
|
||||
+--------------+
|
||||
| POWER7+ |
|
||||
+--------------+
|
||||
|
|
||||
|
|
||||
v
|
||||
+--------------+
|
||||
| POWER8 |
|
||||
+--------------+
|
||||
|
||||
|
||||
+---------------+
|
||||
| PA6T (64 bit) |
|
||||
+---------------+
|
||||
|
||||
|
||||
IBM BookE
|
||||
---------
|
||||
|
||||
- Software loaded TLB.
|
||||
- All 32 bit
|
||||
|
||||
+--------------+
|
||||
| 401 |
|
||||
+--------------+
|
||||
|
|
||||
|
|
||||
v
|
||||
+--------------+
|
||||
| 403 |
|
||||
+--------------+
|
||||
|
|
||||
|
|
||||
v
|
||||
+--------------+
|
||||
| 405 |
|
||||
+--------------+
|
||||
|
|
||||
|
|
||||
v
|
||||
+--------------+
|
||||
| 440 |
|
||||
+--------------+
|
||||
|
|
||||
|
|
||||
v
|
||||
+--------------+ +----------------+
|
||||
| 450 | --> | BG/P |
|
||||
+--------------+ +----------------+
|
||||
|
|
||||
|
|
||||
v
|
||||
+--------------+
|
||||
| 460 |
|
||||
+--------------+
|
||||
|
|
||||
|
|
||||
v
|
||||
+--------------+
|
||||
| 476 |
|
||||
+--------------+
|
||||
|
||||
|
||||
Motorola/Freescale 8xx
|
||||
----------------------
|
||||
|
||||
- Software loaded with hardware assist.
|
||||
- All 32 bit
|
||||
|
||||
+-------------+
|
||||
| MPC8xx Core |
|
||||
+-------------+
|
||||
|
||||
|
||||
Freescale BookE
|
||||
---------------
|
||||
|
||||
- Software loaded TLB.
|
||||
- e6500 adds HW loaded indirect TLB entries.
|
||||
- Mix of 32 & 64 bit
|
||||
|
||||
+--------------+
|
||||
| e200 |
|
||||
+--------------+
|
||||
|
||||
|
||||
+--------------------------------+
|
||||
| e500 |
|
||||
+--------------------------------+
|
||||
|
|
||||
|
|
||||
v
|
||||
+--------------------------------+
|
||||
| e500v2 |
|
||||
+--------------------------------+
|
||||
|
|
||||
|
|
||||
v
|
||||
+--------------------------------+
|
||||
| e500mc (Book3e) |
|
||||
+--------------------------------+
|
||||
|
|
||||
|
|
||||
v
|
||||
+--------------------------------+
|
||||
| e5500 (64 bit) |
|
||||
+--------------------------------+
|
||||
|
|
||||
|
|
||||
v
|
||||
+--------------------------------+
|
||||
| e6500 (HW TLB) (Multithreaded) |
|
||||
+--------------------------------+
|
||||
|
||||
|
||||
IBM A2 core
|
||||
-----------
|
||||
|
||||
- Book3E, software loaded TLB + HW loaded indirect TLB entries.
|
||||
- 64 bit
|
||||
|
||||
+--------------+ +----------------+
|
||||
| A2 core | --> | WSP |
|
||||
+--------------+ +----------------+
|
||||
|
|
||||
|
|
||||
v
|
||||
+--------------+
|
||||
| BG/Q |
|
||||
+--------------+
|
||||
|
|
@ -453,6 +453,14 @@ config NODES_SHIFT
|
|||
default "4"
|
||||
depends on NEED_MULTIPLE_NODES
|
||||
|
||||
config USE_PERCPU_NUMA_NODE_ID
|
||||
def_bool y
|
||||
depends on NUMA
|
||||
|
||||
config HAVE_MEMORYLESS_NODES
|
||||
def_bool y
|
||||
depends on NUMA
|
||||
|
||||
config ARCH_SELECT_MEMORY_MODEL
|
||||
def_bool y
|
||||
depends on PPC64
|
||||
|
|
|
|||
|
|
@ -113,8 +113,13 @@ else
|
|||
endif
|
||||
endif
|
||||
|
||||
CFLAGS-$(CONFIG_PPC64) := -mtraceback=no -mcall-aixdesc
|
||||
CFLAGS-$(CONFIG_PPC64) += $(call cc-option,-mabi=elfv1)
|
||||
CFLAGS-$(CONFIG_PPC64) := -mtraceback=no
|
||||
ifeq ($(CONFIG_CPU_LITTLE_ENDIAN),y)
|
||||
CFLAGS-$(CONFIG_PPC64) += $(call cc-option,-mabi=elfv2,-mcall-aixdesc)
|
||||
AFLAGS-$(CONFIG_PPC64) += $(call cc-option,-mabi=elfv2)
|
||||
else
|
||||
CFLAGS-$(CONFIG_PPC64) += -mcall-aixdesc
|
||||
endif
|
||||
CFLAGS-$(CONFIG_PPC64) += $(call cc-option,-mcmodel=medium,-mminimal-toc)
|
||||
CFLAGS-$(CONFIG_PPC64) += $(call cc-option,-mno-pointers-to-nested-functions)
|
||||
CFLAGS-$(CONFIG_PPC32) := -ffixed-r2 $(MULTIPLEWORD)
|
||||
|
|
@ -153,7 +158,7 @@ CFLAGS-$(CONFIG_TUNE_CELL) += $(call cc-option,-mtune=cell)
|
|||
asinstr := $(call as-instr,lis 9$(comma)foo@high,-DHAVE_AS_ATHIGH=1)
|
||||
|
||||
KBUILD_CPPFLAGS += -Iarch/$(ARCH) $(asinstr)
|
||||
KBUILD_AFLAGS += -Iarch/$(ARCH)
|
||||
KBUILD_AFLAGS += -Iarch/$(ARCH) $(AFLAGS-y)
|
||||
KBUILD_CFLAGS += -msoft-float -pipe -Iarch/$(ARCH) $(CFLAGS-y)
|
||||
CPP = $(CC) -E $(KBUILD_CFLAGS)
|
||||
|
||||
|
|
@ -161,6 +166,11 @@ CHECKFLAGS += -m$(CONFIG_WORD_SIZE) -D__powerpc__ -D__powerpc$(CONFIG_WORD_SIZE)
|
|||
|
||||
KBUILD_LDFLAGS_MODULE += arch/powerpc/lib/crtsavres.o
|
||||
|
||||
ifeq ($(CONFIG_476FPE_ERR46),y)
|
||||
KBUILD_LDFLAGS_MODULE += --ppc476-workaround \
|
||||
-T $(srctree)/arch/powerpc/platforms/44x/ppc476_modules.lds
|
||||
endif
|
||||
|
||||
# No AltiVec or VSX instructions when building kernel
|
||||
KBUILD_CFLAGS += $(call cc-option,-mno-altivec)
|
||||
KBUILD_CFLAGS += $(call cc-option,-mno-vsx)
|
||||
|
|
|
|||
|
|
@ -22,8 +22,14 @@ all: $(obj)/zImage
|
|||
BOOTCFLAGS := -Wall -Wundef -Wstrict-prototypes -Wno-trigraphs \
|
||||
-fno-strict-aliasing -Os -msoft-float -pipe \
|
||||
-fomit-frame-pointer -fno-builtin -fPIC -nostdinc \
|
||||
-isystem $(shell $(CROSS32CC) -print-file-name=include) \
|
||||
-mbig-endian
|
||||
-isystem $(shell $(CROSS32CC) -print-file-name=include)
|
||||
ifdef CONFIG_PPC64_BOOT_WRAPPER
|
||||
BOOTCFLAGS += -m64
|
||||
endif
|
||||
ifdef CONFIG_CPU_BIG_ENDIAN
|
||||
BOOTCFLAGS += -mbig-endian
|
||||
endif
|
||||
|
||||
BOOTAFLAGS := -D__ASSEMBLY__ $(BOOTCFLAGS) -traditional -nostdinc
|
||||
|
||||
ifdef CONFIG_DEBUG_INFO
|
||||
|
|
@ -47,6 +53,7 @@ $(obj)/cuboot-acadia.o: BOOTCFLAGS += -mcpu=405
|
|||
$(obj)/treeboot-walnut.o: BOOTCFLAGS += -mcpu=405
|
||||
$(obj)/treeboot-iss4xx.o: BOOTCFLAGS += -mcpu=405
|
||||
$(obj)/treeboot-currituck.o: BOOTCFLAGS += -mcpu=405
|
||||
$(obj)/treeboot-akebono.o: BOOTCFLAGS += -mcpu=405
|
||||
$(obj)/virtex405-head.o: BOOTAFLAGS += -mcpu=405
|
||||
|
||||
|
||||
|
|
@ -86,6 +93,7 @@ src-plat-$(CONFIG_44x) += treeboot-ebony.c cuboot-ebony.c treeboot-bamboo.c \
|
|||
cuboot-taishan.c cuboot-katmai.c \
|
||||
cuboot-warp.c cuboot-yosemite.c \
|
||||
treeboot-iss4xx.c treeboot-currituck.c \
|
||||
treeboot-akebono.c \
|
||||
simpleboot.c fixed-head.S virtex.c
|
||||
src-plat-$(CONFIG_8xx) += cuboot-8xx.c fixed-head.S ep88xc.c redboot-8xx.c
|
||||
src-plat-$(CONFIG_PPC_MPC52xx) += cuboot-52xx.c
|
||||
|
|
@ -99,6 +107,11 @@ src-plat-$(CONFIG_EMBEDDED6xx) += cuboot-pq2.c cuboot-mpc7448hpc2.c \
|
|||
src-plat-$(CONFIG_AMIGAONE) += cuboot-amigaone.c
|
||||
src-plat-$(CONFIG_PPC_PS3) += ps3-head.S ps3-hvcall.S ps3.c
|
||||
src-plat-$(CONFIG_EPAPR_BOOT) += epapr.c epapr-wrapper.c
|
||||
src-plat-$(CONFIG_PPC_PSERIES) += pseries-head.S
|
||||
src-plat-$(CONFIG_PPC_POWERNV) += pseries-head.S
|
||||
src-plat-$(CONFIG_PPC_IBM_CELL_BLADE) += pseries-head.S
|
||||
src-plat-$(CONFIG_PPC_CELLEB) += pseries-head.S
|
||||
src-plat-$(CONFIG_PPC_CELL_QPACE) += pseries-head.S
|
||||
|
||||
src-wlib := $(sort $(src-wlib-y))
|
||||
src-plat := $(sort $(src-plat-y))
|
||||
|
|
@ -137,7 +150,11 @@ $(addprefix $(obj)/,$(libfdt) $(libfdtheader)): $(obj)/%: $(srctree)/scripts/dtc
|
|||
$(obj)/empty.c:
|
||||
@touch $@
|
||||
|
||||
$(obj)/zImage.lds $(obj)/zImage.coff.lds $(obj)/zImage.ps3.lds: $(obj)/%: $(srctree)/$(src)/%.S
|
||||
$(obj)/zImage.lds: $(obj)/%: $(srctree)/$(src)/%.S
|
||||
$(CROSS32CC) $(cpp_flags) -E -Wp,-MD,$(depfile) -P -Upowerpc \
|
||||
-D__ASSEMBLY__ -DLINKER_SCRIPT -o $@ $<
|
||||
|
||||
$(obj)/zImage.coff.lds $(obj)/zImage.ps3.lds : $(obj)/%: $(srctree)/$(src)/%.S
|
||||
@cp $< $@
|
||||
|
||||
clean-files := $(zlib) $(zlibheader) $(zliblinuxheader) \
|
||||
|
|
@ -235,6 +252,7 @@ image-$(CONFIG_YOSEMITE) += cuImage.yosemite
|
|||
image-$(CONFIG_ISS4xx) += treeImage.iss4xx \
|
||||
treeImage.iss4xx-mpic
|
||||
image-$(CONFIG_CURRITUCK) += treeImage.currituck
|
||||
image-$(CONFIG_AKEBONO) += treeImage.akebono
|
||||
|
||||
# Board ports in arch/powerpc/platform/8xx/Kconfig
|
||||
image-$(CONFIG_MPC86XADS) += cuImage.mpc866ads
|
||||
|
|
|
|||
|
|
@ -6,6 +6,8 @@
|
|||
*
|
||||
* Copyright 2000 Paul Mackerras.
|
||||
*
|
||||
* Adapted for 64 bit little endian images by Andrew Tauferner.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License
|
||||
* as published by the Free Software Foundation; either version
|
||||
|
|
@ -55,36 +57,61 @@ unsigned int rpanote[N_RPA_DESCR] = {
|
|||
|
||||
#define ROUNDUP(len) (((len) + 3) & ~3)
|
||||
|
||||
unsigned char buf[512];
|
||||
unsigned char buf[1024];
|
||||
#define ELFDATA2LSB 1
|
||||
#define ELFDATA2MSB 2
|
||||
static int e_data = ELFDATA2MSB;
|
||||
#define ELFCLASS32 1
|
||||
#define ELFCLASS64 2
|
||||
static int e_class = ELFCLASS32;
|
||||
|
||||
#define GET_16BE(off) ((buf[off] << 8) + (buf[(off)+1]))
|
||||
#define GET_32BE(off) ((GET_16BE(off) << 16) + GET_16BE((off)+2))
|
||||
#define GET_32BE(off) ((GET_16BE(off) << 16U) + GET_16BE((off)+2U))
|
||||
#define GET_64BE(off) ((((unsigned long long)GET_32BE(off)) << 32ULL) + \
|
||||
((unsigned long long)GET_32BE((off)+4ULL)))
|
||||
#define PUT_16BE(off, v)(buf[off] = ((v) >> 8) & 0xff, \
|
||||
buf[(off) + 1] = (v) & 0xff)
|
||||
#define PUT_32BE(off, v)(PUT_16BE((off), (v) >> 16L), PUT_16BE((off) + 2, (v)))
|
||||
#define PUT_64BE(off, v)((PUT_32BE((off), (v) >> 32L), \
|
||||
PUT_32BE((off) + 4, (v))))
|
||||
|
||||
#define PUT_16BE(off, v) (buf[off] = ((v) >> 8) & 0xff, \
|
||||
buf[(off) + 1] = (v) & 0xff)
|
||||
#define PUT_32BE(off, v) (PUT_16BE((off), (v) >> 16), \
|
||||
PUT_16BE((off) + 2, (v)))
|
||||
#define GET_16LE(off) ((buf[off]) + (buf[(off)+1] << 8))
|
||||
#define GET_32LE(off) (GET_16LE(off) + (GET_16LE((off)+2U) << 16U))
|
||||
#define GET_64LE(off) ((unsigned long long)GET_32LE(off) + \
|
||||
(((unsigned long long)GET_32LE((off)+4ULL)) << 32ULL))
|
||||
#define PUT_16LE(off, v) (buf[off] = (v) & 0xff, \
|
||||
buf[(off) + 1] = ((v) >> 8) & 0xff)
|
||||
#define PUT_32LE(off, v) (PUT_16LE((off), (v)), PUT_16LE((off) + 2, (v) >> 16L))
|
||||
#define PUT_64LE(off, v) (PUT_32LE((off), (v)), PUT_32LE((off) + 4, (v) >> 32L))
|
||||
|
||||
#define GET_16(off) (e_data == ELFDATA2MSB ? GET_16BE(off) : GET_16LE(off))
|
||||
#define GET_32(off) (e_data == ELFDATA2MSB ? GET_32BE(off) : GET_32LE(off))
|
||||
#define GET_64(off) (e_data == ELFDATA2MSB ? GET_64BE(off) : GET_64LE(off))
|
||||
#define PUT_16(off, v) (e_data == ELFDATA2MSB ? PUT_16BE(off, v) : \
|
||||
PUT_16LE(off, v))
|
||||
#define PUT_32(off, v) (e_data == ELFDATA2MSB ? PUT_32BE(off, v) : \
|
||||
PUT_32LE(off, v))
|
||||
#define PUT_64(off, v) (e_data == ELFDATA2MSB ? PUT_64BE(off, v) : \
|
||||
PUT_64LE(off, v))
|
||||
|
||||
/* Structure of an ELF file */
|
||||
#define E_IDENT 0 /* ELF header */
|
||||
#define E_PHOFF 28
|
||||
#define E_PHENTSIZE 42
|
||||
#define E_PHNUM 44
|
||||
#define E_HSIZE 52 /* size of ELF header */
|
||||
#define E_PHOFF (e_class == ELFCLASS32 ? 28 : 32)
|
||||
#define E_PHENTSIZE (e_class == ELFCLASS32 ? 42 : 54)
|
||||
#define E_PHNUM (e_class == ELFCLASS32 ? 44 : 56)
|
||||
#define E_HSIZE (e_class == ELFCLASS32 ? 52 : 64)
|
||||
|
||||
#define EI_MAGIC 0 /* offsets in E_IDENT area */
|
||||
#define EI_CLASS 4
|
||||
#define EI_DATA 5
|
||||
|
||||
#define PH_TYPE 0 /* ELF program header */
|
||||
#define PH_OFFSET 4
|
||||
#define PH_FILESZ 16
|
||||
#define PH_HSIZE 32 /* size of program header */
|
||||
#define PH_OFFSET (e_class == ELFCLASS32 ? 4 : 8)
|
||||
#define PH_FILESZ (e_class == ELFCLASS32 ? 16 : 32)
|
||||
#define PH_HSIZE (e_class == ELFCLASS32 ? 32 : 56)
|
||||
|
||||
#define PT_NOTE 4 /* Program header type = note */
|
||||
|
||||
#define ELFCLASS32 1
|
||||
#define ELFDATA2MSB 2
|
||||
|
||||
unsigned char elf_magic[4] = { 0x7f, 'E', 'L', 'F' };
|
||||
|
||||
|
|
@ -92,8 +119,8 @@ int
|
|||
main(int ac, char **av)
|
||||
{
|
||||
int fd, n, i;
|
||||
int ph, ps, np;
|
||||
int nnote, nnote2, ns;
|
||||
unsigned long ph, ps, np;
|
||||
long nnote, nnote2, ns;
|
||||
|
||||
if (ac != 2) {
|
||||
fprintf(stderr, "Usage: %s elf-file\n", av[0]);
|
||||
|
|
@ -114,26 +141,27 @@ main(int ac, char **av)
|
|||
exit(1);
|
||||
}
|
||||
|
||||
if (n < E_HSIZE || memcmp(&buf[E_IDENT+EI_MAGIC], elf_magic, 4) != 0)
|
||||
if (memcmp(&buf[E_IDENT+EI_MAGIC], elf_magic, 4) != 0)
|
||||
goto notelf;
|
||||
e_class = buf[E_IDENT+EI_CLASS];
|
||||
if (e_class != ELFCLASS32 && e_class != ELFCLASS64)
|
||||
goto notelf;
|
||||
e_data = buf[E_IDENT+EI_DATA];
|
||||
if (e_data != ELFDATA2MSB && e_data != ELFDATA2LSB)
|
||||
goto notelf;
|
||||
if (n < E_HSIZE)
|
||||
goto notelf;
|
||||
|
||||
if (buf[E_IDENT+EI_CLASS] != ELFCLASS32
|
||||
|| buf[E_IDENT+EI_DATA] != ELFDATA2MSB) {
|
||||
fprintf(stderr, "%s is not a big-endian 32-bit ELF image\n",
|
||||
av[1]);
|
||||
exit(1);
|
||||
}
|
||||
|
||||
ph = GET_32BE(E_PHOFF);
|
||||
ps = GET_16BE(E_PHENTSIZE);
|
||||
np = GET_16BE(E_PHNUM);
|
||||
ph = (e_class == ELFCLASS32 ? GET_32(E_PHOFF) : GET_64(E_PHOFF));
|
||||
ps = GET_16(E_PHENTSIZE);
|
||||
np = GET_16(E_PHNUM);
|
||||
if (ph < E_HSIZE || ps < PH_HSIZE || np < 1)
|
||||
goto notelf;
|
||||
if (ph + (np + 2) * ps + nnote + nnote2 > n)
|
||||
goto nospace;
|
||||
|
||||
for (i = 0; i < np; ++i) {
|
||||
if (GET_32BE(ph + PH_TYPE) == PT_NOTE) {
|
||||
if (GET_32(ph + PH_TYPE) == PT_NOTE) {
|
||||
fprintf(stderr, "%s already has a note entry\n",
|
||||
av[1]);
|
||||
exit(0);
|
||||
|
|
@ -148,15 +176,22 @@ main(int ac, char **av)
|
|||
|
||||
/* fill in the program header entry */
|
||||
ns = ph + 2 * ps;
|
||||
PUT_32BE(ph + PH_TYPE, PT_NOTE);
|
||||
PUT_32BE(ph + PH_OFFSET, ns);
|
||||
PUT_32BE(ph + PH_FILESZ, nnote);
|
||||
PUT_32(ph + PH_TYPE, PT_NOTE);
|
||||
if (e_class == ELFCLASS32)
|
||||
PUT_32(ph + PH_OFFSET, ns);
|
||||
else
|
||||
PUT_64(ph + PH_OFFSET, ns);
|
||||
|
||||
if (e_class == ELFCLASS32)
|
||||
PUT_32(ph + PH_FILESZ, nnote);
|
||||
else
|
||||
PUT_64(ph + PH_FILESZ, nnote);
|
||||
|
||||
/* fill in the note area we point to */
|
||||
/* XXX we should probably make this a proper section */
|
||||
PUT_32BE(ns, strlen(arch) + 1);
|
||||
PUT_32BE(ns + 4, N_DESCR * 4);
|
||||
PUT_32BE(ns + 8, 0x1275);
|
||||
PUT_32(ns, strlen(arch) + 1);
|
||||
PUT_32(ns + 4, N_DESCR * 4);
|
||||
PUT_32(ns + 8, 0x1275);
|
||||
strcpy((char *) &buf[ns + 12], arch);
|
||||
ns += 12 + strlen(arch) + 1;
|
||||
for (i = 0; i < N_DESCR; ++i, ns += 4)
|
||||
|
|
@ -164,21 +199,28 @@ main(int ac, char **av)
|
|||
|
||||
/* fill in the second program header entry and the RPA note area */
|
||||
ph += ps;
|
||||
PUT_32BE(ph + PH_TYPE, PT_NOTE);
|
||||
PUT_32BE(ph + PH_OFFSET, ns);
|
||||
PUT_32BE(ph + PH_FILESZ, nnote2);
|
||||
PUT_32(ph + PH_TYPE, PT_NOTE);
|
||||
if (e_class == ELFCLASS32)
|
||||
PUT_32(ph + PH_OFFSET, ns);
|
||||
else
|
||||
PUT_64(ph + PH_OFFSET, ns);
|
||||
|
||||
if (e_class == ELFCLASS32)
|
||||
PUT_32(ph + PH_FILESZ, nnote);
|
||||
else
|
||||
PUT_64(ph + PH_FILESZ, nnote2);
|
||||
|
||||
/* fill in the note area we point to */
|
||||
PUT_32BE(ns, strlen(rpaname) + 1);
|
||||
PUT_32BE(ns + 4, sizeof(rpanote));
|
||||
PUT_32BE(ns + 8, 0x12759999);
|
||||
PUT_32(ns, strlen(rpaname) + 1);
|
||||
PUT_32(ns + 4, sizeof(rpanote));
|
||||
PUT_32(ns + 8, 0x12759999);
|
||||
strcpy((char *) &buf[ns + 12], rpaname);
|
||||
ns += 12 + ROUNDUP(strlen(rpaname) + 1);
|
||||
for (i = 0; i < N_RPA_DESCR; ++i, ns += 4)
|
||||
PUT_32BE(ns, rpanote[i]);
|
||||
|
||||
/* Update the number of program headers */
|
||||
PUT_16BE(E_PHNUM, np + 2);
|
||||
PUT_16(E_PHNUM, np + 2);
|
||||
|
||||
/* write back */
|
||||
lseek(fd, (long) 0, SEEK_SET);
|
||||
|
|
|
|||
|
|
@ -1,17 +1,20 @@
|
|||
/*
|
||||
* Copyright (C) Paul Mackerras 1997.
|
||||
*
|
||||
* Adapted for 64 bit LE PowerPC by Andrew Tauferner
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License
|
||||
* as published by the Free Software Foundation; either version
|
||||
* 2 of the License, or (at your option) any later version.
|
||||
*
|
||||
* NOTE: this code runs in 32 bit mode, is position-independent,
|
||||
* and is packaged as ELF32.
|
||||
*/
|
||||
|
||||
#include "ppc_asm.h"
|
||||
|
||||
RELA = 7
|
||||
RELACOUNT = 0x6ffffff9
|
||||
|
||||
.text
|
||||
/* A procedure descriptor used when booting this as a COFF file.
|
||||
* When making COFF, this comes first in the link and we're
|
||||
|
|
@ -21,6 +24,20 @@
|
|||
_zimage_start_opd:
|
||||
.long 0x500000, 0, 0, 0
|
||||
|
||||
#ifdef __powerpc64__
|
||||
.balign 8
|
||||
p_start: .llong _start
|
||||
p_etext: .llong _etext
|
||||
p_bss_start: .llong __bss_start
|
||||
p_end: .llong _end
|
||||
|
||||
p_toc: .llong __toc_start + 0x8000 - p_base
|
||||
p_dyn: .llong __dynamic_start - p_base
|
||||
p_rela: .llong __rela_dyn_start - p_base
|
||||
p_prom: .llong 0
|
||||
.weak _platform_stack_top
|
||||
p_pstack: .llong _platform_stack_top
|
||||
#else
|
||||
p_start: .long _start
|
||||
p_etext: .long _etext
|
||||
p_bss_start: .long __bss_start
|
||||
|
|
@ -28,6 +45,7 @@ p_end: .long _end
|
|||
|
||||
.weak _platform_stack_top
|
||||
p_pstack: .long _platform_stack_top
|
||||
#endif
|
||||
|
||||
.weak _zimage_start
|
||||
.globl _zimage_start
|
||||
|
|
@ -38,6 +56,7 @@ _zimage_start_lib:
|
|||
and the address where we're running. */
|
||||
bl .+4
|
||||
p_base: mflr r10 /* r10 now points to runtime addr of p_base */
|
||||
#ifndef __powerpc64__
|
||||
/* grab the link address of the dynamic section in r11 */
|
||||
addis r11,r10,(_GLOBAL_OFFSET_TABLE_-p_base)@ha
|
||||
lwz r11,(_GLOBAL_OFFSET_TABLE_-p_base)@l(r11)
|
||||
|
|
@ -51,8 +70,6 @@ p_base: mflr r10 /* r10 now points to runtime addr of p_base */
|
|||
|
||||
/* The dynamic section contains a series of tagged entries.
|
||||
* We need the RELA and RELACOUNT entries. */
|
||||
RELA = 7
|
||||
RELACOUNT = 0x6ffffff9
|
||||
li r9,0
|
||||
li r0,0
|
||||
9: lwz r8,0(r12) /* get tag */
|
||||
|
|
@ -120,9 +137,164 @@ RELACOUNT = 0x6ffffff9
|
|||
li r0,0
|
||||
stwu r0,-16(r1) /* establish a stack frame */
|
||||
6:
|
||||
#else /* __powerpc64__ */
|
||||
/* Save the prom pointer at p_prom. */
|
||||
std r5,(p_prom-p_base)(r10)
|
||||
|
||||
/* Set r2 to the TOC. */
|
||||
ld r2,(p_toc-p_base)(r10)
|
||||
add r2,r2,r10
|
||||
|
||||
/* Grab the link address of the dynamic section in r11. */
|
||||
ld r11,-32768(r2)
|
||||
cmpwi r11,0
|
||||
beq 3f /* if not linked -pie then no dynamic section */
|
||||
|
||||
ld r11,(p_dyn-p_base)(r10)
|
||||
add r11,r11,r10
|
||||
ld r9,(p_rela-p_base)(r10)
|
||||
add r9,r9,r10
|
||||
|
||||
li r7,0
|
||||
li r8,0
|
||||
9: ld r6,0(r11) /* get tag */
|
||||
cmpdi r6,0
|
||||
beq 12f /* end of list */
|
||||
cmpdi r6,RELA
|
||||
bne 10f
|
||||
ld r7,8(r11) /* get RELA pointer in r7 */
|
||||
b 11f
|
||||
10: addis r6,r6,(-RELACOUNT)@ha
|
||||
cmpdi r6,RELACOUNT@l
|
||||
bne 11f
|
||||
ld r8,8(r11) /* get RELACOUNT value in r8 */
|
||||
11: addi r11,r11,16
|
||||
b 9b
|
||||
12:
|
||||
cmpdi r7,0 /* check we have both RELA and RELACOUNT */
|
||||
cmpdi cr1,r8,0
|
||||
beq 3f
|
||||
beq cr1,3f
|
||||
|
||||
/* Calcuate the runtime offset. */
|
||||
subf r7,r7,r9
|
||||
|
||||
/* Run through the list of relocations and process the
|
||||
* R_PPC64_RELATIVE ones. */
|
||||
mtctr r8
|
||||
13: ld r0,8(r9) /* ELF64_R_TYPE(reloc->r_info) */
|
||||
cmpdi r0,22 /* R_PPC64_RELATIVE */
|
||||
bne 3f
|
||||
ld r6,0(r9) /* reloc->r_offset */
|
||||
ld r0,16(r9) /* reloc->r_addend */
|
||||
add r0,r0,r7
|
||||
stdx r0,r7,r6
|
||||
addi r9,r9,24
|
||||
bdnz 13b
|
||||
|
||||
/* Do a cache flush for our text, in case the loader didn't */
|
||||
3: ld r9,p_start-p_base(r10) /* note: these are relocated now */
|
||||
ld r8,p_etext-p_base(r10)
|
||||
4: dcbf r0,r9
|
||||
icbi r0,r9
|
||||
addi r9,r9,0x20
|
||||
cmpld cr0,r9,r8
|
||||
blt 4b
|
||||
sync
|
||||
isync
|
||||
|
||||
/* Clear the BSS */
|
||||
ld r9,p_bss_start-p_base(r10)
|
||||
ld r8,p_end-p_base(r10)
|
||||
li r0,0
|
||||
5: std r0,0(r9)
|
||||
addi r9,r9,8
|
||||
cmpld cr0,r9,r8
|
||||
blt 5b
|
||||
|
||||
/* Possibly set up a custom stack */
|
||||
ld r8,p_pstack-p_base(r10)
|
||||
cmpdi r8,0
|
||||
beq 6f
|
||||
ld r1,0(r8)
|
||||
li r0,0
|
||||
stdu r0,-16(r1) /* establish a stack frame */
|
||||
6:
|
||||
#endif /* __powerpc64__ */
|
||||
/* Call platform_init() */
|
||||
bl platform_init
|
||||
|
||||
/* Call start */
|
||||
b start
|
||||
|
||||
#ifdef __powerpc64__
|
||||
|
||||
#define PROM_FRAME_SIZE 512
|
||||
#define SAVE_GPR(n, base) std n,8*(n)(base)
|
||||
#define REST_GPR(n, base) ld n,8*(n)(base)
|
||||
#define SAVE_2GPRS(n, base) SAVE_GPR(n, base); SAVE_GPR(n+1, base)
|
||||
#define SAVE_4GPRS(n, base) SAVE_2GPRS(n, base); SAVE_2GPRS(n+2, base)
|
||||
#define SAVE_8GPRS(n, base) SAVE_4GPRS(n, base); SAVE_4GPRS(n+4, base)
|
||||
#define SAVE_10GPRS(n, base) SAVE_8GPRS(n, base); SAVE_2GPRS(n+8, base)
|
||||
#define REST_2GPRS(n, base) REST_GPR(n, base); REST_GPR(n+1, base)
|
||||
#define REST_4GPRS(n, base) REST_2GPRS(n, base); REST_2GPRS(n+2, base)
|
||||
#define REST_8GPRS(n, base) REST_4GPRS(n, base); REST_4GPRS(n+4, base)
|
||||
#define REST_10GPRS(n, base) REST_8GPRS(n, base); REST_2GPRS(n+8, base)
|
||||
|
||||
/* prom handles the jump into and return from firmware. The prom args pointer
|
||||
is loaded in r3. */
|
||||
.globl prom
|
||||
prom:
|
||||
mflr r0
|
||||
std r0,16(r1)
|
||||
stdu r1,-PROM_FRAME_SIZE(r1) /* Save SP and create stack space */
|
||||
|
||||
SAVE_GPR(2, r1)
|
||||
SAVE_GPR(13, r1)
|
||||
SAVE_8GPRS(14, r1)
|
||||
SAVE_10GPRS(22, r1)
|
||||
mfcr r10
|
||||
std r10,8*32(r1)
|
||||
mfmsr r10
|
||||
std r10,8*33(r1)
|
||||
|
||||
/* remove MSR_LE from msr but keep MSR_SF */
|
||||
mfmsr r10
|
||||
rldicr r10,r10,0,62
|
||||
mtsrr1 r10
|
||||
|
||||
/* Load FW address, set LR to label 1, and jump to FW */
|
||||
bl 0f
|
||||
0: mflr r10
|
||||
addi r11,r10,(1f-0b)
|
||||
mtlr r11
|
||||
|
||||
ld r10,(p_prom-0b)(r10)
|
||||
mtsrr0 r10
|
||||
|
||||
rfid
|
||||
|
||||
1: /* Return from OF */
|
||||
FIXUP_ENDIAN
|
||||
|
||||
/* Restore registers and return. */
|
||||
rldicl r1,r1,0,32
|
||||
|
||||
/* Restore the MSR (back to 64 bits) */
|
||||
ld r10,8*(33)(r1)
|
||||
mtmsr r10
|
||||
isync
|
||||
|
||||
/* Restore other registers */
|
||||
REST_GPR(2, r1)
|
||||
REST_GPR(13, r1)
|
||||
REST_8GPRS(14, r1)
|
||||
REST_10GPRS(22, r1)
|
||||
ld r10,8*32(r1)
|
||||
mtcr r10
|
||||
|
||||
addi r1,r1,PROM_FRAME_SIZE
|
||||
ld r0,16(r1)
|
||||
mtlr r0
|
||||
blr
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -15,6 +15,10 @@
|
|||
asm volatile("mfdcrx %0,%1" : "=r"(rval) : "r"(rn)); \
|
||||
rval; \
|
||||
})
|
||||
#define mtdcrx(rn, val) \
|
||||
({ \
|
||||
asm volatile("mtdcrx %0,%1" : : "r"(rn), "r" (val)); \
|
||||
})
|
||||
|
||||
/* 440GP/440GX SDRAM controller DCRs */
|
||||
#define DCRN_SDRAM0_CFGADDR 0x010
|
||||
|
|
|
|||
415
arch/powerpc/boot/dts/akebono.dts
Normal file
415
arch/powerpc/boot/dts/akebono.dts
Normal file
|
|
@ -0,0 +1,415 @@
|
|||
/*
|
||||
* Device Tree Source for IBM Embedded PPC 476 Platform
|
||||
*
|
||||
* Copyright © 2013 Tony Breeds IBM Corporation
|
||||
* Copyright © 2013 Alistair Popple IBM Corporation
|
||||
*
|
||||
* This file is licensed under the terms of the GNU General Public
|
||||
* License version 2. This program is licensed "as is" without
|
||||
* any warranty of any kind, whether express or implied.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
/memreserve/ 0x01f00000 0x00100000; // spin table
|
||||
|
||||
/ {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
model = "ibm,akebono";
|
||||
compatible = "ibm,akebono", "ibm,476gtr";
|
||||
dcr-parent = <&{/cpus/cpu@0}>;
|
||||
|
||||
aliases {
|
||||
serial0 = &UART0;
|
||||
};
|
||||
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
cpu@0 {
|
||||
device_type = "cpu";
|
||||
model = "PowerPC,476";
|
||||
reg = <0>;
|
||||
clock-frequency = <1600000000>; // 1.6 GHz
|
||||
timebase-frequency = <100000000>; // 100Mhz
|
||||
i-cache-line-size = <32>;
|
||||
d-cache-line-size = <32>;
|
||||
i-cache-size = <32768>;
|
||||
d-cache-size = <32768>;
|
||||
dcr-controller;
|
||||
dcr-access-method = "native";
|
||||
status = "ok"
|
||||
};
|
||||
cpu@1 {
|
||||
device_type = "cpu";
|
||||
model = "PowerPC,476";
|
||||
reg = <1>;
|
||||
clock-frequency = <1600000000>; // 1.6 GHz
|
||||
timebase-frequency = <100000000>; // 100Mhz
|
||||
i-cache-line-size = <32>;
|
||||
d-cache-line-size = <32>;
|
||||
i-cache-size = <32768>;
|
||||
d-cache-size = <32768>;
|
||||
dcr-controller;
|
||||
dcr-access-method = "native";
|
||||
status = "disabled";
|
||||
enable-method = "spin-table";
|
||||
cpu-release-addr = <0x0 0x01f00000>;
|
||||
};
|
||||
};
|
||||
|
||||
memory {
|
||||
device_type = "memory";
|
||||
reg = <0x0 0x0 0x0 0x0>; // filled in by zImage
|
||||
};
|
||||
|
||||
MPIC: interrupt-controller {
|
||||
compatible = "chrp,open-pic";
|
||||
interrupt-controller;
|
||||
dcr-reg = <0xffc00000 0x00040000>;
|
||||
#address-cells = <0>;
|
||||
#size-cells = <0>;
|
||||
#interrupt-cells = <2>;
|
||||
single-cpu-affinity;
|
||||
};
|
||||
|
||||
plb {
|
||||
compatible = "ibm,plb6";
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
ranges;
|
||||
clock-frequency = <200000000>; // 200Mhz
|
||||
|
||||
HSTA0: hsta@310000e0000 {
|
||||
compatible = "ibm,476gtr-hsta-msi", "ibm,hsta-msi";
|
||||
reg = <0x310 0x000e0000 0x0 0xf0>;
|
||||
interrupt-parent = <&MPIC>;
|
||||
interrupts = <108 0
|
||||
109 0
|
||||
110 0
|
||||
111 0
|
||||
112 0
|
||||
113 0
|
||||
114 0
|
||||
115 0
|
||||
116 0
|
||||
117 0
|
||||
118 0
|
||||
119 0
|
||||
120 0
|
||||
121 0
|
||||
122 0
|
||||
123 0>;
|
||||
};
|
||||
|
||||
MAL0: mcmal {
|
||||
compatible = "ibm,mcmal-476gtr", "ibm,mcmal2";
|
||||
dcr-reg = <0xc0000000 0x062>;
|
||||
num-tx-chans = <1>;
|
||||
num-rx-chans = <1>;
|
||||
#address-cells = <0>;
|
||||
#size-cells = <0>;
|
||||
interrupt-parent = <&MPIC>;
|
||||
interrupts = < /*TXEOB*/ 77 0x4
|
||||
/*RXEOB*/ 78 0x4
|
||||
/*SERR*/ 76 0x4
|
||||
/*TXDE*/ 79 0x4
|
||||
/*RXDE*/ 80 0x4>;
|
||||
};
|
||||
|
||||
SATA0: sata@30000010000 {
|
||||
compatible = "ibm,476gtr-ahci";
|
||||
reg = <0x300 0x00010000 0x0 0x10000>;
|
||||
interrupt-parent = <&MPIC>;
|
||||
interrupts = <93 2>;
|
||||
};
|
||||
|
||||
EHCI0: ehci@30010000000 {
|
||||
compatible = "ibm,476gtr-ehci", "generic-ehci";
|
||||
reg = <0x300 0x10000000 0x0 0x10000>;
|
||||
interrupt-parent = <&MPIC>;
|
||||
interrupts = <85 2>;
|
||||
};
|
||||
|
||||
SD0: sd@30000000000 {
|
||||
compatible = "ibm,476gtr-sdhci", "generic-sdhci";
|
||||
reg = <0x300 0x00000000 0x0 0x10000>;
|
||||
interrupts = <91 2>;
|
||||
interrupt-parent = <&MPIC>;
|
||||
};
|
||||
|
||||
OHCI0: ohci@30010010000 {
|
||||
compatible = "ibm,476gtr-ohci", "generic-ohci";
|
||||
reg = <0x300 0x10010000 0x0 0x10000>;
|
||||
interrupt-parent = <&MPIC>;
|
||||
interrupts = <89 1>;
|
||||
};
|
||||
|
||||
OHCI1: ohci@30010020000 {
|
||||
compatible = "ibm,476gtr-ohci", "generic-ohci";
|
||||
reg = <0x300 0x10020000 0x0 0x10000>;
|
||||
interrupt-parent = <&MPIC>;
|
||||
interrupts = <88 1>;
|
||||
};
|
||||
|
||||
POB0: opb {
|
||||
compatible = "ibm,opb-4xx", "ibm,opb";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
/* Wish there was a nicer way of specifying a full
|
||||
* 32-bit range
|
||||
*/
|
||||
ranges = <0x00000000 0x0000033f 0x00000000 0x80000000
|
||||
0x80000000 0x0000033f 0x80000000 0x80000000>;
|
||||
clock-frequency = <100000000>;
|
||||
|
||||
RGMII0: emac-rgmii-wol@50004 {
|
||||
compatible = "ibm,rgmii-wol-476gtr", "ibm,rgmii-wol";
|
||||
reg = <0x50004 0x00000008>;
|
||||
has-mdio;
|
||||
};
|
||||
|
||||
EMAC0: ethernet@30000 {
|
||||
device_type = "network";
|
||||
compatible = "ibm,emac-476gtr", "ibm,emac4sync";
|
||||
interrupt-parent = <&EMAC0>;
|
||||
interrupts = <0x0 0x1>;
|
||||
#interrupt-cells = <1>;
|
||||
#address-cells = <0>;
|
||||
#size-cells = <0>;
|
||||
interrupt-map = </*Status*/ 0x0 &MPIC 81 0x4
|
||||
/*Wake*/ 0x1 &MPIC 82 0x4>;
|
||||
reg = <0x30000 0x78>;
|
||||
|
||||
/* local-mac-address will normally be added by
|
||||
* the wrapper. If your device doesn't support
|
||||
* passing data to the wrapper (in the form
|
||||
* local-mac-addr=<hwaddr>) then you will need
|
||||
* to set it manually here. */
|
||||
//local-mac-address = [000000000000];
|
||||
|
||||
mal-device = <&MAL0>;
|
||||
mal-tx-channel = <0>;
|
||||
mal-rx-channel = <0>;
|
||||
cell-index = <0>;
|
||||
max-frame-size = <9000>;
|
||||
rx-fifo-size = <4096>;
|
||||
tx-fifo-size = <2048>;
|
||||
rx-fifo-size-gige = <16384>;
|
||||
phy-mode = "rgmii";
|
||||
phy-map = <0x00000000>;
|
||||
rgmii-wol-device = <&RGMII0>;
|
||||
has-inverted-stacr-oc;
|
||||
has-new-stacr-staopc;
|
||||
};
|
||||
|
||||
UART0: serial@10000 {
|
||||
device_type = "serial";
|
||||
compatible = "ns16750", "ns16550";
|
||||
reg = <0x10000 0x00000008>;
|
||||
virtual-reg = <0xe8010000>;
|
||||
clock-frequency = <1851851>;
|
||||
current-speed = <38400>;
|
||||
interrupt-parent = <&MPIC>;
|
||||
interrupts = <39 2>;
|
||||
};
|
||||
|
||||
IIC0: i2c@00000000 {
|
||||
compatible = "ibm,iic-476gtr", "ibm,iic";
|
||||
reg = <0x0 0x00000020>;
|
||||
interrupt-parent = <&MPIC>;
|
||||
interrupts = <37 2>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
rtc@68 {
|
||||
compatible = "stm,m41t80", "m41st85";
|
||||
reg = <0x68>;
|
||||
};
|
||||
};
|
||||
|
||||
IIC1: i2c@00000100 {
|
||||
compatible = "ibm,iic-476gtr", "ibm,iic";
|
||||
reg = <0x100 0x00000020>;
|
||||
interrupt-parent = <&MPIC>;
|
||||
interrupts = <38 2>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
avr@58 {
|
||||
compatible = "ibm,akebono-avr";
|
||||
reg = <0x58>;
|
||||
};
|
||||
};
|
||||
|
||||
FPGA0: fpga@ebc00000 {
|
||||
compatible = "ibm,akebono-fpga";
|
||||
reg = <0xebc00000 0x8>;
|
||||
};
|
||||
};
|
||||
|
||||
PCIE0: pciex@10100000000 {
|
||||
device_type = "pci";
|
||||
#interrupt-cells = <1>;
|
||||
#size-cells = <2>;
|
||||
#address-cells = <3>;
|
||||
compatible = "ibm,plb-pciex-476fpe", "ibm,plb-pciex";
|
||||
primary;
|
||||
port = <0x0>; /* port number */
|
||||
reg = <0x00000101 0x00000000 0x0 0x10000000 /* Config space access */
|
||||
0x00000100 0x00000000 0x0 0x00001000>; /* UTL Registers space access */
|
||||
dcr-reg = <0xc0 0x20>;
|
||||
|
||||
// pci_space < pci_addr > < cpu_addr > < size >
|
||||
ranges = <0x02000000 0x00000000 0x80000000 0x00000110 0x80000000 0x0 0x80000000
|
||||
0x01000000 0x0 0x0 0x00000140 0x0 0x0 0x00010000>;
|
||||
|
||||
/* Inbound starting at 0x0 to 0x40000000000. In order to use MSI
|
||||
* PCI devices must be able to write to the HSTA module.
|
||||
*/
|
||||
dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x400 0x0>;
|
||||
|
||||
/* This drives busses 0 to 0xf */
|
||||
bus-range = <0x0 0xf>;
|
||||
|
||||
/* Legacy interrupts (note the weird polarity, the bridge seems
|
||||
* to invert PCIe legacy interrupts).
|
||||
* We are de-swizzling here because the numbers are actually for
|
||||
* port of the root complex virtual P2P bridge. But I want
|
||||
* to avoid putting a node for it in the tree, so the numbers
|
||||
* below are basically de-swizzled numbers.
|
||||
* The real slot is on idsel 0, so the swizzling is 1:1
|
||||
*/
|
||||
interrupt-map-mask = <0x0 0x0 0x0 0x7>;
|
||||
interrupt-map = <
|
||||
0x0 0x0 0x0 0x1 &MPIC 45 0x2 /* int A */
|
||||
0x0 0x0 0x0 0x2 &MPIC 46 0x2 /* int B */
|
||||
0x0 0x0 0x0 0x3 &MPIC 47 0x2 /* int C */
|
||||
0x0 0x0 0x0 0x4 &MPIC 48 0x2 /* int D */>;
|
||||
};
|
||||
|
||||
PCIE1: pciex@20100000000 {
|
||||
device_type = "pci";
|
||||
#interrupt-cells = <1>;
|
||||
#size-cells = <2>;
|
||||
#address-cells = <3>;
|
||||
compatible = "ibm,plb-pciex-476fpe", "ibm,plb-pciex";
|
||||
primary;
|
||||
port = <0x1>; /* port number */
|
||||
reg = <0x00000201 0x00000000 0x0 0x10000000 /* Config space access */
|
||||
0x00000200 0x00000000 0x0 0x00001000>; /* UTL Registers space access */
|
||||
dcr-reg = <0x100 0x20>;
|
||||
|
||||
// pci_space < pci_addr > < cpu_addr > < size >
|
||||
ranges = <0x02000000 0x00000000 0x80000000 0x00000210 0x80000000 0x0 0x80000000
|
||||
0x01000000 0x0 0x0 0x00000240 0x0 0x0 0x00010000>;
|
||||
|
||||
/* Inbound starting at 0x0 to 0x40000000000. In order to use MSI
|
||||
* PCI devices must be able to write to the HSTA module.
|
||||
*/
|
||||
dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x400 0x0>;
|
||||
|
||||
/* This drives busses 0 to 0xf */
|
||||
bus-range = <0x0 0xf>;
|
||||
|
||||
/* Legacy interrupts (note the weird polarity, the bridge seems
|
||||
* to invert PCIe legacy interrupts).
|
||||
* We are de-swizzling here because the numbers are actually for
|
||||
* port of the root complex virtual P2P bridge. But I want
|
||||
* to avoid putting a node for it in the tree, so the numbers
|
||||
* below are basically de-swizzled numbers.
|
||||
* The real slot is on idsel 0, so the swizzling is 1:1
|
||||
*/
|
||||
interrupt-map-mask = <0x0 0x0 0x0 0x7>;
|
||||
interrupt-map = <
|
||||
0x0 0x0 0x0 0x1 &MPIC 53 0x2 /* int A */
|
||||
0x0 0x0 0x0 0x2 &MPIC 54 0x2 /* int B */
|
||||
0x0 0x0 0x0 0x3 &MPIC 55 0x2 /* int C */
|
||||
0x0 0x0 0x0 0x4 &MPIC 56 0x2 /* int D */>;
|
||||
};
|
||||
|
||||
PCIE2: pciex@18100000000 {
|
||||
device_type = "pci";
|
||||
#interrupt-cells = <1>;
|
||||
#size-cells = <2>;
|
||||
#address-cells = <3>;
|
||||
compatible = "ibm,plb-pciex-476fpe", "ibm,plb-pciex";
|
||||
primary;
|
||||
port = <0x2>; /* port number */
|
||||
reg = <0x00000181 0x00000000 0x0 0x10000000 /* Config space access */
|
||||
0x00000180 0x00000000 0x0 0x00001000>; /* UTL Registers space access */
|
||||
dcr-reg = <0xe0 0x20>;
|
||||
|
||||
// pci_space < pci_addr > < cpu_addr > < size >
|
||||
ranges = <0x02000000 0x00000000 0x80000000 0x00000190 0x80000000 0x0 0x80000000
|
||||
0x01000000 0x0 0x0 0x000001c0 0x0 0x0 0x00010000>;
|
||||
|
||||
/* Inbound starting at 0x0 to 0x40000000000. In order to use MSI
|
||||
* PCI devices must be able to write to the HSTA module.
|
||||
*/
|
||||
dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x400 0x0>;
|
||||
|
||||
/* This drives busses 0 to 0xf */
|
||||
bus-range = <0x0 0xf>;
|
||||
|
||||
/* Legacy interrupts (note the weird polarity, the bridge seems
|
||||
* to invert PCIe legacy interrupts).
|
||||
* We are de-swizzling here because the numbers are actually for
|
||||
* port of the root complex virtual P2P bridge. But I want
|
||||
* to avoid putting a node for it in the tree, so the numbers
|
||||
* below are basically de-swizzled numbers.
|
||||
* The real slot is on idsel 0, so the swizzling is 1:1
|
||||
*/
|
||||
interrupt-map-mask = <0x0 0x0 0x0 0x7>;
|
||||
interrupt-map = <
|
||||
0x0 0x0 0x0 0x1 &MPIC 61 0x2 /* int A */
|
||||
0x0 0x0 0x0 0x2 &MPIC 62 0x2 /* int B */
|
||||
0x0 0x0 0x0 0x3 &MPIC 63 0x2 /* int C */
|
||||
0x0 0x0 0x0 0x4 &MPIC 64 0x2 /* int D */>;
|
||||
};
|
||||
|
||||
PCIE3: pciex@28100000000 {
|
||||
device_type = "pci";
|
||||
#interrupt-cells = <1>;
|
||||
#size-cells = <2>;
|
||||
#address-cells = <3>;
|
||||
compatible = "ibm,plb-pciex-476fpe", "ibm,plb-pciex";
|
||||
primary;
|
||||
port = <0x3>; /* port number */
|
||||
reg = <0x00000281 0x00000000 0x0 0x10000000 /* Config space access */
|
||||
0x00000280 0x00000000 0x0 0x00001000>; /* UTL Registers space access */
|
||||
dcr-reg = <0x120 0x20>;
|
||||
|
||||
// pci_space < pci_addr > < cpu_addr > < size >
|
||||
ranges = <0x02000000 0x00000000 0x80000000 0x00000290 0x80000000 0x0 0x80000000
|
||||
0x01000000 0x0 0x0 0x000002c0 0x0 0x0 0x00010000>;
|
||||
|
||||
/* Inbound starting at 0x0 to 0x40000000000. In order to use MSI
|
||||
* PCI devices must be able to write to the HSTA module.
|
||||
*/
|
||||
dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x400 0x0>;
|
||||
|
||||
/* This drives busses 0 to 0xf */
|
||||
bus-range = <0x0 0xf>;
|
||||
|
||||
/* Legacy interrupts (note the weird polarity, the bridge seems
|
||||
* to invert PCIe legacy interrupts).
|
||||
* We are de-swizzling here because the numbers are actually for
|
||||
* port of the root complex virtual P2P bridge. But I want
|
||||
* to avoid putting a node for it in the tree, so the numbers
|
||||
* below are basically de-swizzled numbers.
|
||||
* The real slot is on idsel 0, so the swizzling is 1:1
|
||||
*/
|
||||
interrupt-map-mask = <0x0 0x0 0x0 0x7>;
|
||||
interrupt-map = <
|
||||
0x0 0x0 0x0 0x1 &MPIC 69 0x2 /* int A */
|
||||
0x0 0x0 0x0 0x2 &MPIC 70 0x2 /* int B */
|
||||
0x0 0x0 0x0 0x3 &MPIC 71 0x2 /* int C */
|
||||
0x0 0x0 0x0 0x4 &MPIC 72 0x2 /* int D */>;
|
||||
};
|
||||
};
|
||||
|
||||
chosen {
|
||||
linux,stdout-path = &UART0;
|
||||
};
|
||||
};
|
||||
|
|
@ -61,21 +61,25 @@
|
|||
device_type = "cpu";
|
||||
reg = <0 1>;
|
||||
next-level-cache = <&L2>;
|
||||
fsl,portid-mapping = <0x80000000>;
|
||||
};
|
||||
cpu1: PowerPC,e6500@2 {
|
||||
device_type = "cpu";
|
||||
reg = <2 3>;
|
||||
next-level-cache = <&L2>;
|
||||
fsl,portid-mapping = <0x80000000>;
|
||||
};
|
||||
cpu2: PowerPC,e6500@4 {
|
||||
device_type = "cpu";
|
||||
reg = <4 5>;
|
||||
next-level-cache = <&L2>;
|
||||
fsl,portid-mapping = <0x80000000>;
|
||||
};
|
||||
cpu3: PowerPC,e6500@6 {
|
||||
device_type = "cpu";
|
||||
reg = <6 7>;
|
||||
next-level-cache = <&L2>;
|
||||
fsl,portid-mapping = <0x80000000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
@ -157,7 +161,7 @@
|
|||
};
|
||||
|
||||
corenet-cf@18000 {
|
||||
compatible = "fsl,b4-corenet-cf";
|
||||
compatible = "fsl,corenet2-cf", "fsl,corenet-cf";
|
||||
reg = <0x18000 0x1000>;
|
||||
interrupts = <16 2 1 0>;
|
||||
fsl,ccf-num-csdids = <32>;
|
||||
|
|
@ -167,6 +171,7 @@
|
|||
iommu@20000 {
|
||||
compatible = "fsl,pamu-v1.0", "fsl,pamu";
|
||||
reg = <0x20000 0x4000>;
|
||||
fsl,portid-mapping = <0x8000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
interrupts = <
|
||||
|
|
|
|||
Some files were not shown because too many files have changed in this diff Show more
Loading…
Reference in a new issue