This is the 4.9.78 stable release
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This commit is contained in:
Greg Kroah-Hartman
commit
bf3b33980d
60 changed files with 525 additions and 167 deletions
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@ -78,7 +78,7 @@ this protection comes at a cost:
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non-PTI SYSCALL entry code, so requires mapping fewer
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things into the userspace page tables. The downside is
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that stacks must be switched at entry time.
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d. Global pages are disabled for all kernel structures not
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c. Global pages are disabled for all kernel structures not
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mapped into both kernel and userspace page tables. This
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feature of the MMU allows different processes to share TLB
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entries mapping the kernel. Losing the feature means more
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2
Makefile
2
Makefile
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@ -1,6 +1,6 @@
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VERSION = 4
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PATCHLEVEL = 9
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SUBLEVEL = 77
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SUBLEVEL = 78
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EXTRAVERSION =
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NAME = Roaring Lionus
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@ -53,7 +53,8 @@
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};
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pinctrl: pin-controller@10000 {
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pinctrl-0 = <&pmx_dip_switches &pmx_gpio_header>;
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pinctrl-0 = <&pmx_dip_switches &pmx_gpio_header
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&pmx_gpio_header_gpo>;
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pinctrl-names = "default";
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pmx_uart0: pmx-uart0 {
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@ -85,11 +86,16 @@
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* ground.
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*/
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pmx_gpio_header: pmx-gpio-header {
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marvell,pins = "mpp17", "mpp7", "mpp29", "mpp28",
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marvell,pins = "mpp17", "mpp29", "mpp28",
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"mpp35", "mpp34", "mpp40";
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marvell,function = "gpio";
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};
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pmx_gpio_header_gpo: pxm-gpio-header-gpo {
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marvell,pins = "mpp7";
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marvell,function = "gpo";
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};
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pmx_gpio_init: pmx-init {
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marvell,pins = "mpp38";
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marvell,function = "gpio";
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@ -11,6 +11,7 @@ CONFIG_SMP=y
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CONFIG_NR_CPUS=8
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CONFIG_AEABI=y
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CONFIG_HIGHMEM=y
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CONFIG_CMA=y
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CONFIG_ARM_APPENDED_DTB=y
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CONFIG_ARM_ATAG_DTB_COMPAT=y
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CONFIG_CPU_FREQ=y
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@ -35,6 +36,7 @@ CONFIG_CAN_SUN4I=y
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# CONFIG_WIRELESS is not set
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CONFIG_DEVTMPFS=y
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CONFIG_DEVTMPFS_MOUNT=y
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CONFIG_DMA_CMA=y
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CONFIG_BLK_DEV_SD=y
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CONFIG_ATA=y
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CONFIG_AHCI_SUNXI=y
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@ -44,7 +44,7 @@ static int handle_hvc(struct kvm_vcpu *vcpu, struct kvm_run *run)
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ret = kvm_psci_call(vcpu);
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if (ret < 0) {
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kvm_inject_undefined(vcpu);
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vcpu_set_reg(vcpu, 0, ~0UL);
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return 1;
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}
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@ -53,7 +53,7 @@ static int handle_hvc(struct kvm_vcpu *vcpu, struct kvm_run *run)
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static int handle_smc(struct kvm_vcpu *vcpu, struct kvm_run *run)
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{
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kvm_inject_undefined(vcpu);
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vcpu_set_reg(vcpu, 0, ~0UL);
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return 1;
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}
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@ -576,7 +576,7 @@ static int __init ar7_register_uarts(void)
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uart_port.type = PORT_AR7;
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uart_port.uartclk = clk_get_rate(bus_clk) / 2;
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uart_port.iotype = UPIO_MEM32;
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uart_port.flags = UPF_FIXED_TYPE;
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uart_port.flags = UPF_FIXED_TYPE | UPF_BOOT_AUTOCONF;
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uart_port.regshift = 2;
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uart_port.line = 0;
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@ -229,6 +229,17 @@ ENTRY(__switch_to_asm)
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movl %ebx, PER_CPU_VAR(stack_canary)+stack_canary_offset
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#endif
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#ifdef CONFIG_RETPOLINE
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/*
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* When switching from a shallower to a deeper call stack
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* the RSB may either underflow or use entries populated
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* with userspace addresses. On CPUs where those concerns
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* exist, overwrite the RSB with entries which capture
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* speculative execution to prevent attack.
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*/
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FILL_RETURN_BUFFER %ebx, RSB_CLEAR_LOOPS, X86_FEATURE_RSB_CTXSW
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#endif
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/* restore callee-saved registers */
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popl %esi
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popl %edi
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@ -427,6 +427,17 @@ ENTRY(__switch_to_asm)
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movq %rbx, PER_CPU_VAR(irq_stack_union)+stack_canary_offset
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#endif
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#ifdef CONFIG_RETPOLINE
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/*
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* When switching from a shallower to a deeper call stack
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* the RSB may either underflow or use entries populated
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* with userspace addresses. On CPUs where those concerns
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* exist, overwrite the RSB with entries which capture
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* speculative execution to prevent attack.
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*/
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FILL_RETURN_BUFFER %r12, RSB_CLEAR_LOOPS, X86_FEATURE_RSB_CTXSW
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#endif
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/* restore callee-saved registers */
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popq %r15
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popq %r14
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@ -1053,7 +1064,7 @@ idtentry async_page_fault do_async_page_fault has_error_code=1
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#endif
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#ifdef CONFIG_X86_MCE
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idtentry machine_check has_error_code=0 paranoid=1 do_sym=*machine_check_vector(%rip)
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idtentry machine_check do_mce has_error_code=0 paranoid=1
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#endif
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/*
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@ -197,9 +197,9 @@
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#define X86_FEATURE_RETPOLINE ( 7*32+12) /* Generic Retpoline mitigation for Spectre variant 2 */
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#define X86_FEATURE_RETPOLINE_AMD ( 7*32+13) /* AMD Retpoline mitigation for Spectre variant 2 */
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#define X86_FEATURE_INTEL_PT ( 7*32+15) /* Intel Processor Trace */
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#define X86_FEATURE_AVX512_4VNNIW (7*32+16) /* AVX-512 Neural Network Instructions */
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#define X86_FEATURE_AVX512_4FMAPS (7*32+17) /* AVX-512 Multiply Accumulation Single precision */
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#define X86_FEATURE_RSB_CTXSW ( 7*32+19) /* Fill RSB on context switches */
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/* Because the ALTERNATIVE scheme is for members of the X86_FEATURE club... */
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#define X86_FEATURE_KAISER ( 7*32+31) /* CONFIG_PAGE_TABLE_ISOLATION w/o nokaiser */
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@ -235,6 +235,7 @@
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#define X86_FEATURE_SMAP ( 9*32+20) /* Supervisor Mode Access Prevention */
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#define X86_FEATURE_CLFLUSHOPT ( 9*32+23) /* CLFLUSHOPT instruction */
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#define X86_FEATURE_CLWB ( 9*32+24) /* CLWB instruction */
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#define X86_FEATURE_INTEL_PT ( 9*32+25) /* Intel Processor Trace */
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#define X86_FEATURE_AVX512PF ( 9*32+26) /* AVX-512 Prefetch */
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#define X86_FEATURE_AVX512ER ( 9*32+27) /* AVX-512 Exponential and Reciprocal */
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#define X86_FEATURE_AVX512CD ( 9*32+28) /* AVX-512 Conflict Detection */
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@ -11,7 +11,7 @@
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* Fill the CPU return stack buffer.
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*
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* Each entry in the RSB, if used for a speculative 'ret', contains an
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* infinite 'pause; jmp' loop to capture speculative execution.
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* infinite 'pause; lfence; jmp' loop to capture speculative execution.
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*
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* This is required in various cases for retpoline and IBRS-based
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* mitigations for the Spectre variant 2 vulnerability. Sometimes to
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@ -38,11 +38,13 @@
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call 772f; \
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773: /* speculation trap */ \
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pause; \
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lfence; \
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jmp 773b; \
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772: \
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call 774f; \
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775: /* speculation trap */ \
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pause; \
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lfence; \
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jmp 775b; \
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774: \
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dec reg; \
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@ -73,6 +75,7 @@
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call .Ldo_rop_\@
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.Lspec_trap_\@:
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pause
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lfence
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jmp .Lspec_trap_\@
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.Ldo_rop_\@:
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mov \reg, (%_ASM_SP)
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@ -165,6 +168,7 @@
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" .align 16\n" \
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"901: call 903f;\n" \
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"902: pause;\n" \
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" lfence;\n" \
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" jmp 902b;\n" \
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" .align 16\n" \
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"903: addl $4, %%esp;\n" \
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@ -190,6 +194,9 @@ enum spectre_v2_mitigation {
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SPECTRE_V2_IBRS,
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};
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extern char __indirect_thunk_start[];
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extern char __indirect_thunk_end[];
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/*
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* On VMEXIT we must ensure that no RSB predictions learned in the guest
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* can be followed in the host, by overwriting the RSB completely. Both
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@ -199,16 +206,17 @@ enum spectre_v2_mitigation {
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static inline void vmexit_fill_RSB(void)
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{
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#ifdef CONFIG_RETPOLINE
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unsigned long loops = RSB_CLEAR_LOOPS / 2;
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unsigned long loops;
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asm volatile (ANNOTATE_NOSPEC_ALTERNATIVE
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ALTERNATIVE("jmp 910f",
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__stringify(__FILL_RETURN_BUFFER(%0, RSB_CLEAR_LOOPS, %1)),
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X86_FEATURE_RETPOLINE)
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"910:"
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: "=&r" (loops), ASM_CALL_CONSTRAINT
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: "r" (loops) : "memory" );
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: "=r" (loops), ASM_CALL_CONSTRAINT
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: : "memory" );
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#endif
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}
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#endif /* __ASSEMBLY__ */
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#endif /* __NOSPEC_BRANCH_H__ */
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@ -92,6 +92,7 @@ dotraplinkage void do_simd_coprocessor_error(struct pt_regs *, long);
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#ifdef CONFIG_X86_32
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dotraplinkage void do_iret_error(struct pt_regs *, long);
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#endif
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dotraplinkage void do_mce(struct pt_regs *, long);
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static inline int get_si_code(unsigned long condition)
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{
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@ -361,14 +361,17 @@ static int x86_vector_alloc_irqs(struct irq_domain *domain, unsigned int virq,
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irq_data->chip_data = data;
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irq_data->hwirq = virq + i;
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err = assign_irq_vector_policy(virq + i, node, data, info);
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if (err)
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if (err) {
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irq_data->chip_data = NULL;
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free_apic_chip_data(data);
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goto error;
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}
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}
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return 0;
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error:
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x86_vector_free_irqs(domain, virq, i + 1);
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x86_vector_free_irqs(domain, virq, i);
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return err;
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}
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@ -22,6 +22,7 @@
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#include <asm/alternative.h>
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#include <asm/pgtable.h>
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#include <asm/cacheflush.h>
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#include <asm/intel-family.h>
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static void __init spectre_v2_select_mitigation(void);
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@ -154,6 +155,23 @@ disable:
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return SPECTRE_V2_CMD_NONE;
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}
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/* Check for Skylake-like CPUs (for RSB handling) */
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static bool __init is_skylake_era(void)
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{
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if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL &&
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boot_cpu_data.x86 == 6) {
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switch (boot_cpu_data.x86_model) {
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case INTEL_FAM6_SKYLAKE_MOBILE:
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case INTEL_FAM6_SKYLAKE_DESKTOP:
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case INTEL_FAM6_SKYLAKE_X:
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case INTEL_FAM6_KABYLAKE_MOBILE:
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case INTEL_FAM6_KABYLAKE_DESKTOP:
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return true;
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}
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}
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return false;
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}
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static void __init spectre_v2_select_mitigation(void)
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{
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enum spectre_v2_mitigation_cmd cmd = spectre_v2_parse_cmdline();
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@ -212,6 +230,24 @@ retpoline_auto:
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spectre_v2_enabled = mode;
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pr_info("%s\n", spectre_v2_strings[mode]);
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/*
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* If neither SMEP or KPTI are available, there is a risk of
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* hitting userspace addresses in the RSB after a context switch
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* from a shallow call stack to a deeper one. To prevent this fill
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* the entire RSB, even when using IBRS.
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*
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* Skylake era CPUs have a separate issue with *underflow* of the
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* RSB, when they will predict 'ret' targets from the generic BTB.
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* The proper mitigation for this is IBRS. If IBRS is not supported
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* or deactivated in favour of retpolines the RSB fill on context
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* switch is required.
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*/
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if ((!boot_cpu_has(X86_FEATURE_KAISER) &&
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!boot_cpu_has(X86_FEATURE_SMEP)) || is_skylake_era()) {
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setup_force_cpu_cap(X86_FEATURE_RSB_CTXSW);
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pr_info("Filling RSB on context switch\n");
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}
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}
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#undef pr_fmt
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|
|
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@ -883,8 +883,8 @@ static void __init early_identify_cpu(struct cpuinfo_x86 *c)
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setup_force_cpu_cap(X86_FEATURE_ALWAYS);
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/* Assume for now that ALL x86 CPUs are insecure */
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setup_force_cpu_bug(X86_BUG_CPU_MELTDOWN);
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if (c->x86_vendor != X86_VENDOR_AMD)
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setup_force_cpu_bug(X86_BUG_CPU_MELTDOWN);
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setup_force_cpu_bug(X86_BUG_SPECTRE_V1);
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setup_force_cpu_bug(X86_BUG_SPECTRE_V2);
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|
|
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|
|
@ -1754,6 +1754,11 @@ static void unexpected_machine_check(struct pt_regs *regs, long error_code)
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void (*machine_check_vector)(struct pt_regs *, long error_code) =
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unexpected_machine_check;
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|
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dotraplinkage void do_mce(struct pt_regs *regs, long error_code)
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{
|
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machine_check_vector(regs, error_code);
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}
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||||
|
||||
/*
|
||||
* Called for each booted CPU to set up machine checks.
|
||||
* Must be called with preempt off:
|
||||
|
|
|
|||
|
|
@ -31,7 +31,6 @@ void init_scattered_cpuid_features(struct cpuinfo_x86 *c)
|
|||
const struct cpuid_bit *cb;
|
||||
|
||||
static const struct cpuid_bit cpuid_bits[] = {
|
||||
{ X86_FEATURE_INTEL_PT, CR_EBX,25, 0x00000007, 0 },
|
||||
{ X86_FEATURE_AVX512_4VNNIW, CR_EDX, 2, 0x00000007, 0 },
|
||||
{ X86_FEATURE_AVX512_4FMAPS, CR_EDX, 3, 0x00000007, 0 },
|
||||
{ X86_FEATURE_APERFMPERF, CR_ECX, 0, 0x00000006, 0 },
|
||||
|
|
|
|||
|
|
@ -37,6 +37,7 @@
|
|||
#include <asm/alternative.h>
|
||||
#include <asm/insn.h>
|
||||
#include <asm/debugreg.h>
|
||||
#include <asm/nospec-branch.h>
|
||||
|
||||
#include "common.h"
|
||||
|
||||
|
|
@ -192,7 +193,7 @@ static int copy_optimized_instructions(u8 *dest, u8 *src)
|
|||
}
|
||||
|
||||
/* Check whether insn is indirect jump */
|
||||
static int insn_is_indirect_jump(struct insn *insn)
|
||||
static int __insn_is_indirect_jump(struct insn *insn)
|
||||
{
|
||||
return ((insn->opcode.bytes[0] == 0xff &&
|
||||
(X86_MODRM_REG(insn->modrm.value) & 6) == 4) || /* Jump */
|
||||
|
|
@ -226,6 +227,26 @@ static int insn_jump_into_range(struct insn *insn, unsigned long start, int len)
|
|||
return (start <= target && target <= start + len);
|
||||
}
|
||||
|
||||
static int insn_is_indirect_jump(struct insn *insn)
|
||||
{
|
||||
int ret = __insn_is_indirect_jump(insn);
|
||||
|
||||
#ifdef CONFIG_RETPOLINE
|
||||
/*
|
||||
* Jump to x86_indirect_thunk_* is treated as an indirect jump.
|
||||
* Note that even with CONFIG_RETPOLINE=y, the kernel compiled with
|
||||
* older gcc may use indirect jump. So we add this check instead of
|
||||
* replace indirect-jump check.
|
||||
*/
|
||||
if (!ret)
|
||||
ret = insn_jump_into_range(insn,
|
||||
(unsigned long)__indirect_thunk_start,
|
||||
(unsigned long)__indirect_thunk_end -
|
||||
(unsigned long)__indirect_thunk_start);
|
||||
#endif
|
||||
return ret;
|
||||
}
|
||||
|
||||
/* Decode whole function to ensure any instructions don't jump into target */
|
||||
static int can_optimize(unsigned long paddr)
|
||||
{
|
||||
|
|
|
|||
|
|
@ -693,7 +693,6 @@ unsigned long native_calibrate_tsc(void)
|
|||
case INTEL_FAM6_KABYLAKE_DESKTOP:
|
||||
crystal_khz = 24000; /* 24.0 MHz */
|
||||
break;
|
||||
case INTEL_FAM6_SKYLAKE_X:
|
||||
case INTEL_FAM6_ATOM_DENVERTON:
|
||||
crystal_khz = 25000; /* 25.0 MHz */
|
||||
break;
|
||||
|
|
|
|||
|
|
@ -105,6 +105,13 @@ SECTIONS
|
|||
SOFTIRQENTRY_TEXT
|
||||
*(.fixup)
|
||||
*(.gnu.warning)
|
||||
|
||||
#ifdef CONFIG_RETPOLINE
|
||||
__indirect_thunk_start = .;
|
||||
*(.text.__x86.indirect_thunk)
|
||||
__indirect_thunk_end = .;
|
||||
#endif
|
||||
|
||||
/* End of text section */
|
||||
_etext = .;
|
||||
} :text = 0x9090
|
||||
|
|
|
|||
|
|
@ -9,7 +9,7 @@
|
|||
#include <asm/nospec-branch.h>
|
||||
|
||||
.macro THUNK reg
|
||||
.section .text.__x86.indirect_thunk.\reg
|
||||
.section .text.__x86.indirect_thunk
|
||||
|
||||
ENTRY(__x86_indirect_thunk_\reg)
|
||||
CFI_STARTPROC
|
||||
|
|
@ -25,7 +25,8 @@ ENDPROC(__x86_indirect_thunk_\reg)
|
|||
* than one per register with the correct names. So we do it
|
||||
* the simple and nasty way...
|
||||
*/
|
||||
#define EXPORT_THUNK(reg) EXPORT_SYMBOL(__x86_indirect_thunk_ ## reg)
|
||||
#define __EXPORT_THUNK(sym) _ASM_NOKPROBE(sym); EXPORT_SYMBOL(sym)
|
||||
#define EXPORT_THUNK(reg) __EXPORT_THUNK(__x86_indirect_thunk_ ## reg)
|
||||
#define GENERATE_THUNK(reg) THUNK reg ; EXPORT_THUNK(reg)
|
||||
|
||||
GENERATE_THUNK(_ASM_AX)
|
||||
|
|
|
|||
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Reference in a new issue