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ARM: SoC driver updates for v4.4

Browse source 
As we've enabled multiplatform kernels on ARM, and greatly done away with
 the contents under arch/arm/mach-*, there's still need for SoC-related
 drivers to go somewhere.
 
 Many of them go in through other driver trees, but we still have
 drivers/soc to hold some of the "doesn't fit anywhere" lowlevel code
 that might be shared between ARM and ARM64 (or just in general makes
 sense to not have under the architecture directory).
 
 This branch contains mostly such code:
 
 - Drivers for qualcomm SoCs for SMEM, SMD and SMD-RPM, used to communicate
   with power management blocks on these SoCs for use by clock, regulator and
   bus frequency drivers.
 - Allwinner Reduced Serial Bus driver, again used to communicate with PMICs.
 - Drivers for ARM's SCPI (System Control Processor). Not to be confused with
   PSCI (Power State Coordination Interface). SCPI is used to communicate with
   the assistant embedded cores doing power management, and we have yet to see
   how many of them will implement this for their hardware vs abstracting in
   other ways (or not at all like in the past).
 - To make confusion between SCPI and PSCI more likely, this release also
   includes an update of PSCI to interface version 1.0.
 - Rockchip support for power domains.
 - A driver to talk to the firmware on Raspberry Pi.
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Merge tag 'armsoc-drivers' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc

Pull ARM SoC driver updates from Olof Johansson:
 "As we've enabled multiplatform kernels on ARM, and greatly done away
  with the contents under arch/arm/mach-*, there's still need for
  SoC-related drivers to go somewhere.

  Many of them go in through other driver trees, but we still have
  drivers/soc to hold some of the "doesn't fit anywhere" lowlevel code
  that might be shared between ARM and ARM64 (or just in general makes
  sense to not have under the architecture directory).

  This branch contains mostly such code:

   - Drivers for qualcomm SoCs for SMEM, SMD and SMD-RPM, used to
     communicate with power management blocks on these SoCs for use by
     clock, regulator and bus frequency drivers.

   - Allwinner Reduced Serial Bus driver, again used to communicate with
     PMICs.

   - Drivers for ARM's SCPI (System Control Processor).  Not to be
     confused with PSCI (Power State Coordination Interface).  SCPI is
     used to communicate with the assistant embedded cores doing power
     management, and we have yet to see how many of them will implement
     this for their hardware vs abstracting in other ways (or not at all
     like in the past).

   - To make confusion between SCPI and PSCI more likely, this release
     also includes an update of PSCI to interface version 1.0.

   - Rockchip support for power domains.

   - A driver to talk to the firmware on Raspberry Pi"

* tag 'armsoc-drivers' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (57 commits)
  soc: qcom: smd-rpm: Correct size of outgoing message
  bus: sunxi-rsb: Add driver for Allwinner Reduced Serial Bus
  bus: sunxi-rsb: Add Allwinner Reduced Serial Bus (RSB) controller bindings
  ARM: bcm2835: add mutual inclusion protection
  drivers: psci: make PSCI 1.0 functions initialization version dependent
  dt-bindings: Correct paths in Rockchip power domains binding document
  soc: rockchip: power-domain: don't try to print the clock name in error case
  soc: qcom/smem: add HWSPINLOCK dependency
  clk: berlin: add cpuclk
  ARM: berlin: dts: add CLKID_CPU for BG2Q
  ARM: bcm2835: Add the Raspberry Pi firmware driver
  soc: qcom: smem: Move RPM message ram out of smem DT node
  soc: qcom: smd-rpm: Correct the active vs sleep state flagging
  soc: qcom: smd: delete unneeded of_node_put
  firmware: qcom-scm: build for correct architecture level
  soc: qcom: smd: Correct SMEM items for upper channels
  qcom-scm: add missing prototype for qcom_scm_is_available()
  qcom-scm: fix endianess issue in __qcom_scm_is_call_available
  soc: qcom: smd: Reject send of too big packets
  soc: qcom: smd: Handle big endian CPUs
  ...
This commit is contained in:
Linus Torvalds 2015-11-10 15:00:03 -08:00
commit b44a3d2a85
54 changed files with 4467 additions and 393 deletions
Download patch file Download diff file Expand all files Collapse all files

188
Documentation/devicetree/bindings/arm/arm,scpi.txt Normal file
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@ -0,0 +1,188 @@
System Control and Power Interface (SCPI) Message Protocol
----------------------------------------------------------
Firmware implementing the SCPI described in ARM document number ARM DUI 0922B
("ARM Compute Subsystem SCP: Message Interface Protocols")[0] can be used
by Linux to initiate various system control and power operations.
Required properties:
- compatible : should be "arm,scpi"
- mboxes: List of phandle and mailbox channel specifiers
All the channels reserved by remote SCP firmware for use by
SCPI message protocol should be specified in any order
- shmem : List of phandle pointing to the shared memory(SHM) area between the
processors using these mailboxes for IPC, one for each mailbox
SHM can be any memory reserved for the purpose of this communication
between the processors.
See Documentation/devicetree/bindings/mailbox/mailbox.txt
for more details about the generic mailbox controller and
client driver bindings.
Clock bindings for the clocks based on SCPI Message Protocol
------------------------------------------------------------
This binding uses the common clock binding[1].
Container Node
==============
Required properties:
- compatible : should be "arm,scpi-clocks"
All the clocks provided by SCP firmware via SCPI message
protocol much be listed as sub-nodes under this node.
Sub-nodes
=========
Required properties:
- compatible : shall include one of the following
"arm,scpi-dvfs-clocks" - all the clocks that are variable and index based.
These clocks don't provide an entire range of values between the
limits but only discrete points within the range. The firmware
provides the mapping for each such operating frequency and the
index associated with it. The firmware also manages the
voltage scaling appropriately with the clock scaling.
"arm,scpi-variable-clocks" - all the clocks that are variable and provide full
range within the specified range. The firmware provides the
range of values within a specified range.
Other required properties for all clocks(all from common clock binding):
- #clock-cells : Should be 1. Contains the Clock ID value used by SCPI commands.
- clock-output-names : shall be the corresponding names of the outputs.
- clock-indices: The identifying number for the clocks(i.e.clock_id) in the
node. It can be non linear and hence provide the mapping of identifiers
into the clock-output-names array.
SRAM and Shared Memory for SCPI
-------------------------------
A small area of SRAM is reserved for SCPI communication between application
processors and SCP.
Required properties:
- compatible : should be "arm,juno-sram-ns" for Non-secure SRAM on Juno
The rest of the properties should follow the generic mmio-sram description
found in ../../misc/sysram.txt
Each sub-node represents the reserved area for SCPI.
Required sub-node properties:
- reg : The base offset and size of the reserved area with the SRAM
- compatible : should be "arm,juno-scp-shmem" for Non-secure SRAM based
shared memory on Juno platforms
Sensor bindings for the sensors based on SCPI Message Protocol
--------------------------------------------------------------
SCPI provides an API to access the various sensors on the SoC.
Required properties:
- compatible : should be "arm,scpi-sensors".
- #thermal-sensor-cells: should be set to 1. This property follows the
thermal device tree bindings[2].
Valid cell values are raw identifiers (Sensor
ID) as used by the firmware. Refer to
platform documentation for your
implementation for the IDs to use. For Juno
R0 and Juno R1 refer to [3].
[0] http://infocenter.arm.com/help/topic/com.arm.doc.dui0922b/index.html
[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
[2] Documentation/devicetree/bindings/thermal/thermal.txt
[3] http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.dui0922b/apas03s22.html
Example:
sram: sram@50000000 {
compatible = "arm,juno-sram-ns", "mmio-sram";
reg = <0x0 0x50000000 0x0 0x10000>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x0 0x50000000 0x10000>;
cpu_scp_lpri: scp-shmem@0 {
compatible = "arm,juno-scp-shmem";
reg = <0x0 0x200>;
};
cpu_scp_hpri: scp-shmem@200 {
compatible = "arm,juno-scp-shmem";
reg = <0x200 0x200>;
};
};
mailbox: mailbox0@40000000 {
....
#mbox-cells = <1>;
};
scpi_protocol: scpi@2e000000 {
compatible = "arm,scpi";
mboxes = <&mailbox 0 &mailbox 1>;
shmem = <&cpu_scp_lpri &cpu_scp_hpri>;
clocks {
compatible = "arm,scpi-clocks";
scpi_dvfs: scpi_clocks@0 {
compatible = "arm,scpi-dvfs-clocks";
#clock-cells = <1>;
clock-indices = <0>, <1>, <2>;
clock-output-names = "atlclk", "aplclk","gpuclk";
};
scpi_clk: scpi_clocks@3 {
compatible = "arm,scpi-variable-clocks";
#clock-cells = <1>;
clock-indices = <3>, <4>;
clock-output-names = "pxlclk0", "pxlclk1";
};
};
scpi_sensors0: sensors {
compatible = "arm,scpi-sensors";
#thermal-sensor-cells = <1>;
};
};
cpu@0 {
...
reg = <0 0>;
clocks = <&scpi_dvfs 0>;
};
hdlcd@7ff60000 {
...
reg = <0 0x7ff60000 0 0x1000>;
clocks = <&scpi_clk 4>;
};
thermal-zones {
soc_thermal {
polling-delay-passive = <100>;
polling-delay = <1000>;
/* sensor ID */
thermal-sensors = <&scpi_sensors0 3>;
...
};
};
In the above example, the #clock-cells is set to 1 as required.
scpi_dvfs has 3 output clocks namely: atlclk, aplclk, and gpuclk with 0,
1 and 2 as clock-indices. scpi_clk has 2 output clocks namely: pxlclk0
and pxlclk1 with 3 and 4 as clock-indices.
The first consumer in the example is cpu@0 and it has '0' as the clock
specifier which points to the first entry in the output clocks of
scpi_dvfs i.e. "atlclk".
Similarly the second example is hdlcd@7ff60000 and it has pxlclk1 as input
clock. '4' in the clock specifier here points to the second entry
in the output clocks of scpi_clocks i.e. "pxlclk1"
The thermal-sensors property in the soc_thermal node uses the
temperature sensor provided by SCP firmware to setup a thermal
zone. The ID "3" is the sensor identifier for the temperature sensor
as used by the firmware.

6
Documentation/devicetree/bindings/arm/psci.txt
View file

@ -31,6 +31,10 @@ Main node required properties:
support, but are permitted to be present for compatibility with
existing software when "arm,psci" is later in the compatible list.
* "arm,psci-1.0" : for implementations complying to PSCI 1.0. PSCI 1.0 is
backward compatible with PSCI 0.2 with minor specification updates,
as defined in the PSCI specification[2].
- method : The method of calling the PSCI firmware. Permitted
values are:
@ -100,3 +104,5 @@ Case 3: PSCI v0.2 and PSCI v0.1.
[1] Kernel documentation - ARM idle states bindings
Documentation/devicetree/bindings/arm/idle-states.txt
[2] Power State Coordination Interface (PSCI) specification
http://infocenter.arm.com/help/topic/com.arm.doc.den0022c/DEN0022C_Power_State_Coordination_Interface.pdf

47
Documentation/devicetree/bindings/bus/sunxi-rsb.txt Normal file
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@ -0,0 +1,47 @@
Allwinner Reduced Serial Bus (RSB) controller
The RSB controller found on later Allwinner SoCs is an SMBus like 2 wire
serial bus with 1 master and up to 15 slaves. It is represented by a node
for the controller itself, and child nodes representing the slave devices.
Required properties :
- reg : Offset and length of the register set for the controller.
- compatible : Shall be "allwinner,sun8i-a23-rsb".
- interrupts : The interrupt line associated to the RSB controller.
- clocks : The gate clk associated to the RSB controller.
- resets : The reset line associated to the RSB controller.
- #address-cells : shall be 1
- #size-cells : shall be 0
Optional properties :
- clock-frequency : Desired RSB bus clock frequency in Hz. Maximum is 20MHz.
If not set this defaults to 3MHz.
Child nodes:
An RSB controller node can contain zero or more child nodes representing
slave devices on the bus. Child 'reg' properties should contain the slave
device's hardware address. The hardware address is hardwired in the device,
which can normally be found in the datasheet.
Example:
rsb@01f03400 {
compatible = "allwinner,sun8i-a23-rsb";
reg = <0x01f03400 0x400>;
interrupts = <0 39 4>;
clocks = <&apb0_gates 3>;
clock-frequency = <3000000>;
resets = <&apb0_rst 3>;
#address-cells = <1>;
#size-cells = <0>;
pmic@3e3 {
compatible = "...";
reg = <0x3e3>;
/* ... */
};
};

8
Documentation/devicetree/bindings/memory-controllers/arm,pl172.txt
View file

@ -1,8 +1,9 @@
* Device tree bindings for ARM PL172 MultiPort Memory Controller
* Device tree bindings for ARM PL172/PL175/PL176 MultiPort Memory Controller
Required properties:
- compatible: "arm,pl172", "arm,primecell"
- compatible: Must be "arm,primecell" and exactly one from
"arm,pl172", "arm,pl175" or "arm,pl176".
- reg: Must contains offset/length value for controller.
@ -56,7 +57,8 @@ Optional child cs node config properties:
- mpmc,extended-wait: Enable extended wait.
- mpmc,buffer-enable: Enable write buffer.
- mpmc,buffer-enable: Enable write buffer, option is not supported by
PL175 and PL176 controllers.
- mpmc,write-protect: Enable write protect.

46
Documentation/devicetree/bindings/soc/rockchip/power_domain.txt Normal file
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@ -0,0 +1,46 @@
* Rockchip Power Domains
Rockchip processors include support for multiple power domains which can be
powered up/down by software based on different application scenes to save power.
Required properties for power domain controller:
- compatible: Should be one of the following.
"rockchip,rk3288-power-controller" - for RK3288 SoCs.
- #power-domain-cells: Number of cells in a power-domain specifier.
Should be 1 for multiple PM domains.
- #address-cells: Should be 1.
- #size-cells: Should be 0.
Required properties for power domain sub nodes:
- reg: index of the power domain, should use macros in:
"include/dt-bindings/power/rk3288-power.h" - for RK3288 type power domain.
- clocks (optional): phandles to clocks which need to be enabled while power domain
switches state.
Example:
power: power-controller {
compatible = "rockchip,rk3288-power-controller";
#power-domain-cells = <1>;
#address-cells = <1>;
#size-cells = <0>;
pd_gpu {
reg = <RK3288_PD_GPU>;
clocks = <&cru ACLK_GPU>;
};
};
Node of a device using power domains must have a power-domains property,
containing a phandle to the power device node and an index specifying which
power domain to use.
The index should use macros in:
"include/dt-bindings/power/rk3288-power.h" - for rk3288 type power domain.
Example of the node using power domain:
node {
/* ... */
power-domains = <&power RK3288_PD_GPU>;
/* ... */
};

33
Documentation/hwmon/scpi-hwmon Normal file
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@ -0,0 +1,33 @@
Kernel driver scpi-hwmon
========================
Supported chips:
* Chips based on ARM System Control Processor Interface
Addresses scanned: -
Datasheet: http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.dui0922b/index.html
Author: Punit Agrawal <punit.agrawal@arm.com>
Description
-----------
This driver supports hardware monitoring for SoC's based on the ARM
System Control Processor (SCP) implementing the System Control
Processor Interface (SCPI). The following sensor types are supported
by the SCP -
* temperature
* voltage
* current
* power
The SCP interface provides an API to query the available sensors and
their values which are then exported to userspace by this driver.
Usage Notes
-----------
The driver relies on device tree node to indicate the presence of SCPI
support in the kernel. See
Documentation/devicetree/bindings/arm/arm,scpi.txt for details of the
devicetree node.

10
MAINTAINERS
View file

@ -9362,6 +9362,16 @@ W: http://www.sunplus.com
S: Supported
F: arch/score/
SYSTEM CONTROL & POWER INTERFACE (SCPI) Message Protocol drivers
M: Sudeep Holla <sudeep.holla@arm.com>
L: linux-arm-kernel@lists.infradead.org
S: Maintained
F: Documentation/devicetree/bindings/arm/arm,scpi.txt
F: drivers/clk/clk-scpi.c
F: drivers/cpufreq/scpi-cpufreq.c
F: drivers/firmware/arm_scpi.c
F: include/linux/scpi_protocol.h
SCSI CDROM DRIVER
M: Jens Axboe <axboe@kernel.dk>
L: linux-scsi@vger.kernel.org

17
arch/arm/boot/dts/qcom-msm8974.dtsi
View file

@ -100,6 +100,15 @@
clock-frequency = <19200000>;
};
smem {
compatible = "qcom,smem";
memory-region = <&smem_region>;
qcom,rpm-msg-ram = <&rpm_msg_ram>;
hwlocks = <&tcsr_mutex 3>;
};
soc: soc {
#address-cells = <1>;
#size-cells = <1>;
@ -250,13 +259,9 @@
#hwlock-cells = <1>;
};
smem@fa00000 {
compatible = "qcom,smem";
memory-region = <&smem_region>;
rpm_msg_ram: memory@fc428000 {
compatible = "qcom,rpm-msg-ram";
reg = <0xfc428000 0x4000>;
hwlocks = <&tcsr_mutex 3>;
};
blsp1_uart2: serial@f991e000 {

14
arch/arm64/kernel/psci.c
View file

@ -30,20 +30,6 @@
#include <asm/smp_plat.h>
#include <asm/suspend.h>
static bool psci_power_state_loses_context(u32 state)
{
return state & PSCI_0_2_POWER_STATE_TYPE_MASK;
}
static bool psci_power_state_is_valid(u32 state)
{
const u32 valid_mask = PSCI_0_2_POWER_STATE_ID_MASK |
PSCI_0_2_POWER_STATE_TYPE_MASK |
PSCI_0_2_POWER_STATE_AFFL_MASK;
return !(state & ~valid_mask);
}
static DEFINE_PER_CPU_READ_MOSTLY(u32 *, psci_power_state);
static int __maybe_unused cpu_psci_cpu_init_idle(unsigned int cpu)

6
drivers/base/power/clock_ops.c
View file

@ -93,7 +93,7 @@ static int __pm_clk_add(struct device *dev, const char *con_id,
return -ENOMEM;
}
} else {
if (IS_ERR(clk) || !__clk_get(clk)) {
if (IS_ERR(clk)) {
kfree(ce);
return -ENOENT;
}
@ -127,7 +127,9 @@ int pm_clk_add(struct device *dev, const char *con_id)
* @clk: Clock pointer
*
* Add the clock to the list of clocks used for the power management of @dev.
* It will increment refcount on clock pointer, use clk_put() on it when done.
* The power-management code will take control of the clock reference, so
* callers should not call clk_put() on @clk after this function sucessfully
* returned.
*/
int pm_clk_add_clk(struct device *dev, struct clk *clk)
{

11
drivers/bus/Kconfig
View file

@ -120,6 +120,17 @@ config SIMPLE_PM_BUS
Controller (BSC, sometimes called "LBSC within Bus Bridge", or
"External Bus Interface") as found on several Renesas ARM SoCs.
config SUNXI_RSB
tristate "Allwinner sunXi Reduced Serial Bus Driver"
default MACH_SUN8I || MACH_SUN9I
depends on ARCH_SUNXI
select REGMAP
help
Say y here to enable support for Allwinner's Reduced Serial Bus
(RSB) support. This controller is responsible for communicating
with various RSB based devices, such as AXP223, AXP8XX PMICs,
and AC100/AC200 ICs.
config VEXPRESS_CONFIG
bool "Versatile Express configuration bus"
default y if ARCH_VEXPRESS

1
drivers/bus/Makefile
View file

@ -15,5 +15,6 @@ obj-$(CONFIG_MVEBU_MBUS) += mvebu-mbus.o
obj-$(CONFIG_OMAP_INTERCONNECT) += omap_l3_smx.o omap_l3_noc.o
obj-$(CONFIG_OMAP_OCP2SCP) += omap-ocp2scp.o
obj-$(CONFIG_SUNXI_RSB) += sunxi-rsb.o
obj-$(CONFIG_SIMPLE_PM_BUS) += simple-pm-bus.o
obj-$(CONFIG_VEXPRESS_CONFIG) += vexpress-config.o

783
drivers/bus/sunxi-rsb.c Normal file
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@ -0,0 +1,783 @@
/*
* RSB (Reduced Serial Bus) driver.
*
* Author: Chen-Yu Tsai <wens@csie.org>
*
* This file is licensed under the terms of the GNU General Public License
* version 2. This program is licensed "as is" without any warranty of any
* kind, whether express or implied.
*
* The RSB controller looks like an SMBus controller which only supports
* byte and word data transfers. But, it differs from standard SMBus
* protocol on several aspects:
* - it uses addresses set at runtime to address slaves. Runtime addresses
* are sent to slaves using their 12bit hardware addresses. Up to 15
* runtime addresses are available.
* - it adds a parity bit every 8bits of data and address for read and
* write accesses; this replaces the ack bit
* - only one read access is required to read a byte (instead of a write
* followed by a read access in standard SMBus protocol)
* - there's no Ack bit after each read access
*
* This means this bus cannot be used to interface with standard SMBus
* devices. Devices known to support this interface include the AXP223,
* AXP809, and AXP806 PMICs, and the AC100 audio codec, all from X-Powers.
*
* A description of the operation and wire protocol can be found in the
* RSB section of Allwinner's A80 user manual, which can be found at
*
* https://github.com/allwinner-zh/documents/tree/master/A80
*
* This document is officially released by Allwinner.
*
* This driver is based on i2c-sun6i-p2wi.c, the P2WI bus driver.
*
*/
#include <linux/clk.h>
#include <linux/clk/clk-conf.h>
#include <linux/device.h>
#include <linux/interrupt.h>
#include <linux/io.h>
#include <linux/iopoll.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/of_irq.h>
#include <linux/of_platform.h>
#include <linux/platform_device.h>
#include <linux/regmap.h>
#include <linux/reset.h>
#include <linux/slab.h>
#include <linux/sunxi-rsb.h>
#include <linux/types.h>
/* RSB registers */
#define RSB_CTRL 0x0 /* Global control */
#define RSB_CCR 0x4 /* Clock control */
#define RSB_INTE 0x8 /* Interrupt controls */
#define RSB_INTS 0xc /* Interrupt status */
#define RSB_ADDR 0x10 /* Address to send with read/write command */
#define RSB_DATA 0x1c /* Data to read/write */
#define RSB_LCR 0x24 /* Line control */
#define RSB_DMCR 0x28 /* Device mode (init) control */
#define RSB_CMD 0x2c /* RSB Command */
#define RSB_DAR 0x30 /* Device address / runtime address */
/* CTRL fields */
#define RSB_CTRL_START_TRANS BIT(7)
#define RSB_CTRL_ABORT_TRANS BIT(6)
#define RSB_CTRL_GLOBAL_INT_ENB BIT(1)
#define RSB_CTRL_SOFT_RST BIT(0)
/* CLK CTRL fields */
#define RSB_CCR_SDA_OUT_DELAY(v) (((v) & 0x7) << 8)
#define RSB_CCR_MAX_CLK_DIV 0xff
#define RSB_CCR_CLK_DIV(v) ((v) & RSB_CCR_MAX_CLK_DIV)
/* STATUS fields */
#define RSB_INTS_TRANS_ERR_ACK BIT(16)
#define RSB_INTS_TRANS_ERR_DATA_BIT(v) (((v) >> 8) & 0xf)
#define RSB_INTS_TRANS_ERR_DATA GENMASK(11, 8)
#define RSB_INTS_LOAD_BSY BIT(2)
#define RSB_INTS_TRANS_ERR BIT(1)
#define RSB_INTS_TRANS_OVER BIT(0)
/* LINE CTRL fields*/
#define RSB_LCR_SCL_STATE BIT(5)
#define RSB_LCR_SDA_STATE BIT(4)
#define RSB_LCR_SCL_CTL BIT(3)
#define RSB_LCR_SCL_CTL_EN BIT(2)
#define RSB_LCR_SDA_CTL BIT(1)
#define RSB_LCR_SDA_CTL_EN BIT(0)
/* DEVICE MODE CTRL field values */
#define RSB_DMCR_DEVICE_START BIT(31)
#define RSB_DMCR_MODE_DATA (0x7c << 16)
#define RSB_DMCR_MODE_REG (0x3e << 8)
#define RSB_DMCR_DEV_ADDR 0x00
/* CMD values */
#define RSB_CMD_RD8 0x8b
#define RSB_CMD_RD16 0x9c
#define RSB_CMD_RD32 0xa6
#define RSB_CMD_WR8 0x4e
#define RSB_CMD_WR16 0x59
#define RSB_CMD_WR32 0x63
#define RSB_CMD_STRA 0xe8
/* DAR fields */
#define RSB_DAR_RTA(v) (((v) & 0xff) << 16)
#define RSB_DAR_DA(v) ((v) & 0xffff)
#define RSB_MAX_FREQ 20000000
#define RSB_CTRL_NAME "sunxi-rsb"
struct sunxi_rsb_addr_map {
u16 hwaddr;
u8 rtaddr;
};
struct sunxi_rsb {
struct device *dev;
void __iomem *regs;
struct clk *clk;
struct reset_control *rstc;
struct completion complete;
struct mutex lock;
unsigned int status;
};
/* bus / slave device related functions */
static struct bus_type sunxi_rsb_bus;
static int sunxi_rsb_device_match(struct device *dev, struct device_driver *drv)
{
return of_driver_match_device(dev, drv);
}
static int sunxi_rsb_device_probe(struct device *dev)
{
const struct sunxi_rsb_driver *drv = to_sunxi_rsb_driver(dev->driver);
struct sunxi_rsb_device *rdev = to_sunxi_rsb_device(dev);
int ret;
if (!drv->probe)
return -ENODEV;
if (!rdev->irq) {
int irq = -ENOENT;
if (dev->of_node)
irq = of_irq_get(dev->of_node, 0);
if (irq == -EPROBE_DEFER)
return irq;
if (irq < 0)
irq = 0;
rdev->irq = irq;
}
ret = of_clk_set_defaults(dev->of_node, false);
if (ret < 0)
return ret;
return drv->probe(rdev);
}
static int sunxi_rsb_device_remove(struct device *dev)
{
const struct sunxi_rsb_driver *drv = to_sunxi_rsb_driver(dev->driver);
return drv->remove(to_sunxi_rsb_device(dev));
}
static struct bus_type sunxi_rsb_bus = {
.name = RSB_CTRL_NAME,
.match = sunxi_rsb_device_match,
.probe = sunxi_rsb_device_probe,
.remove = sunxi_rsb_device_remove,
};
static void sunxi_rsb_dev_release(struct device *dev)
{
struct sunxi_rsb_device *rdev = to_sunxi_rsb_device(dev);
kfree(rdev);
}
/**
* sunxi_rsb_device_create() - allocate and add an RSB device
* @rsb: RSB controller
* @node: RSB slave device node
* @hwaddr: RSB slave hardware address
* @rtaddr: RSB slave runtime address
*/
static struct sunxi_rsb_device *sunxi_rsb_device_create(struct sunxi_rsb *rsb,
struct device_node *node, u16 hwaddr, u8 rtaddr)
{
int err;
struct sunxi_rsb_device *rdev;
rdev = kzalloc(sizeof(*rdev), GFP_KERNEL);
if (!rdev)
return ERR_PTR(-ENOMEM);
rdev->rsb = rsb;
rdev->hwaddr = hwaddr;
rdev->rtaddr = rtaddr;
rdev->dev.bus = &sunxi_rsb_bus;
rdev->dev.parent = rsb->dev;
rdev->dev.of_node = node;
rdev->dev.release = sunxi_rsb_dev_release;
dev_set_name(&rdev->dev, "%s-%x", RSB_CTRL_NAME, hwaddr);
err = device_register(&rdev->dev);
if (err < 0) {
dev_err(&rdev->dev, "Can't add %s, status %d\n",
dev_name(&rdev->dev), err);
goto err_device_add;
}
dev_dbg(&rdev->dev, "device %s registered\n", dev_name(&rdev->dev));
err_device_add:
put_device(&rdev->dev);
return ERR_PTR(err);
}
/**
* sunxi_rsb_device_unregister(): unregister an RSB device
* @rdev: rsb_device to be removed
*/
static void sunxi_rsb_device_unregister(struct sunxi_rsb_device *rdev)
{
device_unregister(&rdev->dev);
}
static int sunxi_rsb_remove_devices(struct device *dev, void *data)
{
struct sunxi_rsb_device *rdev = to_sunxi_rsb_device(dev);
if (dev->bus == &sunxi_rsb_bus)
sunxi_rsb_device_unregister(rdev);
return 0;
}
/**
* sunxi_rsb_driver_register() - Register device driver with RSB core
* @rdrv: device driver to be associated with slave-device.
*
* This API will register the client driver with the RSB framework.
* It is typically called from the driver's module-init function.
*/
int sunxi_rsb_driver_register(struct sunxi_rsb_driver *rdrv)
{
rdrv->driver.bus = &sunxi_rsb_bus;
return driver_register(&rdrv->driver);
}
EXPORT_SYMBOL_GPL(sunxi_rsb_driver_register);
/* common code that starts a transfer */
static int _sunxi_rsb_run_xfer(struct sunxi_rsb *rsb)
{
if (readl(rsb->regs + RSB_CTRL) & RSB_CTRL_START_TRANS) {
dev_dbg(rsb->dev, "RSB transfer still in progress\n");
return -EBUSY;
}
reinit_completion(&rsb->complete);
writel(RSB_INTS_LOAD_BSY | RSB_INTS_TRANS_ERR | RSB_INTS_TRANS_OVER,
rsb->regs + RSB_INTE);
writel(RSB_CTRL_START_TRANS | RSB_CTRL_GLOBAL_INT_ENB,
rsb->regs + RSB_CTRL);
if (!wait_for_completion_io_timeout(&rsb->complete,
msecs_to_jiffies(100))) {
dev_dbg(rsb->dev, "RSB timeout\n");
/* abort the transfer */
writel(RSB_CTRL_ABORT_TRANS, rsb->regs + RSB_CTRL);
/* clear any interrupt flags */
writel(readl(rsb->regs + RSB_INTS), rsb->regs + RSB_INTS);
return -ETIMEDOUT;
}
if (rsb->status & RSB_INTS_LOAD_BSY) {
dev_dbg(rsb->dev, "RSB busy\n");
return -EBUSY;
}
if (rsb->status & RSB_INTS_TRANS_ERR) {
if (rsb->status & RSB_INTS_TRANS_ERR_ACK) {
dev_dbg(rsb->dev, "RSB slave nack\n");
return -EINVAL;
}
if (rsb->status & RSB_INTS_TRANS_ERR_DATA) {
dev_dbg(rsb->dev, "RSB transfer data error\n");
return -EIO;
}
}
return 0;
}
static int sunxi_rsb_read(struct sunxi_rsb *rsb, u8 rtaddr, u8 addr,
u32 *buf, size_t len)
{
u32 cmd;
int ret;
if (!buf)
return -EINVAL;
switch (len) {
case 1:
cmd = RSB_CMD_RD8;
break;
case 2:
cmd = RSB_CMD_RD16;
break;
case 4:
cmd = RSB_CMD_RD32;
break;
default:
dev_err(rsb->dev, "Invalid access width: %d\n", len);
return -EINVAL;
}
mutex_lock(&rsb->lock);
writel(addr, rsb->regs + RSB_ADDR);
writel(RSB_DAR_RTA(rtaddr), rsb->regs + RSB_DAR);
writel(cmd, rsb->regs + RSB_CMD);
ret = _sunxi_rsb_run_xfer(rsb);
if (ret)
goto out;
*buf = readl(rsb->regs + RSB_DATA);
mutex_unlock(&rsb->lock);
out:
return ret;
}
static int sunxi_rsb_write(struct sunxi_rsb *rsb, u8 rtaddr, u8 addr,
const u32 *buf, size_t len)
{
u32 cmd;
int ret;
if (!buf)
return -EINVAL;
switch (len) {
case 1:
cmd = RSB_CMD_WR8;
break;
case 2:
cmd = RSB_CMD_WR16;
break;
case 4:
cmd = RSB_CMD_WR32;
break;
default:
dev_err(rsb->dev, "Invalid access width: %d\n", len);
return -EINVAL;
}
mutex_lock(&rsb->lock);
writel(addr, rsb->regs + RSB_ADDR);
writel(RSB_DAR_RTA(rtaddr), rsb->regs + RSB_DAR);
writel(*buf, rsb->regs + RSB_DATA);
writel(cmd, rsb->regs + RSB_CMD);
ret = _sunxi_rsb_run_xfer(rsb);
mutex_unlock(&rsb->lock);
return ret;
}
/* RSB regmap functions */
struct sunxi_rsb_ctx {
struct sunxi_rsb_device *rdev;
int size;
};
static int regmap_sunxi_rsb_reg_read(void *context, unsigned int reg,
unsigned int *val)
{
struct sunxi_rsb_ctx *ctx = context;
struct sunxi_rsb_device *rdev = ctx->rdev;
if (reg > 0xff)
return -EINVAL;
return sunxi_rsb_read(rdev->rsb, rdev->rtaddr, reg, val, ctx->size);
}
static int regmap_sunxi_rsb_reg_write(void *context, unsigned int reg,
unsigned int val)
{
struct sunxi_rsb_ctx *ctx = context;
struct sunxi_rsb_device *rdev = ctx->rdev;
return sunxi_rsb_write(rdev->rsb, rdev->rtaddr, reg, &val, ctx->size);
}
static void regmap_sunxi_rsb_free_ctx(void *context)
{
struct sunxi_rsb_ctx *ctx = context;
kfree(ctx);
}
static struct regmap_bus regmap_sunxi_rsb = {
.reg_write = regmap_sunxi_rsb_reg_write,
.reg_read = regmap_sunxi_rsb_reg_read,
.free_context = regmap_sunxi_rsb_free_ctx,
.reg_format_endian_default = REGMAP_ENDIAN_NATIVE,
.val_format_endian_default = REGMAP_ENDIAN_NATIVE,
};
static struct sunxi_rsb_ctx *regmap_sunxi_rsb_init_ctx(struct sunxi_rsb_device *rdev,
const struct regmap_config *config)
{
struct sunxi_rsb_ctx *ctx;
switch (config->val_bits) {
case 8:
case 16:
case 32:
break;
default:
return ERR_PTR(-EINVAL);
}
ctx = kzalloc(sizeof(*ctx), GFP_KERNEL);
if (!ctx)
return ERR_PTR(-ENOMEM);
ctx->rdev = rdev;
ctx->size = config->val_bits / 8;
return ctx;
}
struct regmap *__devm_regmap_init_sunxi_rsb(struct sunxi_rsb_device *rdev,
const struct regmap_config *config,
struct lock_class_key *lock_key,
const char *lock_name)
{
struct sunxi_rsb_ctx *ctx = regmap_sunxi_rsb_init_ctx(rdev, config);
if (IS_ERR(ctx))
return ERR_CAST(ctx);
return __devm_regmap_init(&rdev->dev, &regmap_sunxi_rsb, ctx, config,
lock_key, lock_name);
}
EXPORT_SYMBOL_GPL(__devm_regmap_init_sunxi_rsb);
/* RSB controller driver functions */
static irqreturn_t sunxi_rsb_irq(int irq, void *dev_id)
{
struct sunxi_rsb *rsb = dev_id;
u32 status;
status = readl(rsb->regs + RSB_INTS);
rsb->status = status;
/* Clear interrupts */
status &= (RSB_INTS_LOAD_BSY | RSB_INTS_TRANS_ERR |
RSB_INTS_TRANS_OVER);
writel(status, rsb->regs + RSB_INTS);
complete(&rsb->complete);
return IRQ_HANDLED;
}
static int sunxi_rsb_init_device_mode(struct sunxi_rsb *rsb)
{
int ret = 0;
u32 reg;
/* send init sequence */
writel(RSB_DMCR_DEVICE_START | RSB_DMCR_MODE_DATA |
RSB_DMCR_MODE_REG | RSB_DMCR_DEV_ADDR, rsb->regs + RSB_DMCR);
readl_poll_timeout(rsb->regs + RSB_DMCR, reg,
!(reg & RSB_DMCR_DEVICE_START), 100, 250000);
if (reg & RSB_DMCR_DEVICE_START)
ret = -ETIMEDOUT;
/* clear interrupt status bits */
writel(readl(rsb->regs + RSB_INTS), rsb->regs + RSB_INTS);
return ret;
}
/*
* There are 15 valid runtime addresses, though Allwinner typically
* skips the first, for unknown reasons, and uses the following three.
*
* 0x17, 0x2d, 0x3a, 0x4e, 0x59, 0x63, 0x74, 0x8b,
* 0x9c, 0xa6, 0xb1, 0xc5, 0xd2, 0xe8, 0xff
*
* No designs with 2 RSB slave devices sharing identical hardware
* addresses on the same bus have been seen in the wild. All designs
* use 0x2d for the primary PMIC, 0x3a for the secondary PMIC if
* there is one, and 0x45 for peripheral ICs.
*
* The hardware does not seem to support re-setting runtime addresses.
* Attempts to do so result in the slave devices returning a NACK.
* Hence we just hardcode the mapping here, like Allwinner does.
*/
static const struct sunxi_rsb_addr_map sunxi_rsb_addr_maps[] = {
{ 0x3e3, 0x2d }, /* Primary PMIC: AXP223, AXP809, AXP81X, ... */
{ 0x745, 0x3a }, /* Secondary PMIC: AXP806, ... */
{ 0xe89, 0x45 }, /* Peripheral IC: AC100, ... */
};
static u8 sunxi_rsb_get_rtaddr(u16 hwaddr)
{
int i;
for (i = 0; i < ARRAY_SIZE(sunxi_rsb_addr_maps); i++)
if (hwaddr == sunxi_rsb_addr_maps[i].hwaddr)
return sunxi_rsb_addr_maps[i].rtaddr;
return 0; /* 0 is an invalid runtime address */
}
static int of_rsb_register_devices(struct sunxi_rsb *rsb)
{
struct device *dev = rsb->dev;
struct device_node *child, *np = dev->of_node;
u32 hwaddr;
u8 rtaddr;
int ret;
if (!np)
return -EINVAL;
/* Runtime addresses for all slaves should be set first */
for_each_available_child_of_node(np, child) {
dev_dbg(dev, "setting child %s runtime address\n",
child->full_name);
ret = of_property_read_u32(child, "reg", &hwaddr);
if (ret) {
dev_err(dev, "%s: invalid 'reg' property: %d\n",
child->full_name, ret);
continue;
}
rtaddr = sunxi_rsb_get_rtaddr(hwaddr);
if (!rtaddr) {
dev_err(dev, "%s: unknown hardware device address\n",
child->full_name);
continue;
}
/*
* Since no devices have been registered yet, we are the
* only ones using the bus, we can skip locking the bus.
*/
/* setup command parameters */
writel(RSB_CMD_STRA, rsb->regs + RSB_CMD);
writel(RSB_DAR_RTA(rtaddr) | RSB_DAR_DA(hwaddr),
rsb->regs + RSB_DAR);
/* send command */
ret = _sunxi_rsb_run_xfer(rsb);
if (ret)
dev_warn(dev, "%s: set runtime address failed: %d\n",
child->full_name, ret);
}
/* Then we start adding devices and probing them */
for_each_available_child_of_node(np, child) {
struct sunxi_rsb_device *rdev;
dev_dbg(dev, "adding child %s\n", child->full_name);
ret = of_property_read_u32(child, "reg", &hwaddr);
if (ret)
continue;
rtaddr = sunxi_rsb_get_rtaddr(hwaddr);
if (!rtaddr)
continue;
rdev = sunxi_rsb_device_create(rsb, child, hwaddr, rtaddr);
if (IS_ERR(rdev))
dev_err(dev, "failed to add child device %s: %ld\n",
child->full_name, PTR_ERR(rdev));
}
return 0;
}
static const struct of_device_id sunxi_rsb_of_match_table[] = {
{ .compatible = "allwinner,sun8i-a23-rsb" },
{}
};
MODULE_DEVICE_TABLE(of, sunxi_rsb_of_match_table);
static int sunxi_rsb_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
struct device_node *np = dev->of_node;
struct resource *r;
struct sunxi_rsb *rsb;
unsigned long p_clk_freq;
u32 clk_delay, clk_freq = 3000000;
int clk_div, irq, ret;
u32 reg;
of_property_read_u32(np, "clock-frequency", &clk_freq);
if (clk_freq > RSB_MAX_FREQ) {
dev_err(dev,
"clock-frequency (%u Hz) is too high (max = 20MHz)\n",
clk_freq);
return -EINVAL;
}
rsb = devm_kzalloc(dev, sizeof(*rsb), GFP_KERNEL);
if (!rsb)
return -ENOMEM;
rsb->dev = dev;
platform_set_drvdata(pdev, rsb);
r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
rsb->regs = devm_ioremap_resource(dev, r);
if (IS_ERR(rsb->regs))
return PTR_ERR(rsb->regs);
irq = platform_get_irq(pdev, 0);
if (irq < 0) {
dev_err(dev, "failed to retrieve irq: %d\n", irq);
return irq;
}
rsb->clk = devm_clk_get(dev, NULL);
if (IS_ERR(rsb->clk)) {
ret = PTR_ERR(rsb->clk);
dev_err(dev, "failed to retrieve clk: %d\n", ret);
return ret;
}
ret = clk_prepare_enable(rsb->clk);
if (ret) {
dev_err(dev, "failed to enable clk: %d\n", ret);
return ret;
}
p_clk_freq = clk_get_rate(rsb->clk);
rsb->rstc = devm_reset_control_get(dev, NULL);
if (IS_ERR(rsb->rstc)) {
ret = PTR_ERR(rsb->rstc);
dev_err(dev, "failed to retrieve reset controller: %d\n", ret);
goto err_clk_disable;
}
ret = reset_control_deassert(rsb->rstc);
if (ret) {
dev_err(dev, "failed to deassert reset line: %d\n", ret);
goto err_clk_disable;
}
init_completion(&rsb->complete);
mutex_init(&rsb->lock);
/* reset the controller */
writel(RSB_CTRL_SOFT_RST, rsb->regs + RSB_CTRL);
readl_poll_timeout(rsb->regs + RSB_CTRL, reg,
!(reg & RSB_CTRL_SOFT_RST), 1000, 100000);
/*
* Clock frequency and delay calculation code is from
* Allwinner U-boot sources.
*
* From A83 user manual:
* bus clock frequency = parent clock frequency / (2 * (divider + 1))
*/
clk_div = p_clk_freq / clk_freq / 2;
if (!clk_div)
clk_div = 1;
else if (clk_div > RSB_CCR_MAX_CLK_DIV + 1)
clk_div = RSB_CCR_MAX_CLK_DIV + 1;
clk_delay = clk_div >> 1;
if (!clk_delay)
clk_delay = 1;
dev_info(dev, "RSB running at %lu Hz\n", p_clk_freq / clk_div / 2);
writel(RSB_CCR_SDA_OUT_DELAY(clk_delay) | RSB_CCR_CLK_DIV(clk_div - 1),
rsb->regs + RSB_CCR);
ret = devm_request_irq(dev, irq, sunxi_rsb_irq, 0, RSB_CTRL_NAME, rsb);
if (ret) {
dev_err(dev, "can't register interrupt handler irq %d: %d\n",
irq, ret);
goto err_reset_assert;
}
/* initialize all devices on the bus into RSB mode */
ret = sunxi_rsb_init_device_mode(rsb);
if (ret)
dev_warn(dev, "Initialize device mode failed: %d\n", ret);
of_rsb_register_devices(rsb);
return 0;
err_reset_assert:
reset_control_assert(rsb->rstc);
err_clk_disable:
clk_disable_unprepare(rsb->clk);
return ret;
}
static int sunxi_rsb_remove(struct platform_device *pdev)
{
struct sunxi_rsb *rsb = platform_get_drvdata(pdev);
device_for_each_child(rsb->dev, NULL, sunxi_rsb_remove_devices);
reset_control_assert(rsb->rstc);
clk_disable_unprepare(rsb->clk);
return 0;
}
static struct platform_driver sunxi_rsb_driver = {
.probe = sunxi_rsb_probe,
.remove = sunxi_rsb_remove,
.driver = {
.name = RSB_CTRL_NAME,
.of_match_table = sunxi_rsb_of_match_table,
},
};
static int __init sunxi_rsb_init(void)
{
int ret;
ret = bus_register(&sunxi_rsb_bus);
if (ret) {
pr_err("failed to register sunxi sunxi_rsb bus: %d\n", ret);
return ret;
}
return platform_driver_register(&sunxi_rsb_driver);
}
module_init(sunxi_rsb_init);
static void __exit sunxi_rsb_exit(void)
{
platform_driver_unregister(&sunxi_rsb_driver);
bus_unregister(&sunxi_rsb_bus);
}
module_exit(sunxi_rsb_exit);
MODULE_AUTHOR("Chen-Yu Tsai <wens@csie.org>");
MODULE_DESCRIPTION("Allwinner sunXi Reduced Serial Bus controller driver");
MODULE_LICENSE("GPL v2");

10
drivers/clk/Kconfig
View file

@ -60,6 +60,16 @@ config COMMON_CLK_RK808
clocked at 32KHz each. Clkout1 is always on, Clkout2 can off
by control register.
config COMMON_CLK_SCPI
tristate "Clock driver controlled via SCPI interface"
depends on ARM_SCPI_PROTOCOL || COMPILE_TEST
---help---
This driver provides support for clocks that are controlled
by firmware that implements the SCPI interface.
This driver uses SCPI Message Protocol to interact with the
firmware providing all the clock controls.
config COMMON_CLK_SI5351
tristate "Clock driver for SiLabs 5351A/B/C"
depends on I2C

1
drivers/clk/Makefile
View file

@ -36,6 +36,7 @@ obj-$(CONFIG_COMMON_CLK_PALMAS) += clk-palmas.o
obj-$(CONFIG_CLK_QORIQ) += clk-qoriq.o
obj-$(CONFIG_COMMON_CLK_RK808) += clk-rk808.o
obj-$(CONFIG_COMMON_CLK_S2MPS11) += clk-s2mps11.o
obj-$(CONFIG_COMMON_CLK_SCPI) += clk-scpi.o
obj-$(CONFIG_COMMON_CLK_SI5351) += clk-si5351.o
obj-$(CONFIG_COMMON_CLK_SI514) += clk-si514.o
obj-$(CONFIG_COMMON_CLK_SI570) += clk-si570.o

14
drivers/clk/berlin/bg2q.c
View file

@ -45,7 +45,7 @@
#define REG_SDIO0XIN_CLKCTL 0x0158
#define REG_SDIO1XIN_CLKCTL 0x015c
#define MAX_CLKS 27
#define MAX_CLKS 28
static struct clk *clks[MAX_CLKS];
static struct clk_onecell_data clk_data;
static DEFINE_SPINLOCK(lock);
@ -356,13 +356,13 @@ static void __init berlin2q_clock_setup(struct device_node *np)
gd->bit_idx, 0, &lock);
}
/*
* twdclk is derived from cpu/3
* TODO: use cpupll until cpuclk is not available
*/
/* cpuclk divider is fixed to 1 */
clks[CLKID_CPU] =
clk_register_fixed_factor(NULL, "cpu", clk_names[CPUPLL],
0, 1, 1);
/* twdclk is derived from cpu/3 */
clks[CLKID_TWD] =
clk_register_fixed_factor(NULL, "twd", clk_names[CPUPLL],
0, 1, 3);
clk_register_fixed_factor(NULL, "twd", "cpu", 0, 1, 3);
/* check for errors on leaf clocks */
for (n = 0; n < MAX_CLKS; n++) {

325
drivers/clk/clk-scpi.c Normal file
View file

@ -0,0 +1,325 @@
/*
* System Control and Power Interface (SCPI) Protocol based clock driver
*
* Copyright (C) 2015 ARM Ltd.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
* version 2, as published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program. If not, see <http://www.gnu.org/licenses/>.
*/
#include <linux/clk-provider.h>
#include <linux/device.h>
#include <linux/err.h>
#include <linux/of.h>
#include <linux/module.h>
#include <linux/of_platform.h>
#include <linux/platform_device.h>
#include <linux/scpi_protocol.h>
struct scpi_clk {
u32 id;
struct clk_hw hw;
struct scpi_dvfs_info *info;
struct scpi_ops *scpi_ops;
};
#define to_scpi_clk(clk) container_of(clk, struct scpi_clk, hw)
static struct platform_device *cpufreq_dev;
static unsigned long scpi_clk_recalc_rate(struct clk_hw *hw,
unsigned long parent_rate)
{
struct scpi_clk *clk = to_scpi_clk(hw);
return clk->scpi_ops->clk_get_val(clk->id);
}
static long scpi_clk_round_rate(struct clk_hw *hw, unsigned long rate,
unsigned long *parent_rate)
{
/*
* We can't figure out what rate it will be, so just return the
* rate back to the caller. scpi_clk_recalc_rate() will be called
* after the rate is set and we'll know what rate the clock is
* running at then.
*/
return rate;
}
static int scpi_clk_set_rate(struct clk_hw *hw, unsigned long rate,
unsigned long parent_rate)
{
struct scpi_clk *clk = to_scpi_clk(hw);
return clk->scpi_ops->clk_set_val(clk->id, rate);
}
static const struct clk_ops scpi_clk_ops = {
.recalc_rate = scpi_clk_recalc_rate,
.round_rate = scpi_clk_round_rate,
.set_rate = scpi_clk_set_rate,
};
/* find closest match to given frequency in OPP table */
static int __scpi_dvfs_round_rate(struct scpi_clk *clk, unsigned long rate)
{
int idx;
u32 fmin = 0, fmax = ~0, ftmp;
const struct scpi_opp *opp = clk->info->opps;
for (idx = 0; idx < clk->info->count; idx++, opp++) {
ftmp = opp->freq;
if (ftmp >= (u32)rate) {
if (ftmp <= fmax)
fmax = ftmp;
break;
} else if (ftmp >= fmin) {
fmin = ftmp;
}
}
return fmax != ~0 ? fmax : fmin;
}
static unsigned long scpi_dvfs_recalc_rate(struct clk_hw *hw,
unsigned long parent_rate)
{
struct scpi_clk *clk = to_scpi_clk(hw);
int idx = clk->scpi_ops->dvfs_get_idx(clk->id);
const struct scpi_opp *opp;
if (idx < 0)
return 0;
opp = clk->info->opps + idx;
return opp->freq;
}
static long scpi_dvfs_round_rate(struct clk_hw *hw, unsigned long rate,
unsigned long *parent_rate)
{
struct scpi_clk *clk = to_scpi_clk(hw);
return __scpi_dvfs_round_rate(clk, rate);
}
static int __scpi_find_dvfs_index(struct scpi_clk *clk, unsigned long rate)
{
int idx, max_opp = clk->info->count;
const struct scpi_opp *opp = clk->info->opps;
for (idx = 0; idx < max_opp; idx++, opp++)
if (opp->freq == rate)
return idx;
return -EINVAL;
}
static int scpi_dvfs_set_rate(struct clk_hw *hw, unsigned long rate,
unsigned long parent_rate)
{
struct scpi_clk *clk = to_scpi_clk(hw);
int ret = __scpi_find_dvfs_index(clk, rate);
if (ret < 0)
return ret;
return clk->scpi_ops->dvfs_set_idx(clk->id, (u8)ret);
}
static const struct clk_ops scpi_dvfs_ops = {
.recalc_rate = scpi_dvfs_recalc_rate,
.round_rate = scpi_dvfs_round_rate,
.set_rate = scpi_dvfs_set_rate,
};
static const struct of_device_id scpi_clk_match[] = {
{ .compatible = "arm,scpi-dvfs-clocks", .data = &scpi_dvfs_ops, },
{ .compatible = "arm,scpi-variable-clocks", .data = &scpi_clk_ops, },
{}
};
static struct clk *
scpi_clk_ops_init(struct device *dev, const struct of_device_id *match,
struct scpi_clk *sclk, const char *name)
{
struct clk_init_data init;
struct clk *clk;
unsigned long min = 0, max = 0;
init.name = name;
init.flags = CLK_IS_ROOT;
init.num_parents = 0;
init.ops = match->data;
sclk->hw.init = &init;
sclk->scpi_ops = get_scpi_ops();
if (init.ops == &scpi_dvfs_ops) {
sclk->info = sclk->scpi_ops->dvfs_get_info(sclk->id);
if (IS_ERR(sclk->info))
return NULL;
} else if (init.ops == &scpi_clk_ops) {
if (sclk->scpi_ops->clk_get_range(sclk->id, &min, &max) || !max)
return NULL;
} else {
return NULL;
}
clk = devm_clk_register(dev, &sclk->hw);
if (!IS_ERR(clk) && max)
clk_hw_set_rate_range(&sclk->hw, min, max);
return clk;
}
struct scpi_clk_data {
struct scpi_clk **clk;
unsigned int clk_num;
};
static struct clk *
scpi_of_clk_src_get(struct of_phandle_args *clkspec, void *data)
{
struct scpi_clk *sclk;
struct scpi_clk_data *clk_data = data;
unsigned int idx = clkspec->args[0], count;
for (count = 0; count < clk_data->clk_num; count++) {
sclk = clk_data->clk[count];
if (idx == sclk->id)
return sclk->hw.clk;
}
return ERR_PTR(-EINVAL);
}
static int scpi_clk_add(struct device *dev, struct device_node *np,
const struct of_device_id *match)
{
struct clk **clks;
int idx, count;
struct scpi_clk_data *clk_data;
count = of_property_count_strings(np, "clock-output-names");
if (count < 0) {
dev_err(dev, "%s: invalid clock output count\n", np->name);
return -EINVAL;
}
clk_data = devm_kmalloc(dev, sizeof(*clk_data), GFP_KERNEL);
if (!clk_data)
return -ENOMEM;
clk_data->clk_num = count;
clk_data->clk = devm_kcalloc(dev, count, sizeof(*clk_data->clk),
GFP_KERNEL);
if (!clk_data->clk)
return -ENOMEM;
clks = devm_kcalloc(dev, count, sizeof(*clks), GFP_KERNEL);
if (!clks)
return -ENOMEM;
for (idx = 0; idx < count; idx++) {
struct scpi_clk *sclk;
const char *name;
u32 val;
sclk = devm_kzalloc(dev, sizeof(*sclk), GFP_KERNEL);
if (!sclk)
return -ENOMEM;
if (of_property_read_string_index(np, "clock-output-names",
idx, &name)) {
dev_err(dev, "invalid clock name @ %s\n", np->name);
return -EINVAL;
}
if (of_property_read_u32_index(np, "clock-indices",
idx, &val)) {
dev_err(dev, "invalid clock index @ %s\n", np->name);
return -EINVAL;
}
sclk->id = val;
clks[idx] = scpi_clk_ops_init(dev, match, sclk, name);
if (IS_ERR_OR_NULL(clks[idx]))
dev_err(dev, "failed to register clock '%s'\n", name);
else
dev_dbg(dev, "Registered clock '%s'\n", name);
clk_data->clk[idx] = sclk;
}
return of_clk_add_provider(np, scpi_of_clk_src_get, clk_data);
}
static int scpi_clocks_remove(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
struct device_node *child, *np = dev->of_node;
if (cpufreq_dev) {
platform_device_unregister(cpufreq_dev);
cpufreq_dev = NULL;
}
for_each_available_child_of_node(np, child)
of_clk_del_provider(np);
return 0;
}
static int scpi_clocks_probe(struct platform_device *pdev)
{
int ret;
struct device *dev = &pdev->dev;
struct device_node *child, *np = dev->of_node;
const struct of_device_id *match;
if (!get_scpi_ops())
return -ENXIO;
for_each_available_child_of_node(np, child) {
match = of_match_node(scpi_clk_match, child);
if (!match)
continue;
ret = scpi_clk_add(dev, child, match);
if (ret) {
scpi_clocks_remove(pdev);
return ret;
}
}
/* Add the virtual cpufreq device */
cpufreq_dev = platform_device_register_simple("scpi-cpufreq",
-1, NULL, 0);
if (!cpufreq_dev)
pr_warn("unable to register cpufreq device");
return 0;
}
static const struct of_device_id scpi_clocks_ids[] = {
{ .compatible = "arm,scpi-clocks", },
{}
};
MODULE_DEVICE_TABLE(of, scpi_clocks_ids);
static struct platform_driver scpi_clocks_driver = {
.driver = {
.name = "scpi_clocks",
.of_match_table = scpi_clocks_ids,
},
.probe = scpi_clocks_probe,
.remove = scpi_clocks_remove,
};
module_platform_driver(scpi_clocks_driver);
MODULE_AUTHOR("Sudeep Holla <sudeep.holla@arm.com>");
MODULE_DESCRIPTION("ARM SCPI clock driver");
MODULE_LICENSE("GPL v2");

14
drivers/clocksource/tcb_clksrc.c
View file

@ -193,10 +193,17 @@ static int __init setup_clkevents(struct atmel_tc *tc, int clk32k_divisor_idx)
struct clk *t2_clk = tc->clk[2];
int irq = tc->irq[2];
/* try to enable t2 clk to avoid future errors in mode change */
ret = clk_prepare_enable(t2_clk);
ret = clk_prepare_enable(tc->slow_clk);
if (ret)
return ret;
/* try to enable t2 clk to avoid future errors in mode change */
ret = clk_prepare_enable(t2_clk);
if (ret) {
clk_disable_unprepare(tc->slow_clk);
return ret;
}
clk_disable(t2_clk);
clkevt.regs = tc->regs;
@ -208,7 +215,8 @@ static int __init setup_clkevents(struct atmel_tc *tc, int clk32k_divisor_idx)
ret = request_irq(irq, ch2_irq, IRQF_TIMER, "tc_clkevt", &clkevt);
if (ret) {
clk_disable_unprepare(t2_clk);
clk_unprepare(t2_clk);
clk_disable_unprepare(tc->slow_clk);
return ret;
}

31
drivers/clocksource/timer-atmel-st.c
View file

@ -22,6 +22,7 @@
#include <linux/kernel.h>
#include <linux/interrupt.h>
#include <linux/irq.h>
#include <linux/clk.h>
#include <linux/clockchips.h>
#include <linux/export.h>
#include <linux/mfd/syscon.h>
@ -33,9 +34,7 @@ static unsigned long last_crtr;
static u32 irqmask;
static struct clock_event_device clkevt;
static struct regmap *regmap_st;
#define AT91_SLOW_CLOCK 32768
#define RM9200_TIMER_LATCH ((AT91_SLOW_CLOCK + HZ/2) / HZ)
static int timer_latch;
/*
* The ST_CRTR is updated asynchronously to the master clock ... but
@ -82,8 +81,8 @@ static irqreturn_t at91rm9200_timer_interrupt(int irq, void *dev_id)
if (sr & AT91_ST_PITS) {
u32 crtr = read_CRTR();
while (((crtr - last_crtr) & AT91_ST_CRTV) >= RM9200_TIMER_LATCH) {
last_crtr += RM9200_TIMER_LATCH;
while (((crtr - last_crtr) & AT91_ST_CRTV) >= timer_latch) {
last_crtr += timer_latch;
clkevt.event_handler(&clkevt);
}
return IRQ_HANDLED;
@ -144,7 +143,7 @@ static int clkevt32k_set_periodic(struct clock_event_device *dev)
/* PIT for periodic irqs; fixed rate of 1/HZ */
irqmask = AT91_ST_PITS;
regmap_write(regmap_st, AT91_ST_PIMR, RM9200_TIMER_LATCH);
regmap_write(regmap_st, AT91_ST_PIMR, timer_latch);
regmap_write(regmap_st, AT91_ST_IER, irqmask);
return 0;
}
@ -197,7 +196,8 @@ static struct clock_event_device clkevt = {
*/
static void __init atmel_st_timer_init(struct device_node *node)
{
unsigned int val;
struct clk *sclk;
unsigned int sclk_rate, val;
int irq, ret;
regmap_st = syscon_node_to_regmap(node);
@ -221,6 +221,19 @@ static void __init atmel_st_timer_init(struct device_node *node)
if (ret)
panic(pr_fmt("Unable to setup IRQ\n"));
sclk = of_clk_get(node, 0);
if (IS_ERR(sclk))
panic(pr_fmt("Unable to get slow clock\n"));
clk_prepare_enable(sclk);
if (ret)
panic(pr_fmt("Could not enable slow clock\n"));
sclk_rate = clk_get_rate(sclk);
if (!sclk_rate)
panic(pr_fmt("Invalid slow clock rate\n"));
timer_latch = (sclk_rate + HZ / 2) / HZ;
/* The 32KiHz "Slow Clock" (tick every 30517.58 nanoseconds) is used
* directly for the clocksource and all clockevents, after adjusting
* its prescaler from the 1 Hz default.
@ -229,11 +242,11 @@ static void __init atmel_st_timer_init(struct device_node *node)
/* Setup timer clockevent, with minimum of two ticks (important!!) */
clkevt.cpumask = cpumask_of(0);
clockevents_config_and_register(&clkevt, AT91_SLOW_CLOCK,
clockevents_config_and_register(&clkevt, sclk_rate,
2, AT91_ST_ALMV);
/* register clocksource */
clocksource_register_hz(&clk32k, AT91_SLOW_CLOCK);
clocksource_register_hz(&clk32k, sclk_rate);
}
CLOCKSOURCE_OF_DECLARE(atmel_st_timer, "atmel,at91rm9200-st",
atmel_st_timer_init);

10
drivers/cpufreq/Kconfig.arm
View file

@ -199,6 +199,16 @@ config ARM_SA1100_CPUFREQ
config ARM_SA1110_CPUFREQ
bool
config ARM_SCPI_CPUFREQ
tristate "SCPI based CPUfreq driver"
depends on ARM_BIG_LITTLE_CPUFREQ && ARM_SCPI_PROTOCOL
help
This adds the CPUfreq driver support for ARM big.LITTLE platforms
using SCPI protocol for CPU power management.
This driver uses SCPI Message Protocol driver to interact with the
firmware providing the CPU DVFS functionality.
config ARM_SPEAR_CPUFREQ
bool "SPEAr CPUFreq support"
depends on PLAT_SPEAR

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