This is the 4.9.80 stable release
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SUNRPC: Allow connect to return EHOSTUNREACH kmemleak: add scheduling point to kmemleak_scan() drm/bridge: tc358767: do no fail on hi-res displays drm/bridge: tc358767: filter out too high modes drm/bridge: tc358767: fix DP0_MISC register set drm/bridge: tc358767: fix timing calculations drm/bridge: tc358767: fix AUXDATAn registers access drm/bridge: tc358767: fix 1-lane behavior drm/omap: Fix error handling path in 'omap_dmm_probe()' xfs: ubsan fixes xfs: Properly retry failed dquot items in case of error during buffer writeback scsi: aacraid: Prevent crash in case of free interrupt during scsi EH path scsi: ufs: ufshcd: fix potential NULL pointer dereference in ufshcd_config_vreg iwlwifi: mvm: fix the TX queue hang timeout for MONITOR vif type ARM: dts: NSP: Fix PPI interrupt types media: usbtv: add a new usbid usb: gadget: don't dereference g until after it has been null checked staging: rtl8188eu: Fix incorrect response to SIOCGIWESSID drm/vc4: Move IRQ enable to PM path staging: lustre: separate a connection destroy from free struct kib_conn tty: fix data race between tty_init_dev and flush of buf usb: option: Add support for FS040U modem USB: serial: pl2303: new device id for Chilitag USB: cdc-acm: Do not log urb submission errors on disconnect CDC-ACM: apply quirk for card reader USB: serial: io_edgeport: fix possible sleep-in-atomic usbip: prevent bind loops on devices attached to vhci_hcd usbip: list: don't list devices attached to vhci_hcd USB: serial: simple: add Motorola Tetra driver usb: f_fs: Prevent gadget unbind if it is already unbound usb: uas: unconditionally bring back host after reset usb/gadget: Fix "high bandwidth" check in usb_gadget_ep_match_desc() usbip: vhci_hcd: clear just the USB_PORT_STAT_POWER bit serial: imx: Only wakeup via RTSDEN bit if the system has RTS/CTS spi: imx: do not access registers while clocks disabled Linux 4.9.80 Signed-off-by: Greg Kroah-Hartman <gregkh@google.com>
This commit is contained in:
Greg Kroah-Hartman
commit
a9fd318870
84 changed files with 542 additions and 238 deletions
2
Makefile
2
Makefile
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@ -1,6 +1,6 @@
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VERSION = 4
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PATCHLEVEL = 9
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SUBLEVEL = 79
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SUBLEVEL = 80
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EXTRAVERSION =
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NAME = Roaring Lionus
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@ -85,7 +85,7 @@
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timer@20200 {
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compatible = "arm,cortex-a9-global-timer";
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reg = <0x20200 0x100>;
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interrupts = <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>;
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interrupts = <GIC_PPI 11 IRQ_TYPE_EDGE_RISING>;
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clocks = <&periph_clk>;
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};
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@ -93,7 +93,7 @@
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compatible = "arm,cortex-a9-twd-timer";
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reg = <0x20600 0x20>;
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interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) |
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IRQ_TYPE_LEVEL_HIGH)>;
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IRQ_TYPE_EDGE_RISING)>;
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clocks = <&periph_clk>;
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};
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@ -906,7 +906,7 @@ static int helper_rfc4106_encrypt(struct aead_request *req)
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if (sg_is_last(req->src) &&
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req->src->offset + req->src->length <= PAGE_SIZE &&
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sg_is_last(req->dst) &&
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+ sg_is_last(req->dst) && req->dst->length &&
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req->dst->offset + req->dst->length <= PAGE_SIZE) {
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one_entry_in_sg = 1;
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scatterwalk_start(&src_sg_walk, req->src);
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@ -1113,7 +1113,8 @@ int x86_emulate_instruction(struct kvm_vcpu *vcpu, unsigned long cr2,
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static inline int emulate_instruction(struct kvm_vcpu *vcpu,
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int emulation_type)
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{
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return x86_emulate_instruction(vcpu, 0, emulation_type, NULL, 0);
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return x86_emulate_instruction(vcpu, 0,
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emulation_type | EMULTYPE_NO_REEXECUTE, NULL, 0);
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}
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void kvm_enable_efer_bits(u64);
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@ -4990,6 +4990,8 @@ int x86_decode_insn(struct x86_emulate_ctxt *ctxt, void *insn, int insn_len)
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bool op_prefix = false;
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bool has_seg_override = false;
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struct opcode opcode;
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u16 dummy;
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struct desc_struct desc;
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ctxt->memop.type = OP_NONE;
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ctxt->memopp = NULL;
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@ -5008,6 +5010,11 @@ int x86_decode_insn(struct x86_emulate_ctxt *ctxt, void *insn, int insn_len)
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switch (mode) {
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case X86EMUL_MODE_REAL:
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case X86EMUL_MODE_VM86:
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def_op_bytes = def_ad_bytes = 2;
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ctxt->ops->get_segment(ctxt, &dummy, &desc, NULL, VCPU_SREG_CS);
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if (desc.d)
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def_op_bytes = def_ad_bytes = 4;
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break;
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case X86EMUL_MODE_PROT16:
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def_op_bytes = def_ad_bytes = 2;
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break;
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@ -257,8 +257,7 @@ void kvm_ioapic_scan_entry(struct kvm_vcpu *vcpu, ulong *ioapic_handled_vectors)
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index == RTC_GSI) {
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if (kvm_apic_match_dest(vcpu, NULL, 0,
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e->fields.dest_id, e->fields.dest_mode) ||
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(e->fields.trig_mode == IOAPIC_EDGE_TRIG &&
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kvm_apic_pending_eoi(vcpu, e->fields.vector)))
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kvm_apic_pending_eoi(vcpu, e->fields.vector))
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__set_bit(e->fields.vector,
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ioapic_handled_vectors);
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}
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@ -279,6 +278,7 @@ static void ioapic_write_indirect(struct kvm_ioapic *ioapic, u32 val)
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{
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unsigned index;
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bool mask_before, mask_after;
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int old_remote_irr, old_delivery_status;
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union kvm_ioapic_redirect_entry *e;
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switch (ioapic->ioregsel) {
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@ -301,14 +301,28 @@ static void ioapic_write_indirect(struct kvm_ioapic *ioapic, u32 val)
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return;
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e = &ioapic->redirtbl[index];
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mask_before = e->fields.mask;
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/* Preserve read-only fields */
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old_remote_irr = e->fields.remote_irr;
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old_delivery_status = e->fields.delivery_status;
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if (ioapic->ioregsel & 1) {
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e->bits &= 0xffffffff;
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e->bits |= (u64) val << 32;
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} else {
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e->bits &= ~0xffffffffULL;
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e->bits |= (u32) val;
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e->fields.remote_irr = 0;
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}
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e->fields.remote_irr = old_remote_irr;
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e->fields.delivery_status = old_delivery_status;
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/*
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* Some OSes (Linux, Xen) assume that Remote IRR bit will
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* be cleared by IOAPIC hardware when the entry is configured
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* as edge-triggered. This behavior is used to simulate an
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* explicit EOI on IOAPICs that don't have the EOI register.
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*/
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if (e->fields.trig_mode == IOAPIC_EDGE_TRIG)
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e->fields.remote_irr = 0;
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mask_after = e->fields.mask;
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if (mask_before != mask_after)
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kvm_fire_mask_notifiers(ioapic->kvm, KVM_IRQCHIP_IOAPIC, index, mask_after);
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@ -5194,7 +5194,7 @@ static void vmx_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event)
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vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
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}
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vmcs_writel(GUEST_RFLAGS, 0x02);
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kvm_set_rflags(vcpu, X86_EFLAGS_FIXED);
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kvm_rip_write(vcpu, 0xfff0);
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vmcs_writel(GUEST_GDTR_BASE, 0);
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@ -6257,7 +6257,7 @@ static int handle_invalid_guest_state(struct kvm_vcpu *vcpu)
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if (test_bit(KVM_REQ_EVENT, &vcpu->requests))
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return 1;
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err = emulate_instruction(vcpu, EMULTYPE_NO_REEXECUTE);
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err = emulate_instruction(vcpu, 0);
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if (err == EMULATE_USER_EXIT) {
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++vcpu->stat.mmio_exits;
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@ -1751,10 +1751,13 @@ static u64 __get_kvmclock_ns(struct kvm *kvm)
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/* both __this_cpu_read() and rdtsc() should be on the same cpu */
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get_cpu();
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kvm_get_time_scale(NSEC_PER_SEC, __this_cpu_read(cpu_tsc_khz) * 1000LL,
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&hv_clock.tsc_shift,
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&hv_clock.tsc_to_system_mul);
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ret = __pvclock_read_cycles(&hv_clock, rdtsc());
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if (__this_cpu_read(cpu_tsc_khz)) {
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kvm_get_time_scale(NSEC_PER_SEC, __this_cpu_read(cpu_tsc_khz) * 1000LL,
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&hv_clock.tsc_shift,
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&hv_clock.tsc_to_system_mul);
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ret = __pvclock_read_cycles(&hv_clock, rdtsc());
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} else
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ret = ktime_get_boot_ns() + ka->kvmclock_offset;
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put_cpu();
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@ -5308,7 +5311,7 @@ static int handle_emulation_failure(struct kvm_vcpu *vcpu)
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vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
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vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
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vcpu->run->internal.ndata = 0;
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r = EMULATE_FAIL;
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r = EMULATE_USER_EXIT;
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}
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kvm_queue_exception(vcpu, UD_VECTOR);
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@ -120,7 +120,7 @@ config CRYPTO_DH
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config CRYPTO_ECDH
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tristate "ECDH algorithm"
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select CRYTPO_KPP
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select CRYPTO_KPP
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help
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Generic implementation of the ECDH algorithm
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@ -149,7 +149,7 @@ EXPORT_SYMBOL_GPL(af_alg_release_parent);
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static int alg_bind(struct socket *sock, struct sockaddr *uaddr, int addr_len)
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{
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const u32 forbidden = CRYPTO_ALG_INTERNAL;
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const u32 allowed = CRYPTO_ALG_KERN_DRIVER_ONLY;
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struct sock *sk = sock->sk;
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struct alg_sock *ask = alg_sk(sk);
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struct sockaddr_alg *sa = (void *)uaddr;
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@ -157,6 +157,10 @@ static int alg_bind(struct socket *sock, struct sockaddr *uaddr, int addr_len)
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void *private;
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int err;
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/* If caller uses non-allowed flag, return error. */
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if ((sa->salg_feat & ~allowed) || (sa->salg_mask & ~allowed))
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return -EINVAL;
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if (sock->state == SS_CONNECTED)
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return -EINVAL;
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@ -175,9 +179,7 @@ static int alg_bind(struct socket *sock, struct sockaddr *uaddr, int addr_len)
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if (IS_ERR(type))
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return PTR_ERR(type);
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private = type->bind(sa->salg_name,
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sa->salg_feat & ~forbidden,
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sa->salg_mask & ~forbidden);
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private = type->bind(sa->salg_name, sa->salg_feat, sa->salg_mask);
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if (IS_ERR(private)) {
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module_put(type->owner);
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return PTR_ERR(private);
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@ -18,6 +18,7 @@
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#include <linux/types.h>
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#include <crypto/sha3.h>
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#include <asm/byteorder.h>
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#include <asm/unaligned.h>
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#define KECCAK_ROUNDS 24
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@ -149,7 +150,7 @@ static int sha3_update(struct shash_desc *desc, const u8 *data,
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unsigned int i;
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for (i = 0; i < sctx->rsizw; i++)
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sctx->st[i] ^= ((u64 *) src)[i];
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sctx->st[i] ^= get_unaligned_le64(src + 8 * i);
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keccakf(sctx->st);
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done += sctx->rsiz;
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@ -174,7 +175,7 @@ static int sha3_final(struct shash_desc *desc, u8 *out)
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sctx->buf[sctx->rsiz - 1] |= 0x80;
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for (i = 0; i < sctx->rsizw; i++)
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sctx->st[i] ^= ((u64 *) sctx->buf)[i];
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sctx->st[i] ^= get_unaligned_le64(sctx->buf + 8 * i);
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keccakf(sctx->st);
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@ -146,6 +146,10 @@ static int create_pnp_modalias(struct acpi_device *acpi_dev, char *modalias,
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int count;
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struct acpi_hardware_id *id;
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/* Avoid unnecessarily loading modules for non present devices. */
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if (!acpi_device_is_present(acpi_dev))
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return 0;
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/*
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* Since we skip ACPI_DT_NAMESPACE_HID from the modalias below, 0 should
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* be returned if ACPI_DT_NAMESPACE_HID is the only ACPI/PNP ID in the
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@ -121,6 +121,7 @@ config CFAG12864B_RATE
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config IMG_ASCII_LCD
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tristate "Imagination Technologies ASCII LCD Display"
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depends on HAS_IOMEM
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default y if MIPS_MALTA || MIPS_SEAD3
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select SYSCON
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help
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|
|
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@ -1558,9 +1558,8 @@ out:
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return err;
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}
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static void lo_release(struct gendisk *disk, fmode_t mode)
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static void __lo_release(struct loop_device *lo)
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{
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struct loop_device *lo = disk->private_data;
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int err;
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if (atomic_dec_return(&lo->lo_refcnt))
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@ -1586,6 +1585,13 @@ static void lo_release(struct gendisk *disk, fmode_t mode)
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mutex_unlock(&lo->lo_ctl_mutex);
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}
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static void lo_release(struct gendisk *disk, fmode_t mode)
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{
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mutex_lock(&loop_index_mutex);
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__lo_release(disk->private_data);
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mutex_unlock(&loop_index_mutex);
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}
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static const struct block_device_operations lo_fops = {
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.owner = THIS_MODULE,
|
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.open = lo_open,
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|
|
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|||
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|
@ -324,6 +324,7 @@ endif
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if MIPS
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config LOONGSON2_CPUFREQ
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tristate "Loongson2 CPUFreq Driver"
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depends on LEMOTE_MACH2F
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help
|
||||
This option adds a CPUFreq driver for loongson processors which
|
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support software configurable cpu frequency.
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|
|
@ -336,6 +337,7 @@ config LOONGSON2_CPUFREQ
|
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config LOONGSON1_CPUFREQ
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tristate "Loongson1 CPUFreq Driver"
|
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depends on LOONGSON1_LS1B
|
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help
|
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This option adds a CPUFreq driver for loongson1 processors which
|
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support software configurable cpu frequency.
|
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|
|
|
|||
|
|
@ -323,3 +323,6 @@ static struct platform_driver ath79_gpio_driver = {
|
|||
};
|
||||
|
||||
module_platform_driver(ath79_gpio_driver);
|
||||
|
||||
MODULE_DESCRIPTION("Atheros AR71XX/AR724X/AR913X GPIO API support");
|
||||
MODULE_LICENSE("GPL v2");
|
||||
|
|
|
|||
|
|
@ -58,3 +58,7 @@ static int __init iop3xx_gpio_init(void)
|
|||
return platform_driver_register(&iop3xx_gpio_driver);
|
||||
}
|
||||
arch_initcall(iop3xx_gpio_init);
|
||||
|
||||
MODULE_DESCRIPTION("GPIO handling for Intel IOP3xx processors");
|
||||
MODULE_AUTHOR("Lennert Buytenhek <buytenh@wantstofly.org>");
|
||||
MODULE_LICENSE("GPL");
|
||||
|
|
|
|||
|
|
@ -190,6 +190,16 @@ static void stmpe_gpio_irq_sync_unlock(struct irq_data *d)
|
|||
};
|
||||
int i, j;
|
||||
|
||||
/*
|
||||
* STMPE1600: to be able to get IRQ from pins,
|
||||
* a read must be done on GPMR register, or a write in
|
||||
* GPSR or GPCR registers
|
||||
*/
|
||||
if (stmpe->partnum == STMPE1600) {
|
||||
stmpe_reg_read(stmpe, stmpe->regs[STMPE_IDX_GPMR_LSB]);
|
||||
stmpe_reg_read(stmpe, stmpe->regs[STMPE_IDX_GPMR_CSB]);
|
||||
}
|
||||
|
||||
for (i = 0; i < CACHE_NR_REGS; i++) {
|
||||
/* STMPE801 and STMPE1600 don't have RE and FE registers */
|
||||
if ((stmpe->partnum == STMPE801 ||
|
||||
|
|
@ -227,21 +237,11 @@ static void stmpe_gpio_irq_unmask(struct irq_data *d)
|
|||
{
|
||||
struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
|
||||
struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(gc);
|
||||
struct stmpe *stmpe = stmpe_gpio->stmpe;
|
||||
int offset = d->hwirq;
|
||||
int regoffset = offset / 8;
|
||||
int mask = BIT(offset % 8);
|
||||
|
||||
stmpe_gpio->regs[REG_IE][regoffset] |= mask;
|
||||
|
||||
/*
|
||||
* STMPE1600 workaround: to be able to get IRQ from pins,
|
||||
* a read must be done on GPMR register, or a write in
|
||||
* GPSR or GPCR registers
|
||||
*/
|
||||
if (stmpe->partnum == STMPE1600)
|
||||
stmpe_reg_read(stmpe,
|
||||
stmpe->regs[STMPE_IDX_GPMR_LSB + regoffset]);
|
||||
}
|
||||
|
||||
static void stmpe_dbg_show_one(struct seq_file *s,
|
||||
|
|
|
|||
|
|
@ -705,6 +705,9 @@ static irqreturn_t lineevent_irq_thread(int irq, void *p)
|
|||
struct gpioevent_data ge;
|
||||
int ret, level;
|
||||
|
||||
/* Do not leak kernel stack to userspace */
|
||||
memset(&ge, 0, sizeof(ge));
|
||||
|
||||
ge.timestamp = ktime_get_real_ns();
|
||||
level = gpiod_get_value_cansleep(le->desc);
|
||||
|
||||
|
|
|
|||
|
|
@ -367,29 +367,50 @@ static int kgd_hqd_sdma_load(struct kgd_dev *kgd, void *mqd)
|
|||
{
|
||||
struct amdgpu_device *adev = get_amdgpu_device(kgd);
|
||||
struct cik_sdma_rlc_registers *m;
|
||||
unsigned long end_jiffies;
|
||||
uint32_t sdma_base_addr;
|
||||
uint32_t data;
|
||||
|
||||
m = get_sdma_mqd(mqd);
|
||||
sdma_base_addr = get_sdma_base_addr(m);
|
||||
|
||||
WREG32(sdma_base_addr + mmSDMA0_RLC0_VIRTUAL_ADDR,
|
||||
m->sdma_rlc_virtual_addr);
|
||||
WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_CNTL,
|
||||
m->sdma_rlc_rb_cntl & (~SDMA0_RLC0_RB_CNTL__RB_ENABLE_MASK));
|
||||
|
||||
WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_BASE,
|
||||
m->sdma_rlc_rb_base);
|
||||
|
||||
WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_BASE_HI,
|
||||
m->sdma_rlc_rb_base_hi);
|
||||
|
||||
WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_RPTR_ADDR_LO,
|
||||
m->sdma_rlc_rb_rptr_addr_lo);
|
||||
|
||||
WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_RPTR_ADDR_HI,
|
||||
m->sdma_rlc_rb_rptr_addr_hi);
|
||||
end_jiffies = msecs_to_jiffies(2000) + jiffies;
|
||||
while (true) {
|
||||
data = RREG32(sdma_base_addr + mmSDMA0_RLC0_CONTEXT_STATUS);
|
||||
if (data & SDMA0_RLC0_CONTEXT_STATUS__IDLE_MASK)
|
||||
break;
|
||||
if (time_after(jiffies, end_jiffies))
|
||||
return -ETIME;
|
||||
usleep_range(500, 1000);
|
||||
}
|
||||
if (m->sdma_engine_id) {
|
||||
data = RREG32(mmSDMA1_GFX_CONTEXT_CNTL);
|
||||
data = REG_SET_FIELD(data, SDMA1_GFX_CONTEXT_CNTL,
|
||||
RESUME_CTX, 0);
|
||||
WREG32(mmSDMA1_GFX_CONTEXT_CNTL, data);
|
||||
} else {
|
||||
data = RREG32(mmSDMA0_GFX_CONTEXT_CNTL);
|
||||
data = REG_SET_FIELD(data, SDMA0_GFX_CONTEXT_CNTL,
|
||||
RESUME_CTX, 0);
|
||||
WREG32(mmSDMA0_GFX_CONTEXT_CNTL, data);
|
||||
}
|
||||
|
||||
WREG32(sdma_base_addr + mmSDMA0_RLC0_DOORBELL,
|
||||
m->sdma_rlc_doorbell);
|
||||
|
||||
m->sdma_rlc_doorbell);
|
||||
WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_RPTR, 0);
|
||||
WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_WPTR, 0);
|
||||
WREG32(sdma_base_addr + mmSDMA0_RLC0_VIRTUAL_ADDR,
|
||||
m->sdma_rlc_virtual_addr);
|
||||
WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_BASE, m->sdma_rlc_rb_base);
|
||||
WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_BASE_HI,
|
||||
m->sdma_rlc_rb_base_hi);
|
||||
WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_RPTR_ADDR_LO,
|
||||
m->sdma_rlc_rb_rptr_addr_lo);
|
||||
WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_RPTR_ADDR_HI,
|
||||
m->sdma_rlc_rb_rptr_addr_hi);
|
||||
WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_CNTL,
|
||||
m->sdma_rlc_rb_cntl);
|
||||
|
||||
|
|
@ -493,9 +514,9 @@ static int kgd_hqd_sdma_destroy(struct kgd_dev *kgd, void *mqd,
|
|||
}
|
||||
|
||||
WREG32(sdma_base_addr + mmSDMA0_RLC0_DOORBELL, 0);
|
||||
WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_RPTR, 0);
|
||||
WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_WPTR, 0);
|
||||
WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_BASE, 0);
|
||||
WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_CNTL,
|
||||
RREG32(sdma_base_addr + mmSDMA0_RLC0_RB_CNTL) |
|
||||
SDMA0_RLC0_RB_CNTL__RB_ENABLE_MASK);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
|
|||
Some files were not shown because too many files have changed in this diff Show more
Loading…
Reference in a new issue