joy/android_kernel_sony_sdm845
Watch
1
Fork
You've already forked android_kernel_sony_sdm845
 0
Code Issues Pull requests Projects Releases Wiki Activity

Merge tag 'LA.UM.8.3.c25-07000-sdm845.0' of https://git.codelinaro.org/clo/la/kernel/msm-4.9 into android13-4.9-sdm845

Browse source 
"LA.UM.8.3.c25-07000-sdm845.0"

* tag 'LA.UM.8.3.c25-07000-sdm845.0' of https://git.codelinaro.org/clo/la/kernel/msm-4.9:
  msm: ADSPRPC: Restrict untrusted applications from attaching to GuestOS
  msm: kgsl: Remove 'fd' dependency to get dma_buf handle
  msm: kgsl: Fix gpuaddr_in_range() to check upper bound
  msm: kgsl: Zap performance counters across context switches
  msm: kgsl: Add a sysfs node to control performance counter reads
  msm: kgsl: Perform cache flush on the pages obtained using get_user_pages()
  msm: kgsl: Fix memory leak for anonymous buffers
  msm: kgsl: Update register protection config
  disp: msm: sde: protect file private structure with mutex lock
  msm: kgsl: Fix out of bound write in adreno_profile_submit_time
  soc: qcom: glink: wait for tx blocked signal response
  msm: kgsl: Deregister gpu address on memdesc_sg_virt failure
  disp: msm: sde: add null check for drm file in msm_release
  msm: adsprpc: Handle UAF in process shell memory
  msm: adsprpc: Fix race condition in internal_control
  msm: adsprpc: overflow vulnerability by race condition in adsprpc driver
  crypto: Fix possible stack out-of-bound error
  net:sockev: hold file reference till the sock event is sent
  msm: kgsl: Access map_count only if entry is successfully allocated
  msm: kgsl: Correct the refcount on current process PID
  msm: kgsl: Stop using memdesc->usermem
  msm: kgsl: Protect the memdesc->gpuaddr in SVM use cases
  msm:ADSPRPC :Fix to avoid Use after free in fastrpc_internal_munmap
  msm: kgsl: Allocate user_ctxt_record based on preemption feature flag

 Conflicts:
	drivers/char/adsprpc.c
	drivers/gpu/msm/kgsl_iommu.c
	drivers/gpu/msm/kgsl_mmu.c

Change-Id: I918030d8b29f3a67939a7711b4fa9f65da4c02b8
This commit is contained in:
Michael Bestas 2022-10-13 02:32:26 +03:00
commit a2ec1d2ec1
No known key found for this signature in database
GPG key ID: CC95044519BE6669
18 changed files with 192 additions and 37 deletions
Download patch file Download diff file Expand all files Collapse all files

13
drivers/char/adsprpc.c
View file

@ -2237,6 +2237,12 @@ static int fastrpc_init_process(struct fastrpc_file *fl,
remote_arg_t ra[1];
int tgid = fl->tgid;
if (fl->dev_minor == MINOR_NUM_DEV) {
err = -ECONNREFUSED;
pr_err("adsprpc: %s: untrusted apk trying to attach to privileged DSP PD\n",
__func__);
return err;
}
ra[0].buf.pv = (void *)&tgid;
ra[0].buf.len = sizeof(tgid);
ioctl.inv.handle = FASTRPC_STATIC_HANDLE_PROCESS_GROUP;
@ -2359,6 +2365,13 @@ static int fastrpc_init_process(struct fastrpc_file *fl,
unsigned int pageslen;
} inbuf;
if (fl->dev_minor == MINOR_NUM_DEV) {
err = -ECONNREFUSED;
pr_err("adsprpc: %s: untrusted apk trying to attach to audio PD\n",
__func__);
return err;
}
if (!init->filelen)
goto bail;

3
drivers/gpu/msm/a6xx_reg.h
View file

@ -1,4 +1,5 @@
/* Copyright (c) 2017-2018, The Linux Foundation. All rights reserved.
* Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
@ -395,6 +396,8 @@
#define A6XX_RBBM_PERFCTR_RBBM_SEL_2 0x509
#define A6XX_RBBM_PERFCTR_RBBM_SEL_3 0x50A
#define A6XX_RBBM_PERFCTR_GPU_BUSY_MASKED 0x50B
#define A6XX_RBBM_PERFCTR_SRAM_INIT_CMD 0x50e
#define A6XX_RBBM_PERFCTR_SRAM_INIT_STATUS 0x50f
#define A6XX_RBBM_ISDB_CNT 0x533

3
drivers/gpu/msm/adreno.c
View file

@ -1,4 +1,5 @@
/* Copyright (c) 2002,2007-2018,2020, The Linux Foundation. All rights reserved.
* Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
@ -1426,6 +1427,8 @@ static int adreno_probe(struct platform_device *pdev)
adreno_debugfs_init(adreno_dev);
adreno_profile_init(adreno_dev);
adreno_dev->perfcounter = false;
adreno_sysfs_init(adreno_dev);
kgsl_pwrscale_init(&pdev->dev, CONFIG_QCOM_ADRENO_DEFAULT_GOVERNOR);

14
drivers/gpu/msm/adreno.h
View file

@ -1,4 +1,5 @@
/* Copyright (c) 2008-2018,2020, The Linux Foundation. All rights reserved.
* Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
@ -34,6 +35,9 @@
#define DEVICE_3D_NAME "kgsl-3d"
#define DEVICE_3D0_NAME "kgsl-3d0"
/* Index to preemption scratch buffer to store KMD postamble */
#define KMD_POSTAMBLE_IDX 100
/* ADRENO_DEVICE - Given a kgsl_device return the adreno device struct */
#define ADRENO_DEVICE(device) \
container_of(device, struct adreno_device, dev)
@ -251,6 +255,9 @@ struct adreno_gpudev;
/* Time to allow preemption to complete (in ms) */
#define ADRENO_PREEMPT_TIMEOUT 10000
#define PREEMPT_SCRATCH_ADDR(dev, id) \
((dev)->preempt.scratch.gpuaddr + (id * sizeof(u64)))
#define ADRENO_INT_BIT(a, _bit) (((a)->gpucore->gpudev->int_bits) ? \
(adreno_get_int(a, _bit) < 0 ? 0 : \
BIT(adreno_get_int(a, _bit))) : 0)
@ -287,6 +294,7 @@ enum adreno_preempt_states {
* skipsaverestore: To skip saverestore during L1 preemption (for 6XX)
* usesgmem: enable GMEM save/restore across preemption (for 6XX)
* count: Track the number of preemptions triggered
* @postamble_len: Number of dwords in KMD postamble pm4 packet
*/
struct adreno_preemption {
atomic_t state;
@ -298,6 +306,7 @@ struct adreno_preemption {
bool skipsaverestore;
bool usesgmem;
unsigned int count;
u32 postamble_len;
};
@ -578,6 +587,11 @@ struct adreno_device {
bool gpuhtw_llc_slice_enable;
unsigned int zap_loaded;
unsigned int soc_hw_rev;
/*
* @perfcounter: Flag to clear perfcounters across contexts and
* controls perfcounter ioctl read
*/
bool perfcounter;
};
/**

49
drivers/gpu/msm/adreno_a6xx_preempt.c
View file

@ -1,4 +1,5 @@
/* Copyright (c) 2017-2018,2020, The Linux Foundation. All rights reserved.
* Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
@ -544,13 +545,27 @@ unsigned int a6xx_preemption_pre_ibsubmit(
if (context) {
struct adreno_context *drawctxt = ADRENO_CONTEXT(context);
struct adreno_ringbuffer *rb = drawctxt->rb;
uint64_t dest = adreno_dev->preempt.scratch.gpuaddr +
sizeof(u64) * rb->id;
uint64_t dest = PREEMPT_SCRATCH_ADDR(adreno_dev, rb->id);
*cmds++ = cp_mem_packet(adreno_dev, CP_MEM_WRITE, 2, 2);
cmds += cp_gpuaddr(adreno_dev, cmds, dest);
*cmds++ = lower_32_bits(gpuaddr);
*cmds++ = upper_32_bits(gpuaddr);
/*
* Add a KMD post amble to clear the perf counters during
* preemption
*/
if (!adreno_dev->perfcounter) {
u64 kmd_postamble_addr =
PREEMPT_SCRATCH_ADDR(adreno_dev, KMD_POSTAMBLE_IDX);
*cmds++ = cp_type7_packet(CP_SET_AMBLE, 3);
*cmds++ = lower_32_bits(kmd_postamble_addr);
*cmds++ = upper_32_bits(kmd_postamble_addr);
*cmds++ = ((CP_KMD_AMBLE_TYPE << 20) | GENMASK(22, 20))
| (adreno_dev->preempt.postamble_len | GENMASK(19, 0));
}
}
return (unsigned int) (cmds - cmds_orig);
@ -563,8 +578,7 @@ unsigned int a6xx_preemption_post_ibsubmit(struct adreno_device *adreno_dev,
struct adreno_ringbuffer *rb = adreno_dev->cur_rb;
if (rb) {
uint64_t dest = adreno_dev->preempt.scratch.gpuaddr +
sizeof(u64) * rb->id;
uint64_t dest = PREEMPT_SCRATCH_ADDR(adreno_dev, rb->id);
*cmds++ = cp_mem_packet(adreno_dev, CP_MEM_WRITE, 2, 2);
cmds += cp_gpuaddr(adreno_dev, cmds, dest);
@ -778,6 +792,33 @@ int a6xx_preemption_init(struct adreno_device *adreno_dev)
addr += A6XX_CP_CTXRECORD_PREEMPTION_COUNTER_SIZE;
}
/*
* First 8 dwords of the preemption scratch buffer is used to store the
* address for CP to save/restore VPC data. Reserve 11 dwords in the
* preemption scratch buffer from index KMD_POSTAMBLE_IDX for KMD
* postamble pm4 packets
*/
if (!adreno_dev->perfcounter) {
u32 *postamble = preempt->scratch.hostptr +
(KMD_POSTAMBLE_IDX * sizeof(u64));
u32 count = 0;
postamble[count++] = cp_type7_packet(CP_REG_RMW, 3);
postamble[count++] = A6XX_RBBM_PERFCTR_SRAM_INIT_CMD;
postamble[count++] = 0x0;
postamble[count++] = 0x1;
postamble[count++] = cp_type7_packet(CP_WAIT_REG_MEM, 6);
postamble[count++] = 0x3;
postamble[count++] = A6XX_RBBM_PERFCTR_SRAM_INIT_STATUS;
postamble[count++] = 0x0;
postamble[count++] = 0x1;
postamble[count++] = 0x1;
postamble[count++] = 0x0;
preempt->postamble_len = count;
}
ret = a6xx_preemption_iommu_init(adreno_dev);
err:

9
drivers/gpu/msm/adreno_compat.c
View file

@ -1,4 +1,5 @@
/* Copyright (c) 2013-2018, The Linux Foundation. All rights reserved.
* Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
@ -260,6 +261,14 @@ static long adreno_ioctl_perfcounter_read_compat(
struct kgsl_perfcounter_read_compat *read32 = data;
struct kgsl_perfcounter_read read;
/*
* When performance counter zapping is enabled, the counters are cleared
* across context switches. Reading the counters when they are zapped is
* not permitted.
*/
if (!adreno_dev->perfcounter)
return -EPERM;
read.reads = (struct kgsl_perfcounter_read_group __user *)
(uintptr_t)read32->reads;
read.count = read32->count;

4
drivers/gpu/msm/adreno_dispatch.c
View file

@ -1,4 +1,5 @@
/* Copyright (c) 2013-2020, The Linux Foundation. All rights reserved.
* Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
@ -1155,7 +1156,8 @@ static inline bool _verify_ib(struct kgsl_device_private *dev_priv,
}
/* Make sure that the address is mapped */
if (!kgsl_mmu_gpuaddr_in_range(private->pagetable, ib->gpuaddr)) {
if (!kgsl_mmu_gpuaddr_in_range(private->pagetable, ib->gpuaddr,
ib->size)) {
pr_context(device, context, "ctxt %d invalid ib gpuaddr %llX\n",
context->id, ib->gpuaddr);
return false;

9
drivers/gpu/msm/adreno_ioctl.c
View file

@ -1,4 +1,5 @@
/* Copyright (c) 2002,2007-2018,2020, The Linux Foundation. All rights reserved.
* Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
@ -141,6 +142,14 @@ static long adreno_ioctl_perfcounter_read(struct kgsl_device_private *dev_priv,
struct adreno_device *adreno_dev = ADRENO_DEVICE(dev_priv->device);
struct kgsl_perfcounter_read *read = data;
/*
* When performance counter zapping is enabled, the counters are cleared
* across context switches. Reading the counters when they are zapped is
* not permitted.
*/
if (!adreno_dev->perfcounter)
return -EPERM;
return (long) adreno_perfcounter_read_group(adreno_dev, read->reads,
read->count);
}

19
drivers/gpu/msm/adreno_iommu.c
View file

@ -1,4 +1,5 @@
/* Copyright (c) 2002,2007-2017, The Linux Foundation. All rights reserved.
* Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
@ -13,6 +14,7 @@
#include "adreno.h"
#include "kgsl_sharedmem.h"
#include "a3xx_reg.h"
#include "a6xx_reg.h"
#include "adreno_pm4types.h"
#define A5XX_PFP_PER_PROCESS_UCODE_VER 0x5FF064
@ -586,6 +588,12 @@ static unsigned int _adreno_iommu_set_pt_v2_a6xx(struct kgsl_device *device,
cmds += _adreno_iommu_add_idle_cmds(adreno_dev, cmds);
cmds += cp_wait_for_me(adreno_dev, cmds);
/* Clear performance counters during contect switches */
if (!adreno_dev->perfcounter) {
*cmds++ = cp_type4_packet(A6XX_RBBM_PERFCTR_SRAM_INIT_CMD, 1);
*cmds++ = 0x1;
}
/* CP switches the pagetable and flushes the Caches */
*cmds++ = cp_packet(adreno_dev, CP_SMMU_TABLE_UPDATE, 4);
*cmds++ = lower_32_bits(ttbr0);
@ -605,6 +613,17 @@ static unsigned int _adreno_iommu_set_pt_v2_a6xx(struct kgsl_device *device,
cmds += _adreno_iommu_add_idle_cmds(adreno_dev, cmds);
/* Wait for performance counter clear to finish */
if (!adreno_dev->perfcounter) {
*cmds++ = cp_type7_packet(CP_WAIT_REG_MEM, 6);
*cmds++ = 0x3;
*cmds++ = A6XX_RBBM_PERFCTR_SRAM_INIT_STATUS;
*cmds++ = 0x0;
*cmds++ = 0x1;
*cmds++ = 0x1;
*cmds++ = 0x0;
}
return cmds - cmds_orig;
}

7
drivers/gpu/msm/adreno_perfcounter.c
View file

@ -1,4 +1,5 @@
/* Copyright (c) 2002,2007-2017, The Linux Foundation. All rights reserved.
* Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
@ -143,7 +144,8 @@ void adreno_perfcounter_restore(struct adreno_device *adreno_dev)
struct adreno_perfcount_group *group;
unsigned int counter, groupid;
if (counters == NULL)
/* Do not save/restore if not requested */
if (counters == NULL || !adreno_dev->perfcounter)
return;
for (groupid = 0; groupid < counters->group_count; groupid++) {
@ -177,7 +179,8 @@ inline void adreno_perfcounter_save(struct adreno_device *adreno_dev)
unsigned int counter, groupid;
int ret = 0;
if (counters == NULL)
/* Do not save/restore if not requested */
if (counters == NULL || !adreno_dev->perfcounter)
return;
if (gpudev->oob_set)

7
drivers/gpu/msm/adreno_pm4types.h
View file

@ -1,4 +1,5 @@
/* Copyright (c) 2002,2007-2017,2020, The Linux Foundation. All rights reserved.
* Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
@ -55,6 +56,9 @@
/* switches SMMU pagetable, used on a5xx only */
#define CP_SMMU_TABLE_UPDATE 0x53
/* Designate command streams to be executed before/after state restore */
#define CP_SET_AMBLE 0x55
/* Set internal CP registers, used to indicate context save data addresses */
#define CP_SET_PSEUDO_REGISTER 0x56
@ -162,6 +166,9 @@
#define CP_LOADSTATE_STATETYPE_SHIFT 0x00000000
#define CP_LOADSTATE_EXTSRCADDR_SHIFT 0x00000002
/* Used to define amble type in SET_AMBLE packet to execute during preemption */
#define CP_KMD_AMBLE_TYPE 3
static inline uint pm4_calc_odd_parity_bit(uint val)
{
return (0x9669 >> (0xf & ((val) ^

3
drivers/gpu/msm/adreno_ringbuffer.c
View file

@ -1,4 +1,5 @@
/* Copyright (c) 2002,2007-2020, The Linux Foundation. All rights reserved.
* Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
@ -555,7 +556,7 @@ adreno_ringbuffer_addcmds(struct adreno_ringbuffer *rb,
if (gpudev->preemption_pre_ibsubmit &&
adreno_is_preemption_enabled(adreno_dev))
total_sizedwords += 27;
total_sizedwords += 31;
if (gpudev->preemption_post_ibsubmit &&
adreno_is_preemption_enabled(adreno_dev))

33
drivers/gpu/msm/adreno_sysfs.c
View file

@ -1,4 +1,5 @@
/* Copyright (c) 2014-2018, The Linux Foundation. All rights reserved.
* Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
@ -353,6 +354,31 @@ static unsigned int _preempt_count_show(struct adreno_device *adreno_dev)
return preempt->count;
}
static unsigned int _perfcounter_show(struct adreno_device *adreno_dev)
{
return adreno_dev->perfcounter;
}
static int _perfcounter_store(struct adreno_device *adreno_dev,
unsigned int val)
{
struct kgsl_device *device = KGSL_DEVICE(adreno_dev);
if (adreno_dev->perfcounter == val)
return 0;
mutex_lock(&device->mutex);
/* Power down the GPU before changing the state */
kgsl_pwrctrl_change_state(device, KGSL_STATE_SUSPEND);
adreno_dev->perfcounter = val;
kgsl_pwrctrl_change_state(device, KGSL_STATE_SLUMBER);
mutex_unlock(&device->mutex);
return 0;
}
static ssize_t _sysfs_store_u32(struct device *dev,
struct device_attribute *attr,
const char *buf, size_t count)
@ -457,6 +483,7 @@ static ADRENO_SYSFS_BOOL(hwcg);
static ADRENO_SYSFS_BOOL(throttling);
static ADRENO_SYSFS_BOOL(ifpc);
static ADRENO_SYSFS_RO_U32(ifpc_count);
static ADRENO_SYSFS_BOOL(perfcounter);
@ -480,6 +507,7 @@ static const struct device_attribute *_attr_list[] = {
&adreno_attr_ifpc.attr,
&adreno_attr_ifpc_count.attr,
&adreno_attr_preempt_count.attr,
&adreno_attr_perfcounter.attr,
NULL,
};
@ -637,8 +665,11 @@ int adreno_sysfs_init(struct adreno_device *adreno_dev)
ret = kgsl_create_device_sysfs_files(device->dev, _attr_list);
/* Add the PPD directory and files */
if (ret == 0)
if (ret == 0) {
/* Notify userspace */
kobject_uevent(&device->dev->kobj, KOBJ_ADD);
ppd_sysfs_init(adreno_dev);
}
return 0;
}

24
drivers/gpu/msm/kgsl.c
View file

@ -1257,7 +1257,7 @@ kgsl_sharedmem_find(struct kgsl_process_private *private, uint64_t gpuaddr)
if (!private)
return NULL;
if (!kgsl_mmu_gpuaddr_in_range(private->pagetable, gpuaddr))
if (!kgsl_mmu_gpuaddr_in_range(private->pagetable, gpuaddr, 0))
return NULL;
spin_lock(&private->mem_lock);
@ -2243,15 +2243,6 @@ static int kgsl_setup_anon_useraddr(struct kgsl_pagetable *pagetable,
}
#ifdef CONFIG_DMA_SHARED_BUFFER
static int match_file(const void *p, struct file *file, unsigned int fd)
{
/*
* We must return fd + 1 because iterate_fd stops searching on
* non-zero return, but 0 is a valid fd.
*/
return (p == file) ? (fd + 1) : 0;
}
static void _setup_cache_mode(struct kgsl_mem_entry *entry,
struct vm_area_struct *vma)
{
@ -2289,8 +2280,6 @@ static int kgsl_setup_dmabuf_useraddr(struct kgsl_device *device,
vma = find_vma(current->mm, hostptr);
if (vma && vma->vm_file) {
int fd;
ret = check_vma_flags(vma, entry->memdesc.flags);
if (ret) {
up_read(&current->mm->mmap_sem);
@ -2306,10 +2295,13 @@ static int kgsl_setup_dmabuf_useraddr(struct kgsl_device *device,
return -EFAULT;
}
/* Look for the fd that matches this the vma file */
fd = iterate_fd(current->files, 0, match_file, vma->vm_file);
if (fd != 0)
dmabuf = dma_buf_get(fd - 1);
/*
* Take a refcount because dma_buf_put() decrements the
* refcount
*/
get_file(vma->vm_file);
dmabuf = vma->vm_file->private_data;
}
if (IS_ERR_OR_NULL(dmabuf)) {

10
drivers/gpu/msm/kgsl_iommu.c
View file

@ -1,4 +1,5 @@
/* Copyright (c) 2011-2021, The Linux Foundation. All rights reserved.
* Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
@ -2569,20 +2570,21 @@ static int kgsl_iommu_svm_range(struct kgsl_pagetable *pagetable,
}
static bool kgsl_iommu_addr_in_range(struct kgsl_pagetable *pagetable,
uint64_t gpuaddr)
uint64_t gpuaddr, uint64_t size)
{
struct kgsl_iommu_pt *pt = pagetable->priv;
if (gpuaddr == 0)
return false;
if (gpuaddr >= pt->va_start && gpuaddr < pt->va_end)
if (gpuaddr >= pt->va_start && (gpuaddr + size) < pt->va_end)
return true;
if (gpuaddr >= pt->compat_va_start && gpuaddr < pt->compat_va_end)
if (gpuaddr >= pt->compat_va_start &&
(gpuaddr + size) < pt->compat_va_end)
return true;
if (gpuaddr >= pt->svm_start && gpuaddr < pt->svm_end)
if (gpuaddr >= pt->svm_start && (gpuaddr + size) < pt->svm_end)
return true;
return false;

8
drivers/gpu/msm/kgsl_mmu.c
View file

@ -1,4 +1,5 @@
/* Copyright (c) 2002,2007-2017,2021, The Linux Foundation. All rights reserved.
* Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
@ -613,10 +614,11 @@ enum kgsl_mmutype kgsl_mmu_get_mmutype(struct kgsl_device *device)
EXPORT_SYMBOL(kgsl_mmu_get_mmutype);
bool kgsl_mmu_gpuaddr_in_range(struct kgsl_pagetable *pagetable,
uint64_t gpuaddr)
uint64_t gpuaddr, uint64_t size)
{
if (PT_OP_VALID(pagetable, addr_in_range))
return pagetable->pt_ops->addr_in_range(pagetable, gpuaddr);
return pagetable->pt_ops->addr_in_range(pagetable,
gpuaddr, size);
return false;
}
@ -652,7 +654,7 @@ EXPORT_SYMBOL(kgsl_mmu_get_qtimer_global_entry);
*/
static bool nommu_gpuaddr_in_range(struct kgsl_pagetable *pagetable,
uint64_t gpuaddr)
uint64_t gpuaddr, uint64_t size)
{
return (gpuaddr != 0) ? true : false;
}

7
drivers/gpu/msm/kgsl_mmu.h
View file

@ -1,4 +1,5 @@
/* Copyright (c) 2002,2007-2017, The Linux Foundation. All rights reserved.
* Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
@ -102,7 +103,8 @@ struct kgsl_mmu_pt_ops {
int (*set_svm_region)(struct kgsl_pagetable *, uint64_t, uint64_t);
int (*svm_range)(struct kgsl_pagetable *, uint64_t *, uint64_t *,
uint64_t);
bool (*addr_in_range)(struct kgsl_pagetable *pagetable, uint64_t);
bool (*addr_in_range)(struct kgsl_pagetable *pagetable,
uint64_t, uint64_t);
int (*mmu_map_offset)(struct kgsl_pagetable *pt,
uint64_t virtaddr, uint64_t virtoffset,
struct kgsl_memdesc *memdesc, uint64_t physoffset,
@ -194,7 +196,8 @@ unsigned int kgsl_virtaddr_to_physaddr(void *virtaddr);
unsigned int kgsl_mmu_log_fault_addr(struct kgsl_mmu *mmu,
u64 ttbr0, uint64_t addr);
enum kgsl_mmutype kgsl_mmu_get_mmutype(struct kgsl_device *device);
bool kgsl_mmu_gpuaddr_in_range(struct kgsl_pagetable *pt, uint64_t gpuaddr);
bool kgsl_mmu_gpuaddr_in_range(struct kgsl_pagetable *pt, uint64_t gpuaddr,
uint64_t size);
int kgsl_mmu_get_region(struct kgsl_pagetable *pagetable,
uint64_t gpuaddr, uint64_t size);

7
drivers/soc/qcom/glink_smem_native_xprt.c
View file

@ -701,11 +701,12 @@ static int fifo_tx(struct edge_info *einfo, const void *data, int len)
DEFINE_WAIT(wait);
spin_lock_irqsave(&einfo->write_lock, flags);
while (fifo_write_avail(einfo) < len) {
while (fifo_write_avail(einfo) < len || einfo->tx_blocked_signal_sent) {
send_tx_blocked_signal(einfo);
prepare_to_wait(&einfo->tx_blocked_queue, &wait,
TASK_UNINTERRUPTIBLE);
if (fifo_write_avail(einfo) < len && !einfo->in_ssr) {
if ((fifo_write_avail(einfo) < len
|| einfo->tx_blocked_signal_sent) && !einfo->in_ssr) {
spin_unlock_irqrestore(&einfo->write_lock, flags);
schedule();
spin_lock_irqsave(&einfo->write_lock, flags);
@ -2094,7 +2095,7 @@ static int tx_data(struct glink_transport_if *if_ptr, uint16_t cmd_id,
}
/* Need enough space to write the command and some data */
if (size <= sizeof(cmd)) {
if (size <= sizeof(cmd) || einfo->tx_blocked_signal_sent) {
einfo->tx_resume_needed = true;
send_tx_blocked_signal(einfo);
spin_unlock_irqrestore(&einfo->write_lock, flags);