Here is the bulk of pin control changes for the v4.2 series:
- Core functionality:
- Enable exclusive pin ownership: it is possible to flag a pin
controller so that GPIO and other functions cannot use a single
pin simultaneously.
- New drivers:
- NXP LPC18xx System Control Unit pin controller
- Imagination Pistachio SoC pin controller
- New subdrivers:
- Freescale i.MX7d SoC
- Intel Sunrisepoint-H PCH
- Renesas PFC R8A7793
- Renesas PFC R8A7794
- Mediatek MT6397, MT8127
- SiRF Atlas 7
- Allwinner A33
- Qualcomm MSM8660
- Marvell Armada 395
- Rockchip RK3368
- Cleanups:
- A big cleanup of the Marvell MVEBU driver rectifying it to
correspond to reality
- Drop platform device probing from the SH PFC driver, we are now a
DT only shop for SuperH
- Drop obsolte multi-platform check for SH PFC
- Various janitorial: constification, grammar etc
- Improvements:
- The AT91 GPIO portions now supports the set_multiple() feature
- Split out SPI pins on the Xilinx Zynq
- Support DTs without specific function nodes in the i.MX driver
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Merge tag 'pinctrl-v4.2-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl
Pull pin control updates from Linus Walleij:
"Here is the bulk of pin control changes for the v4.2 series: Quite a
lot of new SoC subdrivers and two new main drivers this time, apart
from that business as usual.
Details:
Core functionality:
- Enable exclusive pin ownership: it is possible to flag a pin
controller so that GPIO and other functions cannot use a single pin
simultaneously.
New drivers:
- NXP LPC18xx System Control Unit pin controller
- Imagination Pistachio SoC pin controller
New subdrivers:
- Freescale i.MX7d SoC
- Intel Sunrisepoint-H PCH
- Renesas PFC R8A7793
- Renesas PFC R8A7794
- Mediatek MT6397, MT8127
- SiRF Atlas 7
- Allwinner A33
- Qualcomm MSM8660
- Marvell Armada 395
- Rockchip RK3368
Cleanups:
- A big cleanup of the Marvell MVEBU driver rectifying it to
correspond to reality
- Drop platform device probing from the SH PFC driver, we are now a
DT only shop for SuperH
- Drop obsolte multi-platform check for SH PFC
- Various janitorial: constification, grammar etc
Improvements:
- The AT91 GPIO portions now supports the set_multiple() feature
- Split out SPI pins on the Xilinx Zynq
- Support DTs without specific function nodes in the i.MX driver"
* tag 'pinctrl-v4.2-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (99 commits)
pinctrl: rockchip: add support for the rk3368
pinctrl: rockchip: generalize perpin driver-strength setting
pinctrl: sh-pfc: r8a7794: add SDHI pin groups
pinctrl: sh-pfc: r8a7794: add MMCIF pin groups
pinctrl: sh-pfc: add R8A7794 PFC support
pinctrl: make pinctrl_register() return proper error code
pinctrl: mvebu: armada-39x: add support for Armada 395 variant
pinctrl: mvebu: armada-39x: add missing SATA functions
pinctrl: mvebu: armada-39x: add missing PCIe functions
pinctrl: mvebu: armada-38x: add ptp functions
pinctrl: mvebu: armada-38x: add ua1 functions
pinctrl: mvebu: armada-38x: add nand functions
pinctrl: mvebu: armada-38x: add sata functions
pinctrl: mvebu: armada-xp: add dram functions
pinctrl: mvebu: armada-xp: add nand rb function
pinctrl: mvebu: armada-xp: add spi1 function
pinctrl: mvebu: armada-39x: normalize ref clock naming
pinctrl: mvebu: armada-xp: rename spi to spi0
pinctrl: mvebu: armada-370: align spi1 clock pin naming
pinctrl: mvebu: armada-370: align VDD cpu-pd pin naming with datasheet
...
This commit is contained in:
Linus Torvalds
commit
93a4b1b946
113 changed files with 18261 additions and 843 deletions
50
Documentation/devicetree/bindings/gpio/gpio-atlas7.txt
Normal file
50
Documentation/devicetree/bindings/gpio/gpio-atlas7.txt
Normal file
|
|
@ -0,0 +1,50 @@
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|||
CSR SiRFatlas7 GPIO controller bindings
|
||||
|
||||
Required properties:
|
||||
- compatible : "sirf,atlas7-gpio"
|
||||
- reg : Address range of the pinctrl registers
|
||||
- interrupts : Interrupts used by every GPIO group
|
||||
- gpio-banks : How many gpio banks on this controller
|
||||
- gpio-controller : Indicates this device is a GPIO controller
|
||||
- interrupt-controller : Marks the device node as an interrupt controller
|
||||
|
||||
The GPIO controller also acts as an interrupt controller. It uses the default
|
||||
two cells specifier as described in Documentation/devicetree/bindings/
|
||||
interrupt-controller/interrupts.txt.
|
||||
|
||||
Example:
|
||||
|
||||
gpio_0: gpio_mediam@17040000 {
|
||||
compatible = "sirf,atlas7-gpio";
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||||
reg = <0x17040000 0x1000>;
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||||
interrupts = <0 13 0>, <0 14 0>;
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||||
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||||
#gpio-cells = <2>;
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||||
#interrupt-cells = <2>;
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||||
|
||||
gpio-controller;
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interrupt-controller;
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||||
|
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gpio-banks = <2>;
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||||
gpio-ranges = <&pinctrl 0 0 0>,
|
||||
<&pinctrl 32 0 0>;
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gpio-ranges-group-names = "lvds_gpio_grp",
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||||
"uart_nand_gpio_grp";
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||||
};
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||||
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||||
leds {
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||||
compatible = "gpio-leds";
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||||
|
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led1 {
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||||
gpios = <&gpio_1 15 0>;
|
||||
...
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||||
};
|
||||
|
||||
led2 {
|
||||
gpios = <&gpio_2 34 0>;
|
||||
...
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||||
};
|
||||
};
|
||||
|
||||
Please refer to gpio.txt in this directory for details of the common
|
||||
gpio properties used by devices.
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||||
|
|
@ -16,6 +16,8 @@ Required properties:
|
|||
"allwinner,sun7i-a20-pinctrl"
|
||||
"allwinner,sun8i-a23-pinctrl"
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||||
"allwinner,sun8i-a23-r-pinctrl"
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||||
"allwinner,sun8i-a33-pinctrl"
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||||
|
||||
- reg: Should contain the register physical address and length for the
|
||||
pin controller.
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||||
|
||||
|
|
|
|||
|
|
@ -0,0 +1,217 @@
|
|||
Imagination Technologies Pistachio SoC pin controllers
|
||||
======================================================
|
||||
|
||||
The pin controllers on Pistachio are a combined GPIO controller, (GPIO)
|
||||
interrupt controller, and pinmux + pinconf device. The system ("east") pin
|
||||
controller on Pistachio has 99 pins, 90 of which are MFIOs which can be
|
||||
configured as GPIOs. The 90 GPIOs are divided into 6 banks of up to 16 GPIOs
|
||||
each. The GPIO banks are represented as sub-nodes of the pad controller node.
|
||||
|
||||
Please refer to pinctrl-bindings.txt, ../gpio/gpio.txt, and
|
||||
../interrupt-controller/interrupts.txt for generic information regarding
|
||||
pin controller, GPIO, and interrupt bindings.
|
||||
|
||||
Required properties for pin controller node:
|
||||
--------------------------------------------
|
||||
- compatible: "img,pistachio-system-pinctrl".
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||||
- reg: Address range of the pinctrl registers.
|
||||
|
||||
Required properties for GPIO bank sub-nodes:
|
||||
--------------------------------------------
|
||||
- interrupts: Interrupt line for the GPIO bank.
|
||||
- gpio-controller: Indicates the device is a GPIO controller.
|
||||
- #gpio-cells: Must be two. The first cell is the GPIO pin number and the
|
||||
second cell indicates the polarity. See <dt-bindings/gpio/gpio.h> for
|
||||
a list of possible values.
|
||||
- interrupt-controller: Indicates the device is an interrupt controller.
|
||||
- #interrupt-cells: Must be two. The first cell is the GPIO pin number and
|
||||
the second cell encodes the interrupt flags. See
|
||||
<dt-bindings/interrupt-controller/irq.h> for a list of valid flags.
|
||||
|
||||
Note that the N GPIO bank sub-nodes *must* be named gpio0, gpio1, ... gpioN-1.
|
||||
|
||||
Required properties for pin configuration sub-nodes:
|
||||
----------------------------------------------------
|
||||
- pins: List of pins to which the configuration applies. See below for a
|
||||
list of possible pins.
|
||||
|
||||
Optional properties for pin configuration sub-nodes:
|
||||
----------------------------------------------------
|
||||
- function: Mux function for the specified pins. This is not applicable for
|
||||
non-MFIO pins. See below for a list of valid functions for each pin.
|
||||
- bias-high-impedance: Enable high-impedance mode.
|
||||
- bias-pull-up: Enable weak pull-up.
|
||||
- bias-pull-down: Enable weak pull-down.
|
||||
- bias-bus-hold: Enable bus-keeper mode.
|
||||
- drive-strength: Drive strength in mA. Supported values: 2, 4, 8, 12.
|
||||
- input-schmitt-enable: Enable Schmitt trigger.
|
||||
- input-schmitt-disable: Disable Schmitt trigger.
|
||||
- slew-rate: Slew rate control. 0 for slow, 1 for fast.
|
||||
|
||||
Pin Functions
|
||||
--- ---------
|
||||
mfio0 spim1
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mfio1 spim1, spim0, uart1
|
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mfio2 spim1, spim0, uart1
|
||||
mfio3 spim1
|
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mfio4 spim1
|
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mfio5 spim1
|
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mfio6 spim1
|
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mfio7 spim1
|
||||
mfio8 spim0
|
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mfio9 spim0
|
||||
mfio10 spim0
|
||||
mfio11 spis
|
||||
mfio12 spis
|
||||
mfio13 spis
|
||||
mfio14 spis
|
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mfio15 sdhost, mips_trace_clk, mips_trace_data
|
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mfio16 sdhost, mips_trace_dint, mips_trace_data
|
||||
mfio17 sdhost, mips_trace_trigout, mips_trace_data
|
||||
mfio18 sdhost, mips_trace_trigin, mips_trace_data
|
||||
mfio19 sdhost, mips_trace_dm, mips_trace_data
|
||||
mfio20 sdhost, mips_trace_probe_n, mips_trace_data
|
||||
mfio21 sdhost, mips_trace_data
|
||||
mfio22 sdhost, mips_trace_data
|
||||
mfio23 sdhost
|
||||
mfio24 sdhost
|
||||
mfio25 sdhost
|
||||
mfio26 sdhost
|
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mfio27 sdhost
|
||||
mfio28 i2c0, spim0
|
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mfio29 i2c0, spim0
|
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mfio30 i2c1, spim0
|
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mfio31 i2c1, spim1
|
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mfio32 i2c2
|
||||
mfio33 i2c2
|
||||
mfio34 i2c3
|
||||
mfio35 i2c3
|
||||
mfio36 i2s_out, audio_clk_in
|
||||
mfio37 i2s_out, debug_raw_cca_ind
|
||||
mfio38 i2s_out, debug_ed_sec20_cca_ind
|
||||
mfio39 i2s_out, debug_ed_sec40_cca_ind
|
||||
mfio40 i2s_out, debug_agc_done_0
|
||||
mfio41 i2s_out, debug_agc_done_1
|
||||
mfio42 i2s_out, debug_ed_cca_ind
|
||||
mfio43 i2s_out, debug_s2l_done
|
||||
mfio44 i2s_out
|
||||
mfio45 i2s_dac_clk, audio_sync
|
||||
mfio46 audio_trigger
|
||||
mfio47 i2s_in
|
||||
mfio48 i2s_in
|
||||
mfio49 i2s_in
|
||||
mfio50 i2s_in
|
||||
mfio51 i2s_in
|
||||
mfio52 i2s_in
|
||||
mfio53 i2s_in
|
||||
mfio54 i2s_in, spdif_in
|
||||
mfio55 uart0, spim0, spim1
|
||||
mfio56 uart0, spim0, spim1
|
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mfio57 uart0, spim0, spim1
|
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mfio58 uart0, spim1
|
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mfio59 uart1
|
||||
mfio60 uart1
|
||||
mfio61 spdif_out
|
||||
mfio62 spdif_in
|
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mfio63 eth, mips_trace_clk, mips_trace_data
|
||||
mfio64 eth, mips_trace_dint, mips_trace_data
|
||||
mfio65 eth, mips_trace_trigout, mips_trace_data
|
||||
mfio66 eth, mips_trace_trigin, mips_trace_data
|
||||
mfio67 eth, mips_trace_dm, mips_trace_data
|
||||
mfio68 eth, mips_trace_probe_n, mips_trace_data
|
||||
mfio69 eth, mips_trace_data
|
||||
mfio70 eth, mips_trace_data
|
||||
mfio71 eth
|
||||
mfio72 ir
|
||||
mfio73 pwmpdm, mips_trace_clk, sram_debug
|
||||
mfio74 pwmpdm, mips_trace_dint, sram_debug
|
||||
mfio75 pwmpdm, mips_trace_trigout, rom_debug
|
||||
mfio76 pwmpdm, mips_trace_trigin, rom_debug
|
||||
mfio77 mdc_debug, mips_trace_dm, rpu_debug
|
||||
mfio78 mdc_debug, mips_trace_probe_n, rpu_debug
|
||||
mfio79 ddr_debug, mips_trace_data, mips_debug
|
||||
mfio80 ddr_debug, mips_trace_data, mips_debug
|
||||
mfio81 dreq0, mips_trace_data, eth_debug
|
||||
mfio82 dreq1, mips_trace_data, eth_debug
|
||||
mfio83 mips_pll_lock, mips_trace_data, usb_debug
|
||||
mfio84 sys_pll_lock, mips_trace_data, usb_debug
|
||||
mfio85 wifi_pll_lock, mips_trace_data, sdhost_debug
|
||||
mfio86 bt_pll_lock, mips_trace_data, sdhost_debug
|
||||
mfio87 rpu_v_pll_lock, dreq2, socif_debug
|
||||
mfio88 rpu_l_pll_lock, dreq3, socif_debug
|
||||
mfio89 audio_pll_lock, dreq4, dreq5
|
||||
tck
|
||||
trstn
|
||||
tdi
|
||||
tms
|
||||
tdo
|
||||
jtag_comply
|
||||
safe_mode
|
||||
por_disable
|
||||
resetn
|
||||
|
||||
Example:
|
||||
--------
|
||||
pinctrl@18101C00 {
|
||||
compatible = "img,pistachio-system-pinctrl";
|
||||
reg = <0x18101C00 0x400>;
|
||||
|
||||
gpio0: gpio0 {
|
||||
interrupts = <GIC_SHARED 71 IRQ_TYPE_LEVEL_HIGH>;
|
||||
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
...
|
||||
|
||||
gpio5: gpio5 {
|
||||
interrupts = <GIC_SHARED 76 IRQ_TYPE_LEVEL_HIGH>;
|
||||
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
...
|
||||
|
||||
uart0_xfer: uart0-xfer {
|
||||
uart0-rxd {
|
||||
pins = "mfio55";
|
||||
function = "uart0";
|
||||
};
|
||||
uart0-txd {
|
||||
pins = "mfio56";
|
||||
function = "uart0";
|
||||
};
|
||||
};
|
||||
|
||||
uart0_rts_cts: uart0-rts-cts {
|
||||
uart0-rts {
|
||||
pins = "mfio57";
|
||||
function = "uart0";
|
||||
};
|
||||
uart0-cts {
|
||||
pins = "mfio58";
|
||||
function = "uart0";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
uart@... {
|
||||
...
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&uart0_xfer>, <&uart0_rts_cts>;
|
||||
...
|
||||
};
|
||||
|
||||
usb_vbus: fixed-regulator {
|
||||
...
|
||||
gpio = <&gpio5 6 GPIO_ACTIVE_HIGH>;
|
||||
...
|
||||
};
|
||||
|
|
@ -17,10 +17,10 @@ mpp0 0 gpio, uart0(rxd)
|
|||
mpp1 1 gpo, uart0(txd)
|
||||
mpp2 2 gpio, i2c0(sck), uart0(txd)
|
||||
mpp3 3 gpio, i2c0(sda), uart0(rxd)
|
||||
mpp4 4 gpio, cpu_pd(vdd)
|
||||
mpp5 5 gpo, ge0(txclko), uart1(txd), spi1(clk), audio(mclk)
|
||||
mpp4 4 gpio, vdd(cpu-pd)
|
||||
mpp5 5 gpo, ge0(txclkout), uart1(txd), spi1(sck), audio(mclk)
|
||||
mpp6 6 gpio, ge0(txd0), sata0(prsnt), tdm(rst), audio(sdo)
|
||||
mpp7 7 gpo, ge0(txd1), tdm(tdx), audio(lrclk)
|
||||
mpp7 7 gpo, ge0(txd1), tdm(dtx), audio(lrclk)
|
||||
mpp8 8 gpio, ge0(txd2), uart0(rts), tdm(drx), audio(bclk)
|
||||
mpp9 9 gpo, ge0(txd3), uart1(txd), sd0(clk), audio(spdifo)
|
||||
mpp10 10 gpio, ge0(txctl), uart0(cts), tdm(fsync), audio(sdi)
|
||||
|
|
@ -52,8 +52,8 @@ mpp30 30 gpio, ge0(rxd7), ge1(rxclk), i2c1(sck)
|
|||
mpp31 31 gpio, tclk, ge0(txerr)
|
||||
mpp32 32 gpio, spi0(cs0)
|
||||
mpp33 33 gpio, dev(bootcs), spi0(cs0)
|
||||
mpp34 34 gpo, dev(wen0), spi0(mosi)
|
||||
mpp35 35 gpo, dev(oen), spi0(sck)
|
||||
mpp34 34 gpo, dev(we0), spi0(mosi)
|
||||
mpp35 35 gpo, dev(oe), spi0(sck)
|
||||
mpp36 36 gpo, dev(a1), spi0(miso)
|
||||
mpp37 37 gpo, dev(a0), sata0(prsnt)
|
||||
mpp38 38 gpio, dev(ready), uart1(cts), uart0(cts)
|
||||
|
|
@ -86,11 +86,11 @@ mpp57 57 gpio, dev(cs3), uart1(rxd), tdm(fsync), sata0(prsnt),
|
|||
mpp58 58 gpio, dev(cs0), uart1(rts), tdm(int), audio(extclk),
|
||||
uart0(rts)
|
||||
mpp59 59 gpo, dev(ale0), uart1(rts), uart0(rts), audio(bclk)
|
||||
mpp60 60 gpio, dev(ale1), uart1(rxd), sata0(prsnt), pcie(rst-out),
|
||||
mpp60 60 gpio, dev(ale1), uart1(rxd), sata0(prsnt), pcie(rstout),
|
||||
audio(sdi)
|
||||
mpp61 61 gpo, dev(wen1), uart1(txd), audio(rclk)
|
||||
mpp61 61 gpo, dev(we1), uart1(txd), audio(lrclk)
|
||||
mpp62 62 gpio, dev(a2), uart1(cts), tdm(drx), pcie(clkreq0),
|
||||
audio(mclk), uart0(cts)
|
||||
mpp63 63 gpo, spi0(sck), tclk
|
||||
mpp64 64 gpio, spi0(miso), spi0-1(cs1)
|
||||
mpp65 65 gpio, spi0(mosi), spi0-1(cs2)
|
||||
mpp64 64 gpio, spi0(miso), spi0(cs1)
|
||||
mpp65 65 gpio, spi0(mosi), spi0(cs2)
|
||||
|
|
|
|||
|
|
@ -15,24 +15,24 @@ name pins functions
|
|||
================================================================================
|
||||
mpp0 0 gpio, dev(ad2), spi0(cs1), spi1(cs1)
|
||||
mpp1 1 gpio, dev(ad3), spi0(mosi), spi1(mosi)
|
||||
mpp2 2 gpio, dev(ad4), ptp(eventreq), led(c0), audio(sdi)
|
||||
mpp3 3 gpio, dev(ad5), ptp(triggen), led(p3), audio(mclk)
|
||||
mpp2 2 gpio, dev(ad4), ptp(evreq), led(c0), audio(sdi)
|
||||
mpp3 3 gpio, dev(ad5), ptp(trig), led(p3), audio(mclk)
|
||||
mpp4 4 gpio, dev(ad6), spi0(miso), spi1(miso)
|
||||
mpp5 5 gpio, dev(ad7), spi0(cs2), spi1(cs2)
|
||||
mpp6 6 gpio, dev(ad0), led(p1), audio(rclk)
|
||||
mpp6 6 gpio, dev(ad0), led(p1), audio(lrclk)
|
||||
mpp7 7 gpio, dev(ad1), ptp(clk), led(p2), audio(extclk)
|
||||
mpp8 8 gpio, dev (bootcs), spi0(cs0), spi1(cs0)
|
||||
mpp9 9 gpio, nf(wen), spi0(sck), spi1(sck)
|
||||
mpp10 10 gpio, nf(ren), dram(vttctrl), led(c1)
|
||||
mpp9 9 gpio, spi0(sck), spi1(sck), nand(we)
|
||||
mpp10 10 gpio, dram(vttctrl), led(c1), nand(re)
|
||||
mpp11 11 gpio, dev(a0), led(c2), audio(sdo)
|
||||
mpp12 12 gpio, dev(a1), audio(bclk)
|
||||
mpp13 13 gpio, dev(readyn), pcie0(rstoutn), pcie1(rstoutn)
|
||||
mpp13 13 gpio, dev(ready), pcie0(rstout), pcie1(rstout)
|
||||
mpp14 14 gpio, i2c0(sda), uart1(txd)
|
||||
mpp15 15 gpio, i2c0(sck), uart1(rxd)
|
||||
mpp16 16 gpio, uart0(txd)
|
||||
mpp17 17 gpio, uart0(rxd)
|
||||
mpp18 18 gpio, tdm(intn)
|
||||
mpp19 19 gpio, tdm(rstn)
|
||||
mpp18 18 gpio, tdm(int)
|
||||
mpp19 19 gpio, tdm(rst)
|
||||
mpp20 20 gpio, tdm(pclk)
|
||||
mpp21 21 gpio, tdm(fsync)
|
||||
mpp22 22 gpio, tdm(drx)
|
||||
|
|
@ -45,12 +45,12 @@ mpp28 28 gpio, led(p3), ge1(txctl), sd(clk)
|
|||
mpp29 29 gpio, pcie1(clkreq), ge1(rxclk), sd(d3)
|
||||
mpp30 30 gpio, ge1(txd0), spi1(cs0)
|
||||
mpp31 31 gpio, ge1(txd1), spi1(mosi)
|
||||
mpp32 32 gpio, ge1(txd2), spi1(sck), ptp(triggen)
|
||||
mpp32 32 gpio, ge1(txd2), spi1(sck), ptp(trig)
|
||||
mpp33 33 gpio, ge1(txd3), spi1(miso)
|
||||
mpp34 34 gpio, ge1(txclkout), spi1(sck)
|
||||
mpp35 35 gpio, ge1(rxctl), spi1(cs1), spi0(cs2)
|
||||
mpp36 36 gpio, pcie0(clkreq)
|
||||
mpp37 37 gpio, pcie0(clkreq), tdm(intn), ge(mdc)
|
||||
mpp37 37 gpio, pcie0(clkreq), tdm(int), ge(mdc)
|
||||
mpp38 38 gpio, pcie1(clkreq), ge(mdio)
|
||||
mpp39 39 gpio, ref(clkout)
|
||||
mpp40 40 gpio, uart1(txd)
|
||||
|
|
@ -58,25 +58,25 @@ mpp41 41 gpio, uart1(rxd)
|
|||
mpp42 42 gpio, spi1(cs2), led(c0)
|
||||
mpp43 43 gpio, sata0(prsnt), dram(vttctrl)
|
||||
mpp44 44 gpio, sata0(prsnt)
|
||||
mpp45 45 gpio, spi0(cs2), pcie0(rstoutn)
|
||||
mpp46 46 gpio, led(p0), ge0(txd0), ge1(txd0)
|
||||
mpp45 45 gpio, spi0(cs2), pcie0(rstout)
|
||||
mpp46 46 gpio, led(p0), ge0(txd0), ge1(txd0), dev(we1)
|
||||
mpp47 47 gpio, led(p1), ge0(txd1), ge1(txd1)
|
||||
mpp48 48 gpio, led(p2), ge0(txd2), ge1(txd2)
|
||||
mpp49 49 gpio, led(p3), ge0(txd3), ge1(txd3)
|
||||
mpp50 50 gpio, led(c0), ge0(rxd0), ge1(rxd0)
|
||||
mpp51 51 gpio, led(c1), ge0(rxd1), ge1(rxd1)
|
||||
mpp52 52 gpio, led(c2), ge0(rxd2), ge1(rxd2)
|
||||
mpp53 53 gpio, pcie1(rstoutn), ge0(rxd3), ge1(rxd3)
|
||||
mpp54 54 gpio, pcie0(rstoutn), ge0(rxctl), ge1(rxctl)
|
||||
mpp53 53 gpio, pcie1(rstout), ge0(rxd3), ge1(rxd3)
|
||||
mpp54 54 gpio, pcie0(rstout), ge0(rxctl), ge1(rxctl)
|
||||
mpp55 55 gpio, ge0(rxclk), ge1(rxclk)
|
||||
mpp56 56 gpio, ge0(txclkout), ge1(txclkout)
|
||||
mpp57 57 gpio, ge0(txctl), ge1(txctl)
|
||||
mpp57 57 gpio, ge0(txctl), ge1(txctl), dev(we0)
|
||||
mpp58 58 gpio, led(c0)
|
||||
mpp59 59 gpio, led(c1)
|
||||
mpp60 60 gpio, uart1(txd), led(c2)
|
||||
mpp61 61 gpio, i2c1(sda), uart1(rxd), spi1(cs2), led(p0)
|
||||
mpp62 62 gpio, i2c1(sck), led(p1)
|
||||
mpp63 63 gpio, ptp(triggen), led(p2)
|
||||
mpp63 63 gpio, ptp(trig), led(p2), dev(burst/last)
|
||||
mpp64 64 gpio, dram(vttctrl), led(p3)
|
||||
mpp65 65 gpio, sata1(prsnt)
|
||||
mpp66 66 gpio, ptp(eventreq), spi1(cs3)
|
||||
mpp66 66 gpio, ptp(evreq), spi1(cs3)
|
||||
|
|
|
|||
|
|
@ -27,16 +27,16 @@ mpp8 8 gpio, ge0(txd1), dev(ad10)
|
|||
mpp9 9 gpio, ge0(txd2), dev(ad11)
|
||||
mpp10 10 gpio, ge0(txd3), dev(ad12)
|
||||
mpp11 11 gpio, ge0(txctl), dev(ad13)
|
||||
mpp12 12 gpio, ge0(rxd0), pcie0(rstout), pcie1(rstout) [1], spi0(cs1), dev(ad14)
|
||||
mpp13 13 gpio, ge0(rxd1), pcie0(clkreq), pcie1(clkreq) [1], spi0(cs2), dev(ad15)
|
||||
mpp14 14 gpio, ge0(rxd2), ptp(clk), m(vtt_ctrl), spi0(cs3), dev(wen1)
|
||||
mpp15 15 gpio, ge0(rxd3), ge(mdc slave), pcie0(rstout), spi0(mosi), pcie1(rstout) [1]
|
||||
mpp16 16 gpio, ge0(rxctl), ge(mdio slave), m(decc_err), spi0(miso), pcie0(clkreq)
|
||||
mpp17 17 gpio, ge0(rxclk), ptp(clk), ua1(rxd), spi0(sck), sata1(prsnt)
|
||||
mpp18 18 gpio, ge0(rxerr), ptp(trig_gen), ua1(txd), spi0(cs0), pcie1(rstout) [1]
|
||||
mpp19 19 gpio, ge0(col), ptp(event_req), pcie0(clkreq), sata1(prsnt), ua0(cts)
|
||||
mpp20 20 gpio, ge0(txclk), ptp(clk), pcie1(rstout) [1], sata0(prsnt), ua0(rts)
|
||||
mpp21 21 gpio, spi0(cs1), ge1(rxd0), sata0(prsnt), sd0(cmd), dev(bootcs)
|
||||
mpp12 12 gpio, ge0(rxd0), pcie0(rstout), spi0(cs1), dev(ad14), pcie3(clkreq)
|
||||
mpp13 13 gpio, ge0(rxd1), pcie0(clkreq), pcie1(clkreq) [1], spi0(cs2), dev(ad15), pcie2(clkreq)
|
||||
mpp14 14 gpio, ge0(rxd2), ptp(clk), dram(vttctrl), spi0(cs3), dev(we1), pcie3(clkreq)
|
||||
mpp15 15 gpio, ge0(rxd3), ge(mdc slave), pcie0(rstout), spi0(mosi)
|
||||
mpp16 16 gpio, ge0(rxctl), ge(mdio slave), dram(deccerr), spi0(miso), pcie0(clkreq), pcie1(clkreq) [1]
|
||||
mpp17 17 gpio, ge0(rxclk), ptp(clk), ua1(rxd), spi0(sck), sata1(prsnt), sata0(prsnt)
|
||||
mpp18 18 gpio, ge0(rxerr), ptp(trig), ua1(txd), spi0(cs0)
|
||||
mpp19 19 gpio, ge0(col), ptp(evreq), ge0(txerr), sata1(prsnt), ua0(cts)
|
||||
mpp20 20 gpio, ge0(txclk), ptp(clk), sata0(prsnt), ua0(rts)
|
||||
mpp21 21 gpio, spi0(cs1), ge1(rxd0), sata0(prsnt), sd0(cmd), dev(bootcs), sata1(prsnt)
|
||||
mpp22 22 gpio, spi0(mosi), dev(ad0)
|
||||
mpp23 23 gpio, spi0(sck), dev(ad2)
|
||||
mpp24 24 gpio, spi0(miso), ua0(cts), ua1(rxd), sd0(d4), dev(ready)
|
||||
|
|
@ -45,36 +45,36 @@ mpp26 26 gpio, spi0(cs2), i2c1(sck), sd0(d6), dev(cs1)
|
|||
mpp27 27 gpio, spi0(cs3), ge1(txclkout), i2c1(sda), sd0(d7), dev(cs2)
|
||||
mpp28 28 gpio, ge1(txd0), sd0(clk), dev(ad5)
|
||||
mpp29 29 gpio, ge1(txd1), dev(ale0)
|
||||
mpp30 30 gpio, ge1(txd2), dev(oen)
|
||||
mpp30 30 gpio, ge1(txd2), dev(oe)
|
||||
mpp31 31 gpio, ge1(txd3), dev(ale1)
|
||||
mpp32 32 gpio, ge1(txctl), dev(wen0)
|
||||
mpp33 33 gpio, m(decc_err), dev(ad3)
|
||||
mpp32 32 gpio, ge1(txctl), dev(we0)
|
||||
mpp33 33 gpio, dram(deccerr), dev(ad3)
|
||||
mpp34 34 gpio, dev(ad1)
|
||||
mpp35 35 gpio, ref(clk_out1), dev(a1)
|
||||
mpp36 36 gpio, ptp(trig_gen), dev(a0)
|
||||
mpp36 36 gpio, ptp(trig), dev(a0)
|
||||
mpp37 37 gpio, ptp(clk), ge1(rxclk), sd0(d3), dev(ad8)
|
||||
mpp38 38 gpio, ptp(event_req), ge1(rxd1), ref(clk_out0), sd0(d0), dev(ad4)
|
||||
mpp38 38 gpio, ptp(evreq), ge1(rxd1), ref(clk_out0), sd0(d0), dev(ad4)
|
||||
mpp39 39 gpio, i2c1(sck), ge1(rxd2), ua0(cts), sd0(d1), dev(a2)
|
||||
mpp40 40 gpio, i2c1(sda), ge1(rxd3), ua0(rts), sd0(d2), dev(ad6)
|
||||
mpp41 41 gpio, ua1(rxd), ge1(rxctl), ua0(cts), spi1(cs3), dev(burst/last)
|
||||
mpp41 41 gpio, ua1(rxd), ge1(rxctl), ua0(cts), spi1(cs3), dev(burst/last), nand(rb0)
|
||||
mpp42 42 gpio, ua1(txd), ua0(rts), dev(ad7)
|
||||
mpp43 43 gpio, pcie0(clkreq), m(vtt_ctrl), m(decc_err), pcie0(rstout), dev(clkout)
|
||||
mpp44 44 gpio, sata0(prsnt), sata1(prsnt), sata2(prsnt) [2], sata3(prsnt) [3], pcie0(rstout)
|
||||
mpp45 45 gpio, ref(clk_out0), pcie0(rstout), pcie1(rstout) [1], pcie2(rstout), pcie3(rstout)
|
||||
mpp46 46 gpio, ref(clk_out1), pcie0(rstout), pcie1(rstout) [1], pcie2(rstout), pcie3(rstout)
|
||||
mpp47 47 gpio, sata0(prsnt), sata1(prsnt), sata2(prsnt) [2], spi1(cs2), sata3(prsnt) [2]
|
||||
mpp48 48 gpio, sata0(prsnt), m(vtt_ctrl), tdm2c(pclk), audio(mclk), sd0(d4)
|
||||
mpp49 49 gpio, sata2(prsnt) [2], sata3(prsnt) [2], tdm2c(fsync), audio(lrclk), sd0(d5)
|
||||
mpp50 50 gpio, pcie0(rstout), pcie1(rstout) [1], tdm2c(drx), audio(extclk), sd0(cmd)
|
||||
mpp51 51 gpio, tdm2c(dtx), audio(sdo), m(decc_err)
|
||||
mpp52 52 gpio, pcie0(rstout), pcie1(rstout) [1], tdm2c(intn), audio(sdi), sd0(d6)
|
||||
mpp53 53 gpio, sata1(prsnt), sata0(prsnt), tdm2c(rstn), audio(bclk), sd0(d7)
|
||||
mpp54 54 gpio, sata0(prsnt), sata1(prsnt), pcie0(rstout), pcie1(rstout) [1], sd0(d3)
|
||||
mpp55 55 gpio, ua1(cts), ge(mdio), pcie1(clkreq) [1], spi1(cs1), sd0(d0)
|
||||
mpp56 56 gpio, ua1(rts), ge(mdc), m(decc_err), spi1(mosi)
|
||||
mpp57 57 gpio, spi1(sck), sd0(clk)
|
||||
mpp58 58 gpio, pcie1(clkreq) [1], i2c1(sck), pcie2(clkreq), spi1(miso), sd0(d1)
|
||||
mpp59 59 gpio, pcie0(rstout), i2c1(sda), pcie1(rstout) [1], spi1(cs0), sd0(d2)
|
||||
mpp43 43 gpio, pcie0(clkreq), dram(vttctrl), dram(deccerr), spi1(cs2), dev(clkout), nand(rb1)
|
||||
mpp44 44 gpio, sata0(prsnt), sata1(prsnt), sata2(prsnt) [2], sata3(prsnt) [3]
|
||||
mpp45 45 gpio, ref(clk_out0), pcie0(rstout), ua1(rxd)
|
||||
mpp46 46 gpio, ref(clk_out1), pcie0(rstout), ua1(txd)
|
||||
mpp47 47 gpio, sata0(prsnt), sata1(prsnt), sata2(prsnt) [2], sata3(prsnt) [2]
|
||||
mpp48 48 gpio, sata0(prsnt), dram(vttctrl), tdm(pclk), audio(mclk), sd0(d4), pcie0(clkreq)
|
||||
mpp49 49 gpio, sata2(prsnt) [2], sata3(prsnt) [2], tdm(fsync), audio(lrclk), sd0(d5), pcie1(clkreq)
|
||||
mpp50 50 gpio, pcie0(rstout), tdm(drx), audio(extclk), sd0(cmd)
|
||||
mpp51 51 gpio, tdm(dtx), audio(sdo), dram(deccerr), ptp(trig)
|
||||
mpp52 52 gpio, pcie0(rstout), tdm(int), audio(sdi), sd0(d6), ptp(clk)
|
||||
mpp53 53 gpio, sata1(prsnt), sata0(prsnt), tdm(rst), audio(bclk), sd0(d7), ptp(evreq)
|
||||
mpp54 54 gpio, sata0(prsnt), sata1(prsnt), pcie0(rstout), ge0(txerr), sd0(d3)
|
||||
mpp55 55 gpio, ua1(cts), ge(mdio), pcie1(clkreq) [1], spi1(cs1), sd0(d0), ua1(rxd)
|
||||
mpp56 56 gpio, ua1(rts), ge(mdc), dram(deccerr), spi1(mosi), ua1(txd)
|
||||
mpp57 57 gpio, spi1(sck), sd0(clk), ua1(txd)
|
||||
mpp58 58 gpio, pcie1(clkreq) [1], i2c1(sck), pcie2(clkreq), spi1(miso), sd0(d1), ua1(rxd)
|
||||
mpp59 59 gpio, pcie0(rstout), i2c1(sda), spi1(cs0), sd0(d2)
|
||||
|
||||
[1]: only available on 88F6820 and 88F6828
|
||||
[2]: only available on 88F6828
|
||||
|
|
|
|||
|
|
@ -4,8 +4,9 @@ Please refer to marvell,mvebu-pinctrl.txt in this directory for common binding
|
|||
part and usage.
|
||||
|
||||
Required properties:
|
||||
- compatible: "marvell,88f6920-pinctrl", "marvell,88f6928-pinctrl"
|
||||
depending on the specific variant of the SoC being used.
|
||||
- compatible: "marvell,88f6920-pinctrl", "marvell,88f6925-pinctrl" or
|
||||
"marvell,88f6928-pinctrl" depending on the specific variant of the
|
||||
SoC being used.
|
||||
- reg: register specifier of MPP registers
|
||||
|
||||
Available mpp pins/groups and functions:
|
||||
|
|
@ -24,55 +25,60 @@ mpp6 6 gpio, dev(cs3), xsmi(mdio)
|
|||
mpp7 7 gpio, dev(ad9), xsmi(mdc)
|
||||
mpp8 8 gpio, dev(ad10), ptp(trig)
|
||||
mpp9 9 gpio, dev(ad11), ptp(clk)
|
||||
mpp10 10 gpio, dev(ad12), ptp(event)
|
||||
mpp10 10 gpio, dev(ad12), ptp(evreq)
|
||||
mpp11 11 gpio, dev(ad13), led(clk)
|
||||
mpp12 12 gpio, pcie0(rstout), dev(ad14), led(stb)
|
||||
mpp13 13 gpio, dev(ad15), led(data)
|
||||
mpp14 14 gpio, m(vtt), dev(wen1), ua1(txd)
|
||||
mpp13 13 gpio, dev(ad15), pcie2(clkreq), led(data)
|
||||
mpp14 14 gpio, dram(vttctrl), dev(we1), ua1(txd)
|
||||
mpp15 15 gpio, pcie0(rstout), spi0(mosi), i2c1(sck)
|
||||
mpp16 16 gpio, m(decc), spi0(miso), i2c1(sda)
|
||||
mpp17 17 gpio, ua1(rxd), spi0(sck), smi(mdio)
|
||||
mpp16 16 gpio, dram(deccerr), spi0(miso), pcie0(clkreq), i2c1(sda)
|
||||
mpp17 17 gpio, ua1(rxd), spi0(sck), sata1(prsnt) [1], sata0(prsnt) [1], smi(mdio)
|
||||
mpp18 18 gpio, ua1(txd), spi0(cs0), i2c2(sck)
|
||||
mpp19 19 gpio, sata1(present) [1], ua0(cts), ua1(rxd), i2c2(sda)
|
||||
mpp20 20 gpio, sata0(present) [1], ua0(rts), ua1(txd), smi(mdc)
|
||||
mpp21 21 gpio, spi0(cs1), sata0(present) [1], sd(cmd), dev(bootcs), ge(rxd0)
|
||||
mpp19 19 gpio, sata1(prsnt) [1], ua0(cts), ua1(rxd), i2c2(sda)
|
||||
mpp20 20 gpio, sata0(prsnt) [1], ua0(rts), ua1(txd), smi(mdc)
|
||||
mpp21 21 gpio, spi0(cs1), sata0(prsnt) [1], sd0(cmd), dev(bootcs),
|
||||
sata1(prsnt) [1], ge(rxd0)
|
||||
mpp22 22 gpio, spi0(mosi), dev(ad0)
|
||||
mpp23 23 gpio, spi0(sck), dev(ad2)
|
||||
mpp24 24 gpio, spi0(miso), ua0(cts), ua1(rxd), sd(d4), dev(readyn)
|
||||
mpp25 25 gpio, spi0(cs0), ua0(rts), ua1(txd), sd(d5), dev(cs0)
|
||||
mpp26 26 gpio, spi0(cs2), i2c1(sck), sd(d6), dev(cs1)
|
||||
mpp27 27 gpio, spi0(cs3), i2c1(sda), sd(d7), dev(cs2), ge(txclkout)
|
||||
mpp28 28 gpio, sd(clk), dev(ad5), ge(txd0)
|
||||
mpp24 24 gpio, spi0(miso), ua0(cts), ua1(rxd), sd0(d4), dev(ready)
|
||||
mpp25 25 gpio, spi0(cs0), ua0(rts), ua1(txd), sd0(d5), dev(cs0)
|
||||
mpp26 26 gpio, spi0(cs2), i2c1(sck), sd0(d6), dev(cs1)
|
||||
mpp27 27 gpio, spi0(cs3), i2c1(sda), sd0(d7), dev(cs2), ge(txclkout)
|
||||
mpp28 28 gpio, sd0(clk), dev(ad5), ge(txd0)
|
||||
mpp29 29 gpio, dev(ale0), ge(txd1)
|
||||
mpp30 30 gpio, dev(oen), ge(txd2)
|
||||
mpp30 30 gpio, dev(oe), ge(txd2)
|
||||
mpp31 31 gpio, dev(ale1), ge(txd3)
|
||||
mpp32 32 gpio, dev(wen0), ge(txctl)
|
||||
mpp33 33 gpio, m(decc), dev(ad3)
|
||||
mpp32 32 gpio, dev(we0), ge(txctl)
|
||||
mpp33 33 gpio, dram(deccerr), dev(ad3)
|
||||
mpp34 34 gpio, dev(ad1)
|
||||
mpp35 35 gpio, ref(clk), dev(a1)
|
||||
mpp36 36 gpio, dev(a0)
|
||||
mpp37 37 gpio, sd(d3), dev(ad8), ge(rxclk)
|
||||
mpp38 38 gpio, ref(clk), sd(d0), dev(ad4), ge(rxd1)
|
||||
mpp39 39 gpio, i2c1(sck), ua0(cts), sd(d1), dev(a2), ge(rxd2)
|
||||
mpp40 40 gpio, i2c1(sda), ua0(rts), sd(d2), dev(ad6), ge(rxd3)
|
||||
mpp41 41 gpio, ua1(rxd), ua0(cts), spi1(cs3), dev(burstn), nd(rbn0), ge(rxctl)
|
||||
mpp37 37 gpio, sd0(d3), dev(ad8), ge(rxclk)
|
||||
mpp38 38 gpio, ref(clk), sd0(d0), dev(ad4), ge(rxd1)
|
||||
mpp39 39 gpio, i2c1(sck), ua0(cts), sd0(d1), dev(a2), ge(rxd2)
|
||||
mpp40 40 gpio, i2c1(sda), ua0(rts), sd0(d2), dev(ad6), ge(rxd3)
|
||||
mpp41 41 gpio, ua1(rxd), ua0(cts), spi1(cs3), dev(burst/last), nand(rb0), ge(rxctl)
|
||||
mpp42 42 gpio, ua1(txd), ua0(rts), dev(ad7)
|
||||
mpp43 43 gpio, pcie0(clkreq), m(vtt), m(decc), spi1(cs2), dev(clkout), nd(rbn1)
|
||||
mpp44 44 gpio, sata0(present) [1], sata1(present) [1], led(clk)
|
||||
mpp43 43 gpio, pcie0(clkreq), dram(vttctrl), dram(deccerr), spi1(cs2), dev(clkout), nand(rb1)
|
||||
mpp44 44 gpio, sata0(prsnt) [1], sata1(prsnt) [1], sata2(prsnt) [2],
|
||||
sata3(prsnt) [2], led(clk)
|
||||
mpp45 45 gpio, ref(clk), pcie0(rstout), ua1(rxd)
|
||||
mpp46 46 gpio, ref(clk), pcie0(rstout), ua1(txd), led(stb)
|
||||
mpp47 47 gpio, sata0(present) [1], sata1(present) [1], led(data)
|
||||
mpp48 48 gpio, sata0(present) [1], m(vtt), tdm(pclk) [1], audio(mclk) [1], sd(d4), pcie0(clkreq), ua1(txd)
|
||||
mpp49 49 gpio, tdm(fsync) [1], audio(lrclk) [1], sd(d5), ua2(rxd)
|
||||
mpp50 50 gpio, pcie0(rstout), tdm(drx) [1], audio(extclk) [1], sd(cmd), ua2(rxd)
|
||||
mpp51 51 gpio, tdm(dtx) [1], audio(sdo) [1], m(decc), ua2(txd)
|
||||
mpp52 52 gpio, pcie0(rstout), tdm(intn) [1], audio(sdi) [1], sd(d6), i2c3(sck)
|
||||
mpp53 53 gpio, sata1(present) [1], sata0(present) [1], tdm(rstn) [1], audio(bclk) [1], sd(d7), i2c3(sda)
|
||||
mpp54 54 gpio, sata0(present) [1], sata1(present) [1], pcie0(rstout), sd(d3), ua3(txd)
|
||||
mpp55 55 gpio, ua1(cts), spi1(cs1), sd(d0), ua1(rxd), ua3(rxd)
|
||||
mpp56 56 gpio, ua1(rts), m(decc), spi1(mosi), ua1(txd)
|
||||
mpp57 57 gpio, spi1(sck), sd(clk), ua1(txd)
|
||||
mpp58 58 gpio, i2c1(sck), pcie2(clkreq), spi1(miso), sd(d1), ua1(rxd)
|
||||
mpp59 59 gpio, pcie0(rstout), i2c1(sda), spi1(cs0), sd(d2)
|
||||
mpp47 47 gpio, sata0(prsnt) [1], sata1(prsnt) [1], sata2(prsnt) [2],
|
||||
sata3(prsnt) [2], led(data)
|
||||
mpp48 48 gpio, sata0(prsnt) [1], dram(vttctrl), tdm(pclk) [2], audio(mclk) [2], sd0(d4), pcie0(clkreq), ua1(txd)
|
||||
mpp49 49 gpio, sata2(prsnt) [2], sata3(prsnt) [2], tdm(fsync) [2],
|
||||
audio(lrclk) [2], sd0(d5), ua2(rxd)
|
||||
mpp50 50 gpio, pcie0(rstout), tdm(drx) [2], audio(extclk) [2], sd0(cmd), ua2(rxd)
|
||||
mpp51 51 gpio, tdm(dtx) [2], audio(sdo) [2], dram(deccerr), ua2(txd)
|
||||
mpp52 52 gpio, pcie0(rstout), tdm(int) [2], audio(sdi) [2], sd0(d6), i2c3(sck)
|
||||
mpp53 53 gpio, sata1(prsnt) [1], sata0(prsnt) [1], tdm(rst) [2], audio(bclk) [2], sd0(d7), i2c3(sda)
|
||||
mpp54 54 gpio, sata0(prsnt) [1], sata1(prsnt) [1], pcie0(rstout), sd0(d3), ua3(txd)
|
||||
mpp55 55 gpio, ua1(cts), spi1(cs1), sd0(d0), ua1(rxd), ua3(rxd)
|
||||
mpp56 56 gpio, ua1(rts), dram(deccerr), spi1(mosi), ua1(txd)
|
||||
mpp57 57 gpio, spi1(sck), sd0(clk), ua1(txd)
|
||||
mpp58 58 gpio, i2c1(sck), pcie2(clkreq), spi1(miso), sd0(d1), ua1(rxd)
|
||||
mpp59 59 gpio, pcie0(rstout), i2c1(sda), spi1(cs0), sd0(d2)
|
||||
|
||||
[1]: only available on 88F6928
|
||||
[1]: only available on 88F6925/88F6928
|
||||
[2]: only available on 88F6928
|
||||
|
|
|
|||
|
|
@ -18,7 +18,7 @@ only for more detailed description in this document.
|
|||
|
||||
name pins functions
|
||||
================================================================================
|
||||
mpp0 0 gpio, ge0(txclko), lcd(d0)
|
||||
mpp0 0 gpio, ge0(txclkout), lcd(d0)
|
||||
mpp1 1 gpio, ge0(txd0), lcd(d1)
|
||||
mpp2 2 gpio, ge0(txd1), lcd(d2)
|
||||
mpp3 3 gpio, ge0(txd2), lcd(d3)
|
||||
|
|
@ -30,49 +30,50 @@ mpp8 8 gpio, ge0(rxd2), lcd(d8)
|
|||
mpp9 9 gpio, ge0(rxd3), lcd(d9)
|
||||
mpp10 10 gpio, ge0(rxctl), lcd(d10)
|
||||
mpp11 11 gpio, ge0(rxclk), lcd(d11)
|
||||
mpp12 12 gpio, ge0(txd4), ge1(txd0), lcd(d12)
|
||||
mpp13 13 gpio, ge0(txd5), ge1(txd1), lcd(d13)
|
||||
mpp14 14 gpio, ge0(txd6), ge1(txd2), lcd(d15)
|
||||
mpp15 15 gpio, ge0(txd7), ge1(txd3), lcd(d16)
|
||||
mpp16 16 gpio, ge0(txd7), ge1(txd3), lcd(d16)
|
||||
mpp17 17 gpio, ge0(col), ge1(txctl), lcd(d17)
|
||||
mpp12 12 gpio, ge0(txd4), ge1(txclkout), lcd(d12)
|
||||
mpp13 13 gpio, ge0(txd5), ge1(txd0), spi1(mosi), lcd(d13)
|
||||
mpp14 14 gpio, ge0(txd6), ge1(txd1), spi1(sck), lcd(d15)
|
||||
mpp15 15 gpio, ge0(txd7), ge1(txd2), lcd(d16)
|
||||
mpp16 16 gpio, ge0(txd7), ge1(txd3), spi1(cs0), lcd(d16)
|
||||
mpp17 17 gpio, ge0(col), ge1(txctl), spi1(miso), lcd(d17)
|
||||
mpp18 18 gpio, ge0(rxerr), ge1(rxd0), lcd(d18), ptp(trig)
|
||||
mpp19 19 gpio, ge0(crs), ge1(rxd1), lcd(d19), ptp(evreq)
|
||||
mpp20 20 gpio, ge0(rxd4), ge1(rxd2), lcd(d20), ptp(clk)
|
||||
mpp21 21 gpio, ge0(rxd5), ge1(rxd3), lcd(d21), mem(bat)
|
||||
mpp21 21 gpio, ge0(rxd5), ge1(rxd3), lcd(d21), dram(bat)
|
||||
mpp22 22 gpio, ge0(rxd6), ge1(rxctl), lcd(d22), sata0(prsnt)
|
||||
mpp23 23 gpio, ge0(rxd7), ge1(rxclk), lcd(d23), sata1(prsnt)
|
||||
mpp24 24 gpio, lcd(hsync), sata1(prsnt), nf(bootcs-re), tdm(rst)
|
||||
mpp25 25 gpio, lcd(vsync), sata0(prsnt), nf(bootcs-we), tdm(pclk)
|
||||
mpp26 26 gpio, lcd(clk), tdm(fsync), vdd(cpu1-pd)
|
||||
mpp24 24 gpio, lcd(hsync), sata1(prsnt), tdm(rst)
|
||||
mpp25 25 gpio, lcd(vsync), sata0(prsnt), tdm(pclk)
|
||||
mpp26 26 gpio, lcd(clk), tdm(fsync)
|
||||
mpp27 27 gpio, lcd(e), tdm(dtx), ptp(trig)
|
||||
mpp28 28 gpio, lcd(pwm), tdm(drx), ptp(evreq)
|
||||
mpp29 29 gpio, lcd(ref-clk), tdm(int0), ptp(clk), vdd(cpu0-pd)
|
||||
mpp29 29 gpio, lcd(ref-clk), tdm(int0), ptp(clk)
|
||||
mpp30 30 gpio, tdm(int1), sd0(clk)
|
||||
mpp31 31 gpio, tdm(int2), sd0(cmd), vdd(cpu0-pd)
|
||||
mpp32 32 gpio, tdm(int3), sd0(d0), vdd(cpu1-pd)
|
||||
mpp33 33 gpio, tdm(int4), sd0(d1), mem(bat)
|
||||
mpp34 34 gpio, tdm(int5), sd0(d2), sata0(prsnt)
|
||||
mpp31 31 gpio, tdm(int2), sd0(cmd)
|
||||
mpp32 32 gpio, tdm(int3), sd0(d0)
|
||||
mpp33 33 gpio, tdm(int4), sd0(d1), dram(bat), dram(vttctrl)
|
||||
mpp34 34 gpio, tdm(int5), sd0(d2), sata0(prsnt), dram(deccerr)
|
||||
mpp35 35 gpio, tdm(int6), sd0(d3), sata1(prsnt)
|
||||
mpp36 36 gpio, spi(mosi)
|
||||
mpp37 37 gpio, spi(miso)
|
||||
mpp38 38 gpio, spi(sck)
|
||||
mpp39 39 gpio, spi(cs0)
|
||||
mpp40 40 gpio, spi(cs1), uart2(cts), lcd(vga-hsync), vdd(cpu1-pd),
|
||||
pcie(clkreq0)
|
||||
mpp41 41 gpio, spi(cs2), uart2(rts), lcd(vga-vsync), sata1(prsnt),
|
||||
pcie(clkreq1)
|
||||
mpp42 42 gpio, uart2(rxd), uart0(cts), tdm(int7), tdm-1(timer),
|
||||
vdd(cpu0-pd)
|
||||
mpp43 43 gpio, uart2(txd), uart0(rts), spi(cs3), pcie(rstout),
|
||||
vdd(cpu2-3-pd){1}
|
||||
mpp44 44 gpio, uart2(cts), uart3(rxd), spi(cs4), pcie(clkreq2),
|
||||
mem(bat)
|
||||
mpp45 45 gpio, uart2(rts), uart3(txd), spi(cs5), sata1(prsnt)
|
||||
mpp46 46 gpio, uart3(rts), uart1(rts), spi(cs6), sata0(prsnt)
|
||||
mpp47 47 gpio, uart3(cts), uart1(cts), spi(cs7), pcie(clkreq3),
|
||||
ref(clkout)
|
||||
mpp48 48 gpio, tclk, dev(burst/last)
|
||||
mpp36 36 gpio, spi0(mosi)
|
||||
mpp37 37 gpio, spi0(miso)
|
||||
mpp38 38 gpio, spi0(sck)
|
||||
mpp39 39 gpio, spi0(cs0)
|
||||
mpp40 40 gpio, spi0(cs1), uart2(cts), lcd(vga-hsync), pcie(clkreq0),
|
||||
spi1(cs1)
|
||||
mpp41 41 gpio, spi0(cs2), uart2(rts), lcd(vga-vsync), sata1(prsnt),
|
||||
pcie(clkreq1), spi1(cs2)
|
||||
mpp42 42 gpio, uart2(rxd), uart0(cts), tdm(int7), tdm(timer)
|
||||
mpp43 43 gpio, uart2(txd), uart0(rts), spi0(cs3), pcie(rstout),
|
||||
spi1(cs3)
|
||||
mpp44 44 gpio, uart2(cts), uart3(rxd), spi0(cs4), pcie(clkreq2),
|
||||
dram(bat), spi1(cs4)
|
||||
mpp45 45 gpio, uart2(rts), uart3(txd), spi0(cs5), sata1(prsnt),
|
||||
spi1(cs5), dram(vttctrl)
|
||||
mpp46 46 gpio, uart3(rts), uart1(rts), spi0(cs6), sata0(prsnt),
|
||||
spi1(cs6)
|
||||
mpp47 47 gpio, uart3(cts), uart1(cts), spi0(cs7), pcie(clkreq3),
|
||||
ref(clkout), spi1(cs7)
|
||||
mpp48 48 gpio, dev(clkout), dev(burst/last), nand(rb)
|
||||
|
||||
* Marvell Armada XP (mv78260 and mv78460 only)
|
||||
|
||||
|
|
@ -84,9 +85,9 @@ mpp51 51 gpio, dev(ad16)
|
|||
mpp52 52 gpio, dev(ad17)
|
||||
mpp53 53 gpio, dev(ad18)
|
||||
mpp54 54 gpio, dev(ad19)
|
||||
mpp55 55 gpio, dev(ad20), vdd(cpu0-pd)
|
||||
mpp56 56 gpio, dev(ad21), vdd(cpu1-pd)
|
||||
mpp57 57 gpio, dev(ad22), vdd(cpu2-3-pd){1}
|
||||
mpp55 55 gpio, dev(ad20)
|
||||
mpp56 56 gpio, dev(ad21)
|
||||
mpp57 57 gpio, dev(ad22)
|
||||
mpp58 58 gpio, dev(ad23)
|
||||
mpp59 59 gpio, dev(ad24)
|
||||
mpp60 60 gpio, dev(ad25)
|
||||
|
|
@ -96,6 +97,3 @@ mpp63 63 gpio, dev(ad28)
|
|||
mpp64 64 gpio, dev(ad29)
|
||||
mpp65 65 gpio, dev(ad30)
|
||||
mpp66 66 gpio, dev(ad31)
|
||||
|
||||
Notes:
|
||||
* {1} vdd(cpu2-3-pd) only available on mv78460.
|
||||
|
|
|
|||
|
|
@ -0,0 +1,57 @@
|
|||
NXP LPC18xx/43xx SCU pin controller Device Tree Bindings
|
||||
--------------------------------------------------------
|
||||
|
||||
Required properties:
|
||||
- compatible : Should be "nxp,lpc1850-scu"
|
||||
- reg : Address and length of the register set for the device
|
||||
- clocks : Clock specifier (see clock bindings for details)
|
||||
|
||||
The lpc1850-scu driver uses the generic pin multiplexing and generic pin
|
||||
configuration documented in pinctrl-bindings.txt.
|
||||
|
||||
The following generic nodes are supported:
|
||||
- function
|
||||
- pins
|
||||
- bias-disable
|
||||
- bias-pull-up
|
||||
- bias-pull-down
|
||||
- drive-strength
|
||||
- input-enable
|
||||
- input-disable
|
||||
- input-schmitt-enable
|
||||
- input-schmitt-disable
|
||||
- slew-rate
|
||||
|
||||
Not all pins support all properties so either refer to the NXP 1850/4350
|
||||
user manual or the pin table in the pinctrl-lpc18xx driver for supported
|
||||
pin properties.
|
||||
|
||||
Example:
|
||||
pinctrl: pinctrl@40086000 {
|
||||
compatible = "nxp,lpc1850-scu";
|
||||
reg = <0x40086000 0x1000>;
|
||||
clocks = <&ccu1 CLK_CPU_SCU>;
|
||||
|
||||
i2c0_pins: i2c0-pins {
|
||||
i2c0_pins_cfg {
|
||||
pins = "i2c0_scl", "i2c0_sda";
|
||||
function = "i2c0";
|
||||
input-enable;
|
||||
};
|
||||
};
|
||||
|
||||
uart0_pins: uart0-pins {
|
||||
uart0_rx_cfg {
|
||||
pins = "pf_11";
|
||||
function = "uart0";
|
||||
bias-disable;
|
||||
input-enable;
|
||||
};
|
||||
|
||||
uart0_tx_cfg {
|
||||
pins = "pf_10";
|
||||
function = "uart0";
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
};
|
||||
109
Documentation/devicetree/bindings/pinctrl/pinctrl-atlas7.txt
Normal file
109
Documentation/devicetree/bindings/pinctrl/pinctrl-atlas7.txt
Normal file
|
|
@ -0,0 +1,109 @@
|
|||
CSR SiRFatlas7 pinmux controller
|
||||
|
||||
Required properties:
|
||||
- compatible : "sirf,atlas7-ioc"
|
||||
- reg : Address range of the pinctrl registers
|
||||
|
||||
For example, pinctrl might have properties like the following:
|
||||
pinctrl: ioc@18880000 {
|
||||
compatible = "sirf,atlas7-ioc";
|
||||
reg = <0x18880000 0x1000>;
|
||||
|
||||
a_ac97_pmx: ac97@0 {
|
||||
ac97 {
|
||||
groups = "audio_ac97_grp";
|
||||
function = "audio_ac97";
|
||||
};
|
||||
};
|
||||
|
||||
...
|
||||
|
||||
sd2_pmx: sd2@0 {
|
||||
sd2 {
|
||||
groups = "sd2_grp0";
|
||||
function = "sd2";
|
||||
};
|
||||
};
|
||||
|
||||
...
|
||||
|
||||
|
||||
sample0_cfg: sample0@0 {
|
||||
sample0 {
|
||||
pins = "ldd_0", "ldd_1";
|
||||
bias-pull-up;
|
||||
};
|
||||
};
|
||||
|
||||
sample1_cfg: sample1@0 {
|
||||
sample1 {
|
||||
pins = "ldd_2", "ldd_3";
|
||||
input-schmitt-enable;
|
||||
};
|
||||
};
|
||||
|
||||
sample2_cfg: sample2@0 {
|
||||
sample2 {
|
||||
groups = "uart4_nopause_grp";
|
||||
bias-pull-down;
|
||||
};
|
||||
};
|
||||
|
||||
sample3_cfg: sample3@0 {
|
||||
sample3 {
|
||||
pins = "ldd_4", "ldd_5";
|
||||
drive-strength = <2>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
Please refer to pinctrl-bindings.txt in this directory for details of the common
|
||||
pinctrl bindings used by client devices.
|
||||
|
||||
SiRFatlas7's pinmux nodes act as a container for an abitrary number of subnodes.
|
||||
Each of these subnodes represents some desired configuration for a group of pins.
|
||||
|
||||
Required subnode-properties:
|
||||
- groups : An array of strings. Each string contains the name of a group.
|
||||
- function: A string containing the name of the function to mux to the
|
||||
group.
|
||||
|
||||
Valid values for group and function names can be found from looking at the
|
||||
group and function arrays in driver files:
|
||||
drivers/pinctrl/pinctrl-sirf.c
|
||||
|
||||
For example, pinctrl might have subnodes like the following:
|
||||
sd0_pmx: sd0@0 {
|
||||
sd0 {
|
||||
groups = "sd0_grp";
|
||||
function = "sd0";
|
||||
};
|
||||
};
|
||||
|
||||
sd1_pmx0: sd1@0 {
|
||||
sd1 {
|
||||
groups = "sd1_grp0";
|
||||
function = "sd1_m0";
|
||||
};
|
||||
};
|
||||
|
||||
sd1_pmx1: sd1@1 {
|
||||
sd1 {
|
||||
groups = "sd1_grp1";
|
||||
function = "sd1_m1";
|
||||
};
|
||||
};
|
||||
|
||||
For a specific board, if it wants to use sd1,
|
||||
it can add the following to its board-specific .dts file.
|
||||
sd1: sd@0x12340000 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&sd1_pmx0>;
|
||||
}
|
||||
|
||||
or
|
||||
|
||||
sd1: sd@0x12340000 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&sd1_pmx1>;
|
||||
}
|
||||
|
|
@ -3,9 +3,11 @@
|
|||
The Mediatek's Pin controller is used to control SoC pins.
|
||||
|
||||
Required properties:
|
||||
- compatible: value should be either of the following.
|
||||
- compatible: value should be one of the following.
|
||||
(a) "mediatek,mt8135-pinctrl", compatible with mt8135 pinctrl.
|
||||
- mediatek,pctl-regmap: Should be a phandle of the syscfg node.
|
||||
(b) "mediatek,mt8173-pinctrl", compatible with mt8173 pinctrl.
|
||||
(c) "mediatek,mt6397-pinctrl", compatible with mt6397 pinctrl.
|
||||
(d) "mediatek,mt8127-pinctrl", compatible with mt8127 pinctrl.
|
||||
- pins-are-numbered: Specify the subnodes are using numbered pinmux to
|
||||
specify pins.
|
||||
- gpio-controller : Marks the device node as a gpio controller.
|
||||
|
|
@ -24,6 +26,9 @@ Required properties:
|
|||
Only the following flags are supported:
|
||||
0 - GPIO_ACTIVE_HIGH
|
||||
1 - GPIO_ACTIVE_LOW
|
||||
|
||||
Optional properties:
|
||||
- mediatek,pctl-regmap: Should be a phandle of the syscfg node.
|
||||
- reg: physicall address base for EINT registers
|
||||
- interrupt-controller: Marks the device node as an interrupt controller
|
||||
- #interrupt-cells: Should be two.
|
||||
|
|
|
|||
|
|
@ -0,0 +1,90 @@
|
|||
Qualcomm MSM8660 TLMM block
|
||||
|
||||
Required properties:
|
||||
- compatible: "qcom,msm8660-pinctrl"
|
||||
- reg: Should be the base address and length of the TLMM block.
|
||||
- interrupts: Should be the parent IRQ of the TLMM block.
|
||||
- interrupt-controller: Marks the device node as an interrupt controller.
|
||||
- #interrupt-cells: Should be two.
|
||||
- gpio-controller: Marks the device node as a GPIO controller.
|
||||
- #gpio-cells : Should be two.
|
||||
The first cell is the gpio pin number and the
|
||||
second cell is used for optional parameters.
|
||||
|
||||
Please refer to ../gpio/gpio.txt and ../interrupt-controller/interrupts.txt for
|
||||
a general description of GPIO and interrupt bindings.
|
||||
|
||||
Please refer to pinctrl-bindings.txt in this directory for details of the
|
||||
common pinctrl bindings used by client devices, including the meaning of the
|
||||
phrase "pin configuration node".
|
||||
|
||||
Qualcomm's pin configuration nodes act as a container for an arbitrary number of
|
||||
subnodes. Each of these subnodes represents some desired configuration for a
|
||||
pin, a group, or a list of pins or groups. This configuration can include the
|
||||
mux function to select on those pin(s)/group(s), and various pin configuration
|
||||
parameters, such as pull-up, drive strength, etc.
|
||||
|
||||
The name of each subnode is not important; all subnodes should be enumerated
|
||||
and processed purely based on their content.
|
||||
|
||||
Each subnode only affects those parameters that are explicitly listed. In
|
||||
other words, a subnode that lists a mux function but no pin configuration
|
||||
parameters implies no information about any pin configuration parameters.
|
||||
Similarly, a pin subnode that describes a pullup parameter implies no
|
||||
information about e.g. the mux function.
|
||||
|
||||
|
||||
The following generic properties as defined in pinctrl-bindings.txt are valid
|
||||
to specify in a pin configuration subnode:
|
||||
|
||||
pins, function, bias-disable, bias-pull-down, bias-pull,up, drive-strength,
|
||||
output-low, output-high.
|
||||
|
||||
Non-empty subnodes must specify the 'pins' property.
|
||||
|
||||
Valid values for pins are:
|
||||
gpio0-gpio172, sdc3_clk, sdc3_cmd, sdc3_data sdc4_clk, sdc4_cmd, sdc4_data
|
||||
|
||||
Valid values for function are:
|
||||
gpio, cam_mclk, dsub, ext_gps, gp_clk_0a, gp_clk_0b, gp_clk_1a, gp_clk_1b,
|
||||
gp_clk_2a, gp_clk_2b, gp_mn, gsbi1, gsbi1_spi_cs1_n, gsbi1_spi_cs2a_n,
|
||||
gsbi1_spi_cs2b_n, gsbi1_spi_cs3_n, gsbi2, gsbi2_spi_cs1_n, gsbi2_spi_cs2_n,
|
||||
gsbi2_spi_cs3_n, gsbi3, gsbi3_spi_cs1_n, gsbi3_spi_cs2_n, gsbi3_spi_cs3_n,
|
||||
gsbi4, gsbi5, gsbi6, gsbi7, gsbi8, gsbi9, gsbi10, gsbi11, gsbi12, hdmi, i2s,
|
||||
lcdc, mdp_vsync, mi2s, pcm, ps_hold, sdc1, sdc2, sdc5, tsif1, tsif2, usb_fs1,
|
||||
usb_fs1_oe_n, usb_fs2, usb_fs2_oe_n, vfe, vsens_alarm,
|
||||
|
||||
Example:
|
||||
|
||||
msmgpio: pinctrl@800000 {
|
||||
compatible = "qcom,msm8660-pinctrl";
|
||||
reg = <0x800000 0x4000>;
|
||||
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
interrupts = <0 16 0x4>;
|
||||
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&gsbi12_uart>;
|
||||
|
||||
gsbi12_uart: gsbi12-uart {
|
||||
mux {
|
||||
pins = "gpio117", "gpio118";
|
||||
function = "gsbi12";
|
||||
};
|
||||
|
||||
tx {
|
||||
pins = "gpio118";
|
||||
drive-strength = <8>;
|
||||
bias-disable;
|
||||
};
|
||||
|
||||
rx {
|
||||
pins = "gpio117";
|
||||
drive-strength = <2>;
|
||||
bias-pull-up;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
@ -16,7 +16,9 @@ Required Properties:
|
|||
- "renesas,pfc-r8a7778": for R8A7778 (R-Mobile M1) compatible pin-controller.
|
||||
- "renesas,pfc-r8a7779": for R8A7779 (R-Car H1) compatible pin-controller.
|
||||
- "renesas,pfc-r8a7790": for R8A7790 (R-Car H2) compatible pin-controller.
|
||||
- "renesas,pfc-r8a7791": for R8A7791 (R-Car M2) compatible pin-controller.
|
||||
- "renesas,pfc-r8a7791": for R8A7791 (R-Car M2-W) compatible pin-controller.
|
||||
- "renesas,pfc-r8a7793": for R8A7793 (R-Car M2-N) compatible pin-controller.
|
||||
- "renesas,pfc-r8a7794": for R8A7794 (R-Car E2) compatible pin-controller.
|
||||
- "renesas,pfc-sh73a0": for SH73A0 (SH-Mobile AG5) compatible pin-controller.
|
||||
|
||||
- reg: Base address and length of each memory resource used by the pin
|
||||
|
|
|
|||
|
|
@ -21,14 +21,15 @@ defined as gpio sub-nodes of the pinmux controller.
|
|||
Required properties for iomux controller:
|
||||
- compatible: one of "rockchip,rk2928-pinctrl", "rockchip,rk3066a-pinctrl"
|
||||
"rockchip,rk3066b-pinctrl", "rockchip,rk3188-pinctrl"
|
||||
"rockchip,rk3288-pinctrl"
|
||||
"rockchip,rk3288-pinctrl", "rockchip,rk3368-pinctrl"
|
||||
- rockchip,grf: phandle referencing a syscon providing the
|
||||
"general register files"
|
||||
|
||||
Optional properties for iomux controller:
|
||||
- rockchip,pmu: phandle referencing a syscon providing the pmu registers
|
||||
as some SoCs carry parts of the iomux controller registers there.
|
||||
Required for at least rk3188 and rk3288.
|
||||
Required for at least rk3188 and rk3288. On the rk3368 this should
|
||||
point to the PMUGRF syscon.
|
||||
|
||||
Deprecated properties for iomux controller:
|
||||
- reg: first element is the general register space of the iomux controller
|
||||
|
|
|
|||
|
|
@ -45,8 +45,9 @@ to specify in a pinconf subnode:
|
|||
|
||||
Valid values for groups are:
|
||||
ethernet0_0_grp, ethernet1_0_grp, mdio0_0_grp, mdio1_0_grp,
|
||||
qspi0_0_grp, qspi1_0_grp, qspi_fbclk, qspi_cs1_grp, spi0_0_grp,
|
||||
spi0_1_grp - spi0_2_grp, spi1_0_grp - spi1_3_grp, sdio0_0_grp - sdio0_2_grp,
|
||||
qspi0_0_grp, qspi1_0_grp, qspi_fbclk, qspi_cs1_grp, spi0_0_grp - spi0_2_grp,
|
||||
spi0_X_ssY (X=0..2, Y=0..2), spi1_0_grp - spi1_3_grp,
|
||||
spi1_X_ssY (X=0..3, Y=0..2), sdio0_0_grp - sdio0_2_grp,
|
||||
sdio1_0_grp - sdio1_3_grp, sdio0_emio_wp, sdio0_emio_cd, sdio1_emio_wp,
|
||||
sdio1_emio_cd, smc0_nor, smc0_nor_cs1_grp, smc0_nor_addr25_grp, smc0_nand,
|
||||
can0_0_grp - can0_10_grp, can1_0_grp - can1_11_grp, uart0_0_grp - uart0_10_grp,
|
||||
|
|
@ -59,7 +60,7 @@ to specify in a pinconf subnode:
|
|||
|
||||
Valid values for function are:
|
||||
ethernet0, ethernet1, mdio0, mdio1, qspi0, qspi1, qspi_fbclk, qspi_cs1,
|
||||
spi0, spi1, sdio0, sdio0_pc, sdio0_cd, sdio0_wp,
|
||||
spi0, spi0_ss, spi1, spi1_ss, sdio0, sdio0_pc, sdio0_cd, sdio0_wp,
|
||||
sdio1, sdio1_pc, sdio1_cd, sdio1_wp,
|
||||
smc0_nor, smc0_nor_cs1, smc0_nor_addr25, smc0_nand, can0, can1, uart0, uart1,
|
||||
i2c0, i2c1, ttc0, ttc1, swdt0, gpio0, usb0, usb1
|
||||
|
|
|
|||
|
|
@ -714,6 +714,7 @@ static struct pinmux_ops foo_pmxops = {
|
|||
.get_function_name = foo_get_fname,
|
||||
.get_function_groups = foo_get_groups,
|
||||
.set_mux = foo_set_mux,
|
||||
.strict = true,
|
||||
};
|
||||
|
||||
/* Pinmux operations are handled by some pin controller */
|
||||
|
|
@ -830,6 +831,11 @@ separate memory range only intended for GPIO driving, and the register
|
|||
range dealing with pin config and pin multiplexing get placed into a
|
||||
different memory range and a separate section of the data sheet.
|
||||
|
||||
A flag "strict" in struct pinctrl_desc is available to check and deny
|
||||
simultaneous access to the same pin from GPIO and pin multiplexing
|
||||
consumers on hardware of this type. The pinctrl driver should set this flag
|
||||
accordingly.
|
||||
|
||||
(B)
|
||||
|
||||
pin config
|
||||
|
|
@ -850,6 +856,11 @@ possible that the GPIO, pin config and pin multiplex registers are placed into
|
|||
the same memory range and the same section of the data sheet, although that
|
||||
need not be the case.
|
||||
|
||||
In some pin controllers, although the physical pins are designed in the same
|
||||
way as (B), the GPIO function still can't be enabled at the same time as the
|
||||
peripheral functions. So again the "strict" flag should be set, denying
|
||||
simultaneous activation by GPIO and other muxed in devices.
|
||||
|
||||
From a kernel point of view, however, these are different aspects of the
|
||||
hardware and shall be put into different subsystems:
|
||||
|
||||
|
|
|
|||
|
|
@ -540,7 +540,7 @@ static void bcm_kona_gpio_irq_unmap(struct irq_domain *d, unsigned int irq)
|
|||
irq_set_chip_data(irq, NULL);
|
||||
}
|
||||
|
||||
static struct irq_domain_ops bcm_kona_irq_ops = {
|
||||
static const struct irq_domain_ops bcm_kona_irq_ops = {
|
||||
.map = bcm_kona_gpio_irq_map,
|
||||
.unmap = bcm_kona_gpio_irq_unmap,
|
||||
.xlate = irq_domain_xlate_twocell,
|
||||
|
|
|
|||
|
|
@ -266,7 +266,7 @@ static int em_gio_irq_domain_map(struct irq_domain *h, unsigned int irq,
|
|||
return 0;
|
||||
}
|
||||
|
||||
static struct irq_domain_ops em_gio_irq_domain_ops = {
|
||||
static const struct irq_domain_ops em_gio_irq_domain_ops = {
|
||||
.map = em_gio_irq_domain_map,
|
||||
.xlate = irq_domain_xlate_twocell,
|
||||
};
|
||||
|
|
|
|||
|
|
@ -332,7 +332,7 @@ static void grgpio_irq_unmap(struct irq_domain *d, unsigned int irq)
|
|||
spin_unlock_irqrestore(&priv->bgc.lock, flags);
|
||||
}
|
||||
|
||||
static struct irq_domain_ops grgpio_irq_domain_ops = {
|
||||
static const struct irq_domain_ops grgpio_irq_domain_ops = {
|
||||
.map = grgpio_irq_map,
|
||||
.unmap = grgpio_irq_unmap,
|
||||
};
|
||||
|
|
|
|||
|
|
@ -329,7 +329,7 @@ static int mpc8xxx_gpio_irq_map(struct irq_domain *h, unsigned int irq,
|
|||
return 0;
|
||||
}
|
||||
|
||||
static struct irq_domain_ops mpc8xxx_gpio_irq_ops = {
|
||||
static const struct irq_domain_ops mpc8xxx_gpio_irq_ops = {
|
||||
.map = mpc8xxx_gpio_irq_map,
|
||||
.xlate = irq_domain_xlate_twocell,
|
||||
};
|
||||
|
|
|
|||
Some files were not shown because too many files have changed in this diff Show more
Loading…
Reference in a new issue