This is the bulk of pin control changes for the v4.3 development
cycle
Core changes:
- It is possible configure groups in debugfs.
- Consolidation of chained IRQ handler install/remove replacing
all call sites where irq_set_handler_data() and
irq_set_chained_handler() were done in succession with a
combined call to irq_set_chained_handler_and_data(). This
series was created by Thomas Gleixner after the problem was
observed by Russell King.
- Tglx also made another series of patches switching
__irq_set_handler_locked() for irq_set_handler_locked() which
is way cleaner.
- Tglx also wrote a good bunch of patches to make use of
irq_desc_get_xxx() accessors and avoid looking up irq_descs
from IRQ numbers. The goal is to get rid of the irq number
from the handlers in the IRQ flow which is nice.
Driver feature enhancements:
- Power management support for the SiRF SoC Atlas 7.
- Power down support for the Qualcomm driver.
- Intel Cherryview and Baytrail: switch drivers to use raw
spinlocks in IRQ handlers to play nice with the realtime
patch set.
- Rework and new modes handling for Qualcomm SPMI-MPP.
- Pinconf power source config for SH PFC.
New drivers and subdrivers:
- A new driver for Conexant Digicolor CX92755.
- A new driver for UniPhier PH1-LD4, PH1-Pro4, PH1-sLD8,
PH1-Pro5, ProXtream2 and PH1-LD6b SoC pin control support.
- Reverse-egineered the S/PDIF settings for the Allwinner
sun4i driver.
- Support for Qualcomm Technologies QDF2xxx ARM64 SoCs
- A new Freescale i.mx6ul subdriver.
Cleanup:
- Remove platform data support in a number of SH PFC
subdrivers.
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Merge tag 'pinctrl-v4.3-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl
Pull pin control updates from Linus Walleij:
"This is the bulk of pin control changes for the v4.3 development
cycle.
Like with GPIO it's a lot of stuff. If my subsystems are any sign of
the overall tempo of the kernel v4.3 will be a gigantic diff.
[ It looks like 4.3 is calmer than 4.2 in most other subsystems, but
we'll see - Linus ]
Core changes:
- It is possible configure groups in debugfs.
- Consolidation of chained IRQ handler install/remove replacing all
call sites where irq_set_handler_data() and
irq_set_chained_handler() were done in succession with a combined
call to irq_set_chained_handler_and_data(). This series was
created by Thomas Gleixner after the problem was observed by
Russell King.
- Tglx also made another series of patches switching
__irq_set_handler_locked() for irq_set_handler_locked() which is
way cleaner.
- Tglx also wrote a good bunch of patches to make use of
irq_desc_get_xxx() accessors and avoid looking up irq_descs from
IRQ numbers. The goal is to get rid of the irq number from the
handlers in the IRQ flow which is nice.
Driver feature enhancements:
- Power management support for the SiRF SoC Atlas 7.
- Power down support for the Qualcomm driver.
- Intel Cherryview and Baytrail: switch drivers to use raw spinlocks
in IRQ handlers to play nice with the realtime patch set.
- Rework and new modes handling for Qualcomm SPMI-MPP.
- Pinconf power source config for SH PFC.
New drivers and subdrivers:
- A new driver for Conexant Digicolor CX92755.
- A new driver for UniPhier PH1-LD4, PH1-Pro4, PH1-sLD8, PH1-Pro5,
ProXtream2 and PH1-LD6b SoC pin control support.
- Reverse-egineered the S/PDIF settings for the Allwinner sun4i
driver.
- Support for Qualcomm Technologies QDF2xxx ARM64 SoCs
- A new Freescale i.mx6ul subdriver.
Cleanup:
- Remove platform data support in a number of SH PFC subdrivers"
* tag 'pinctrl-v4.3-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (95 commits)
pinctrl: at91: fix null pointer dereference
pinctrl: mediatek: Implement wake handler and suspend resume
pinctrl: mediatek: Fix multiple registration issue.
pinctrl: sh-pfc: r8a7794: add USB pin groups
pinctrl: at91: Use generic irq_{request,release}_resources()
pinctrl: cherryview: Use raw_spinlock for locking
pinctrl: baytrail: Use raw_spinlock for locking
pinctrl: imx6ul: Remove .owner field
pinctrl: zynq: Fix typos in smc0_nand_grp and smc0_nor_grp
pinctrl: sh-pfc: Implement pinconf power-source param for voltage switching
clk: rockchip: add pclk_pd_pmu to the list of rk3288 critical clocks
pinctrl: sun4i: add spdif to pin description.
pinctrl: atlas7: clear ugly branch statements for pull and drivestrength
pinctrl: baytrail: Serialize all register access
pinctrl: baytrail: Drop FSF mailing address
pinctrl: rockchip: only enable gpio clock when it setting
pinctrl/mediatek: fix spelling mistake in dev_err error message
pinctrl: cherryview: Serialize all register access
pinctrl: UniPhier: PH1-Pro5: add I2C ch6 pin-mux setting
pinctrl: nomadik: reflect current input value
...
This commit is contained in:
Linus Torvalds
commit
88a99886c2
78 changed files with 12274 additions and 954 deletions
4
CREDITS
4
CREDITS
|
|
@ -20,6 +20,10 @@ D: One of assisting postmasters for vger.kernel.org's lists
|
|||
S: (ask for current address)
|
||||
S: Finland
|
||||
|
||||
N: Thomas Abraham
|
||||
E: thomas.ab@samsung.com
|
||||
D: Samsung pin controller driver
|
||||
|
||||
N: Dragos Acostachioaie
|
||||
E: dragos@iname.com
|
||||
W: http://www.arbornet.org/~dragos
|
||||
|
|
|
|||
|
|
@ -48,7 +48,7 @@ Optional subnode-properties:
|
|||
|
||||
Examples:
|
||||
|
||||
pinctrl@01c20800 {
|
||||
pio: pinctrl@01c20800 {
|
||||
compatible = "allwinner,sun5i-a13-pinctrl";
|
||||
reg = <0x01c20800 0x400>;
|
||||
#address-cells = <1>;
|
||||
|
|
@ -68,3 +68,38 @@ pinctrl@01c20800 {
|
|||
allwinner,pull = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
|
||||
GPIO and interrupt controller
|
||||
-----------------------------
|
||||
|
||||
This hardware also acts as a GPIO controller and an interrupt
|
||||
controller.
|
||||
|
||||
Consumers that would want to refer to one or the other (or both)
|
||||
should provide through the usual *-gpios and interrupts properties a
|
||||
cell with 3 arguments, first the number of the bank, then the pin
|
||||
inside that bank, and finally the flags for the GPIO/interrupts.
|
||||
|
||||
Example:
|
||||
|
||||
xio: gpio@38 {
|
||||
compatible = "nxp,pcf8574a";
|
||||
reg = <0x38>;
|
||||
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
|
||||
interrupt-parent = <&pio>;
|
||||
interrupts = <6 0 IRQ_TYPE_EDGE_FALLING>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
reg_usb1_vbus: usb1-vbus {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "usb1-vbus";
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
gpio = <&pio 7 6 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
|
|
|
|||
|
|
@ -0,0 +1,86 @@
|
|||
Conexant Digicolor CX92755 General Purpose Pin Mapping
|
||||
|
||||
This document describes the device tree binding of the pin mapping hardware
|
||||
modules in the Conexant Digicolor CX92755 SoCs. The CX92755 in one of the
|
||||
Digicolor series of SoCs.
|
||||
|
||||
=== Pin Controller Node ===
|
||||
|
||||
Required Properties:
|
||||
|
||||
- compatible: Must be "cnxt,cx92755-pinctrl"
|
||||
- reg: Base address of the General Purpose Pin Mapping register block and the
|
||||
size of the block.
|
||||
- gpio-controller: Marks the device node as a GPIO controller.
|
||||
- #gpio-cells: Must be <2>. The first cell is the pin number and the
|
||||
second cell is used to specify flags. See include/dt-bindings/gpio/gpio.h
|
||||
for possible values.
|
||||
|
||||
For example, the following is the bare minimum node:
|
||||
|
||||
pinctrl: pinctrl@f0000e20 {
|
||||
compatible = "cnxt,cx92755-pinctrl";
|
||||
reg = <0xf0000e20 0x100>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
};
|
||||
|
||||
As a pin controller device, in addition to the required properties, this node
|
||||
should also contain the pin configuration nodes that client devices reference,
|
||||
if any.
|
||||
|
||||
For a general description of GPIO bindings, please refer to ../gpio/gpio.txt.
|
||||
|
||||
=== Pin Configuration Node ===
|
||||
|
||||
Each pin configuration node is a sub-node of the pin controller node and is a
|
||||
container of an arbitrary number of subnodes, called pin group nodes in this
|
||||
document.
|
||||
|
||||
Please refer to the pinctrl-bindings.txt in this directory for details of the
|
||||
common pinctrl bindings used by client devices, including the definition of a
|
||||
"pin configuration node".
|
||||
|
||||
=== Pin Group Node ===
|
||||
|
||||
A pin group node specifies the desired pin mux for an arbitrary number of
|
||||
pins. The name of the pin group node is optional and not used.
|
||||
|
||||
A pin group node only affects the properties specified in the node, and has no
|
||||
effect on any properties that are omitted.
|
||||
|
||||
The pin group node accepts a subset of the generic pin config properties. For
|
||||
details generic pin config properties, please refer to pinctrl-bindings.txt
|
||||
and <include/linux/pinctrl/pinconfig-generic.h>.
|
||||
|
||||
Required Pin Group Node Properties:
|
||||
|
||||
- pins: Multiple strings. Specifies the name(s) of one or more pins to be
|
||||
configured by this node. The format of a pin name string is "GP_xy", where x
|
||||
is an uppercase character from 'A' to 'R', and y is a digit from 0 to 7.
|
||||
- function: String. Specifies the pin mux selection. Values must be one of:
|
||||
"gpio", "client_a", "client_b", "client_c"
|
||||
|
||||
Example:
|
||||
pinctrl: pinctrl@f0000e20 {
|
||||
compatible = "cnxt,cx92755-pinctrl";
|
||||
reg = <0xf0000e20 0x100>;
|
||||
|
||||
uart0_default: uart0_active {
|
||||
data_signals {
|
||||
pins = "GP_O0", "GP_O1";
|
||||
function = "client_b";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
uart0: uart@f0000740 {
|
||||
compatible = "cnxt,cx92755-usart";
|
||||
...
|
||||
pinctrl-0 = <&uart0_default>;
|
||||
pinctrl-names = "default";
|
||||
};
|
||||
|
||||
In the example above, a single pin group configuration node defines the
|
||||
"client select" for the Rx and Tx signals of uart0. The uart0 node references
|
||||
that pin configuration node using the &uart0_default phandle.
|
||||
|
|
@ -7,8 +7,13 @@ of PMIC's from Qualcomm.
|
|||
Usage: required
|
||||
Value type: <string>
|
||||
Definition: Should contain one of:
|
||||
"qcom,pm8018-mpp",
|
||||
"qcom,pm8038-mpp",
|
||||
"qcom,pm8821-mpp",
|
||||
"qcom,pm8841-mpp",
|
||||
"qcom,pm8916-mpp",
|
||||
"qcom,pm8917-mpp",
|
||||
"qcom,pm8921-mpp",
|
||||
"qcom,pm8941-mpp",
|
||||
"qcom,pma8084-mpp",
|
||||
|
||||
|
|
@ -77,12 +82,9 @@ to specify in a pin configuration subnode:
|
|||
Value type: <string>
|
||||
Definition: Specify the alternative function to be configured for the
|
||||
specified pins. Valid values are:
|
||||
"normal",
|
||||
"paired",
|
||||
"dtest1",
|
||||
"dtest2",
|
||||
"dtest3",
|
||||
"dtest4"
|
||||
"digital",
|
||||
"analog",
|
||||
"sink"
|
||||
|
||||
- bias-disable:
|
||||
Usage: optional
|
||||
|
|
@ -127,12 +129,18 @@ to specify in a pin configuration subnode:
|
|||
Definition: Selects the power source for the specified pins. Valid power
|
||||
sources are defined in <dt-bindings/pinctrl/qcom,pmic-mpp.h>
|
||||
|
||||
- qcom,analog-mode:
|
||||
- qcom,analog-level:
|
||||
Usage: optional
|
||||
Value type: <none>
|
||||
Definition: Selects Analog mode of operation: combined with input-enable
|
||||
and/or output-high, output-low MPP could operate as
|
||||
Bidirectional Logic, Analog Input, Analog Output.
|
||||
Value type: <u32>
|
||||
Definition: Selects the source for analog output. Valued values are
|
||||
defined in <dt-binding/pinctrl/qcom,pmic-mpp.h>
|
||||
PMIC_MPP_AOUT_LVL_*
|
||||
|
||||
- qcom,dtest:
|
||||
Usage: optional
|
||||
Value type: <u32>
|
||||
Definition: Selects which dtest rail to be routed in the various functions.
|
||||
Valid values are 1-4
|
||||
|
||||
- qcom,amux-route:
|
||||
Usage: optional
|
||||
|
|
@ -140,6 +148,10 @@ to specify in a pin configuration subnode:
|
|||
Definition: Selects the source for analog input. Valid values are
|
||||
defined in <dt-bindings/pinctrl/qcom,pmic-mpp.h>
|
||||
PMIC_MPP_AMUX_ROUTE_CH5, PMIC_MPP_AMUX_ROUTE_CH6...
|
||||
- qcom,paired:
|
||||
Usage: optional
|
||||
Value type: <none>
|
||||
Definition: Indicates that the pin should be operating in paired mode.
|
||||
|
||||
Example:
|
||||
|
||||
|
|
@ -156,7 +168,7 @@ Example:
|
|||
pm8841_default: default {
|
||||
gpio {
|
||||
pins = "mpp1", "mpp2", "mpp3", "mpp4";
|
||||
function = "normal";
|
||||
function = "digital";
|
||||
input-enable;
|
||||
power-source = <PM8841_MPP_S3>;
|
||||
};
|
||||
|
|
|
|||
|
|
@ -58,12 +58,12 @@ are parsed through phandles and processed purely based on their content.
|
|||
|
||||
Pin Configuration Node Properties:
|
||||
|
||||
- renesas,pins : An array of strings, each string containing the name of a pin.
|
||||
- renesas,groups : An array of strings, each string containing the name of a pin
|
||||
- pins : An array of strings, each string containing the name of a pin.
|
||||
- groups : An array of strings, each string containing the name of a pin
|
||||
group.
|
||||
|
||||
- renesas,function: A string containing the name of the function to mux to the
|
||||
pin group(s) specified by the renesas,groups property
|
||||
- function: A string containing the name of the function to mux to the pin
|
||||
group(s) specified by the groups property.
|
||||
|
||||
Valid values for pin, group and function names can be found in the group and
|
||||
function arrays of the PFC data file corresponding to the SoC
|
||||
|
|
@ -71,7 +71,9 @@ Pin Configuration Node Properties:
|
|||
|
||||
The pin configuration parameters use the generic pinconf bindings defined in
|
||||
pinctrl-bindings.txt in this directory. The supported parameters are
|
||||
bias-disable, bias-pull-up and bias-pull-down.
|
||||
bias-disable, bias-pull-up, bias-pull-down and power-source. For pins that
|
||||
have a configurable I/O voltage, the power-source value should be the
|
||||
nominal I/O voltage in millivolts.
|
||||
|
||||
|
||||
GPIO
|
||||
|
|
@ -141,19 +143,19 @@ Example 3: KZM-A9-GT (SH-Mobile AG5) default pin state hog and pin control maps
|
|||
|
||||
mmcif_pins: mmcif {
|
||||
mux {
|
||||
renesas,groups = "mmc0_data8_0", "mmc0_ctrl_0";
|
||||
renesas,function = "mmc0";
|
||||
groups = "mmc0_data8_0", "mmc0_ctrl_0";
|
||||
function = "mmc0";
|
||||
};
|
||||
cfg {
|
||||
renesas,groups = "mmc0_data8_0";
|
||||
renesas,pins = "PORT279";
|
||||
groups = "mmc0_data8_0";
|
||||
pins = "PORT279";
|
||||
bias-pull-up;
|
||||
};
|
||||
};
|
||||
|
||||
scifa4_pins: scifa4 {
|
||||
renesas,groups = "scifa4_data", "scifa4_ctrl";
|
||||
renesas,function = "scifa4";
|
||||
groups = "scifa4_data", "scifa4_ctrl";
|
||||
function = "scifa4";
|
||||
};
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -3,7 +3,9 @@ ST Ericsson Nomadik pinmux controller
|
|||
Required properties:
|
||||
- compatible: "stericsson,db8500-pinctrl", "stericsson,db8540-pinctrl",
|
||||
"stericsson,stn8815-pinctrl"
|
||||
- reg: Should contain the register physical address and length of the PRCMU.
|
||||
- nomadik-gpio-chips: array of phandles to the corresponding GPIO chips
|
||||
(these have the register ranges used by the pin controller).
|
||||
- prcm: phandle to the PRCMU managing the back end of this pin controller
|
||||
|
||||
Please refer to pinctrl-bindings.txt in this directory for details of the
|
||||
common pinctrl bindings used by client devices, including the meaning of the
|
||||
|
|
@ -74,7 +76,8 @@ Example board file extract:
|
|||
|
||||
pinctrl@80157000 {
|
||||
compatible = "stericsson,db8500-pinctrl";
|
||||
reg = <0x80157000 0x2000>;
|
||||
nomadik-gpio-chips = <&gpio0>, <&gpio1>, <&gpio2>, <&gpio3>;
|
||||
prcm = <&prcmu>;
|
||||
|
||||
pinctrl-names = "default";
|
||||
|
||||
|
|
|
|||
|
|
@ -8045,7 +8045,6 @@ F: drivers/pinctrl/sh-pfc/
|
|||
|
||||
PIN CONTROLLER - SAMSUNG
|
||||
M: Tomasz Figa <tomasz.figa@gmail.com>
|
||||
M: Thomas Abraham <thomas.abraham@linaro.org>
|
||||
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
|
||||
L: linux-samsung-soc@vger.kernel.org (moderated for non-subscribers)
|
||||
S: Maintained
|
||||
|
|
|
|||
|
|
@ -294,7 +294,7 @@
|
|||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
gpio-bank = <0>;
|
||||
|
||||
gpio-ranges = <&pinctrl 0 0 32>;
|
||||
clocks = <&prcc_pclk 1 9>;
|
||||
};
|
||||
|
||||
|
|
@ -309,7 +309,7 @@
|
|||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
gpio-bank = <1>;
|
||||
|
||||
gpio-ranges = <&pinctrl 0 32 5>;
|
||||
clocks = <&prcc_pclk 1 9>;
|
||||
};
|
||||
|
||||
|
|
@ -324,7 +324,7 @@
|
|||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
gpio-bank = <2>;
|
||||
|
||||
gpio-ranges = <&pinctrl 0 64 32>;
|
||||
clocks = <&prcc_pclk 3 8>;
|
||||
};
|
||||
|
||||
|
|
@ -339,7 +339,7 @@
|
|||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
gpio-bank = <3>;
|
||||
|
||||
gpio-ranges = <&pinctrl 0 96 2>;
|
||||
clocks = <&prcc_pclk 3 8>;
|
||||
};
|
||||
|
||||
|
|
@ -354,7 +354,7 @@
|
|||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
gpio-bank = <4>;
|
||||
|
||||
gpio-ranges = <&pinctrl 0 128 32>;
|
||||
clocks = <&prcc_pclk 3 8>;
|
||||
};
|
||||
|
||||
|
|
@ -369,7 +369,7 @@
|
|||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
gpio-bank = <5>;
|
||||
|
||||
gpio-ranges = <&pinctrl 0 160 12>;
|
||||
clocks = <&prcc_pclk 3 8>;
|
||||
};
|
||||
|
||||
|
|
@ -384,7 +384,7 @@
|
|||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
gpio-bank = <6>;
|
||||
|
||||
gpio-ranges = <&pinctrl 0 192 32>;
|
||||
clocks = <&prcc_pclk 2 11>;
|
||||
};
|
||||
|
||||
|
|
@ -399,7 +399,7 @@
|
|||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
gpio-bank = <7>;
|
||||
|
||||
gpio-ranges = <&pinctrl 0 224 7>;
|
||||
clocks = <&prcc_pclk 2 11>;
|
||||
};
|
||||
|
||||
|
|
@ -414,12 +414,15 @@
|
|||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
gpio-bank = <8>;
|
||||
|
||||
gpio-ranges = <&pinctrl 0 256 12>;
|
||||
clocks = <&prcc_pclk 5 1>;
|
||||
};
|
||||
|
||||
pinctrl {
|
||||
pinctrl: pinctrl {
|
||||
compatible = "stericsson,db8500-pinctrl";
|
||||
nomadik-gpio-chips = <&gpio0>, <&gpio1>, <&gpio2>, <&gpio3>,
|
||||
<&gpio4>, <&gpio5>, <&gpio6>, <&gpio7>,
|
||||
<&gpio8>;
|
||||
prcm = <&prcmu>;
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -59,6 +59,7 @@
|
|||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
gpio-bank = <0>;
|
||||
gpio-ranges = <&pinctrl 0 0 32>;
|
||||
clocks = <&pclk>;
|
||||
};
|
||||
|
||||
|
|
@ -72,6 +73,7 @@
|
|||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
gpio-bank = <1>;
|
||||
gpio-ranges = <&pinctrl 0 32 32>;
|
||||
clocks = <&pclk>;
|
||||
};
|
||||
|
||||
|
|
@ -85,12 +87,14 @@
|
|||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
gpio-bank = <2>;
|
||||
gpio-ranges = <&pinctrl 0 64 32>;
|
||||
clocks = <&pclk>;
|
||||
};
|
||||
|
||||
gpio3: gpio@101e7000 {
|
||||
compatible = "st,nomadik-gpio";
|
||||
reg = <0x101e7000 0x80>;
|
||||
ngpio = <28>;
|
||||
interrupt-parent = <&vica>;
|
||||
interrupts = <9>;
|
||||
interrupt-controller;
|
||||
|
|
@ -98,11 +102,13 @@
|
|||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
gpio-bank = <3>;
|
||||
gpio-ranges = <&pinctrl 0 96 28>;
|
||||
clocks = <&pclk>;
|
||||
};
|
||||
|
||||
pinctrl {
|
||||
pinctrl: pinctrl {
|
||||
compatible = "stericsson,stn8815-pinctrl";
|
||||
nomadik-gpio-chips = <&gpio0>, <&gpio1>, <&gpio2>, <&gpio3>;
|
||||
/* Pin configurations */
|
||||
uart1 {
|
||||
uart1_default_mux: uart1_mux {
|
||||
|
|
|
|||
|
|
@ -11,7 +11,7 @@ obj-y += bus/
|
|||
obj-$(CONFIG_GENERIC_PHY) += phy/
|
||||
|
||||
# GPIO must come after pinctrl as gpios may need to mux pins etc
|
||||
obj-y += pinctrl/
|
||||
obj-$(CONFIG_PINCTRL) += pinctrl/
|
||||
obj-y += gpio/
|
||||
obj-y += pwm/
|
||||
obj-$(CONFIG_PCI) += pci/
|
||||
|
|
|
|||
|
|
@ -780,6 +780,7 @@ static const char *const rk3288_critical_clocks[] __initconst = {
|
|||
"aclk_cpu",
|
||||
"aclk_peri",
|
||||
"hclk_peri",
|
||||
"pclk_pd_pmu",
|
||||
};
|
||||
|
||||
#ifdef CONFIG_PM_SLEEP
|
||||
|
|
|
|||
|
|
@ -82,6 +82,12 @@ config PINCTRL_AMD
|
|||
Requires ACPI/FDT device enumeration code to set up a platform
|
||||
device.
|
||||
|
||||
config PINCTRL_DIGICOLOR
|
||||
bool
|
||||
depends on OF && (ARCH_DIGICOLOR || COMPILE_TEST)
|
||||
select PINMUX
|
||||
select GENERIC_PINCONF
|
||||
|
||||
config PINCTRL_LANTIQ
|
||||
bool
|
||||
depends on LANTIQ
|
||||
|
|
@ -240,6 +246,7 @@ source "drivers/pinctrl/samsung/Kconfig"
|
|||
source "drivers/pinctrl/sh-pfc/Kconfig"
|
||||
source "drivers/pinctrl/spear/Kconfig"
|
||||
source "drivers/pinctrl/sunxi/Kconfig"
|
||||
source "drivers/pinctrl/uniphier/Kconfig"
|
||||
source "drivers/pinctrl/vt8500/Kconfig"
|
||||
source "drivers/pinctrl/mediatek/Kconfig"
|
||||
|
||||
|
|
|
|||
|
|
@ -2,12 +2,10 @@
|
|||
|
||||
subdir-ccflags-$(CONFIG_DEBUG_PINCTRL) += -DDEBUG
|
||||
|
||||
obj-$(CONFIG_PINCTRL) += core.o pinctrl-utils.o
|
||||
obj-y += core.o pinctrl-utils.o
|
||||
obj-$(CONFIG_PINMUX) += pinmux.o
|
||||
obj-$(CONFIG_PINCONF) += pinconf.o
|
||||
ifeq ($(CONFIG_OF),y)
|
||||
obj-$(CONFIG_PINCTRL) += devicetree.o
|
||||
endif
|
||||
obj-$(CONFIG_OF) += devicetree.o
|
||||
obj-$(CONFIG_GENERIC_PINCONF) += pinconf-generic.o
|
||||
obj-$(CONFIG_PINCTRL_ADI2) += pinctrl-adi2.o
|
||||
obj-$(CONFIG_PINCTRL_AS3722) += pinctrl-as3722.o
|
||||
|
|
@ -15,6 +13,7 @@ obj-$(CONFIG_PINCTRL_BF54x) += pinctrl-adi2-bf54x.o
|
|||
obj-$(CONFIG_PINCTRL_BF60x) += pinctrl-adi2-bf60x.o
|
||||
obj-$(CONFIG_PINCTRL_AT91) += pinctrl-at91.o
|
||||
obj-$(CONFIG_PINCTRL_AMD) += pinctrl-amd.o
|
||||
obj-$(CONFIG_PINCTRL_DIGICOLOR) += pinctrl-digicolor.o
|
||||
obj-$(CONFIG_PINCTRL_FALCON) += pinctrl-falcon.o
|
||||
obj-$(CONFIG_PINCTRL_MESON) += meson/
|
||||
obj-$(CONFIG_PINCTRL_PALMAS) += pinctrl-palmas.o
|
||||
|
|
@ -51,5 +50,6 @@ obj-$(CONFIG_PINCTRL_SAMSUNG) += samsung/
|
|||
obj-$(CONFIG_PINCTRL_SH_PFC) += sh-pfc/
|
||||
obj-$(CONFIG_PLAT_SPEAR) += spear/
|
||||
obj-$(CONFIG_ARCH_SUNXI) += sunxi/
|
||||
obj-$(CONFIG_ARCH_UNIPHIER) += uniphier/
|
||||
obj-$(CONFIG_ARCH_VT8500) += vt8500/
|
||||
obj-$(CONFIG_ARCH_MEDIATEK) += mediatek/
|
||||
|
|
|
|||
|
|
@ -586,9 +586,9 @@ static int bcm2835_gpio_irq_set_type(struct irq_data *data, unsigned int type)
|
|||
ret = __bcm2835_gpio_irq_set_type_disabled(pc, gpio, type);
|
||||
|
||||
if (type & IRQ_TYPE_EDGE_BOTH)
|
||||
__irq_set_handler_locked(data->irq, handle_edge_irq);
|
||||
irq_set_handler_locked(data, handle_edge_irq);
|
||||
else
|
||||
__irq_set_handler_locked(data->irq, handle_level_irq);
|
||||
irq_set_handler_locked(data, handle_level_irq);
|
||||
|
||||
spin_unlock_irqrestore(&pc->irq_lock[bank], flags);
|
||||
|
||||
|
|
@ -989,7 +989,6 @@ static int bcm2835_pinctrl_probe(struct platform_device *pdev)
|
|||
irq_set_chip_and_handler(irq, &bcm2835_gpio_irq_chip,
|
||||
handle_level_irq);
|
||||
irq_set_chip_data(irq, pc);
|
||||
set_irq_flags(irq, IRQF_VALID);
|
||||
}
|
||||
|
||||
for (i = 0; i < BCM2835_NUM_BANKS; i++) {
|
||||
|
|
|
|||
|
|
@ -231,8 +231,7 @@ static int pinctrl_register_one_pin(struct pinctrl_dev *pctldev,
|
|||
|
||||
pindesc = pin_desc_get(pctldev, number);
|
||||
if (pindesc != NULL) {
|
||||
pr_err("pin %d already registered on %s\n", number,
|
||||
pctldev->desc->name);
|
||||
dev_err(pctldev->dev, "pin %d already registered\n", number);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -97,13 +97,7 @@ static int dt_remember_or_free_map(struct pinctrl *p, const char *statename,
|
|||
|
||||
struct pinctrl_dev *of_pinctrl_get(struct device_node *np)
|
||||
{
|
||||
struct pinctrl_dev *pctldev;
|
||||
|
||||
pctldev = get_pinctrl_dev_from_of_node(np);
|
||||
if (!pctldev)
|
||||
return NULL;
|
||||
|
||||
return pctldev;
|
||||
return get_pinctrl_dev_from_of_node(np);
|
||||
}
|
||||
|
||||
static int dt_to_map_one_config(struct pinctrl *p, const char *statename,
|
||||
|
|
|
|||
|
|
@ -87,6 +87,13 @@ config PINCTRL_IMX6SX
|
|||
help
|
||||
Say Y here to enable the imx6sx pinctrl driver
|
||||
|
||||
config PINCTRL_IMX6UL
|
||||
bool "IMX6UL pinctrl driver"
|
||||
depends on SOC_IMX6UL
|
||||
select PINCTRL_IMX
|
||||
help
|
||||
Say Y here to enable the imx6ul pinctrl driver
|
||||
|
||||
config PINCTRL_IMX7D
|
||||
bool "IMX7D pinctrl driver"
|
||||
depends on SOC_IMX7D
|
||||
|
|
|
|||
|
|
@ -12,6 +12,7 @@ obj-$(CONFIG_PINCTRL_IMX6Q) += pinctrl-imx6q.o
|
|||
obj-$(CONFIG_PINCTRL_IMX6Q) += pinctrl-imx6dl.o
|
||||
obj-$(CONFIG_PINCTRL_IMX6SL) += pinctrl-imx6sl.o
|
||||
obj-$(CONFIG_PINCTRL_IMX6SX) += pinctrl-imx6sx.o
|
||||
obj-$(CONFIG_PINCTRL_IMX6UL) += pinctrl-imx6ul.o
|
||||
obj-$(CONFIG_PINCTRL_IMX7D) += pinctrl-imx7d.o
|
||||
obj-$(CONFIG_PINCTRL_VF610) += pinctrl-vf610.o
|
||||
obj-$(CONFIG_PINCTRL_MXS) += pinctrl-mxs.o
|
||||
|
|
|
|||
322
drivers/pinctrl/freescale/pinctrl-imx6ul.c
Normal file
322
drivers/pinctrl/freescale/pinctrl-imx6ul.c
Normal file
|
|
@ -0,0 +1,322 @@
|
|||
/*
|
||||
* Copyright (C) 2015 Freescale Semiconductor, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
#include <linux/err.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/io.h>
|
||||
#include <linux/module.h>
|
||||
#include <linux/of.h>
|
||||
#include <linux/of_device.h>
|
||||
#include <linux/pinctrl/pinctrl.h>
|
||||
|
||||
#include "pinctrl-imx.h"
|
||||
|
||||
enum imx6ul_pads {
|
||||
MX6UL_PAD_RESERVE0 = 0,
|
||||
MX6UL_PAD_RESERVE1 = 1,
|
||||
MX6UL_PAD_RESERVE2 = 2,
|
||||
MX6UL_PAD_RESERVE3 = 3,
|
||||
MX6UL_PAD_RESERVE4 = 4,
|
||||
MX6UL_PAD_RESERVE5 = 5,
|
||||
MX6UL_PAD_RESERVE6 = 6,
|
||||
MX6UL_PAD_RESERVE7 = 7,
|
||||
MX6UL_PAD_RESERVE8 = 8,
|
||||
MX6UL_PAD_RESERVE9 = 9,
|
||||
MX6UL_PAD_RESERVE10 = 10,
|
||||
MX6UL_PAD_SNVS_TAMPER4 = 11,
|
||||
MX6UL_PAD_RESERVE12 = 12,
|
||||
MX6UL_PAD_RESERVE13 = 13,
|
||||
MX6UL_PAD_RESERVE14 = 14,
|
||||
MX6UL_PAD_RESERVE15 = 15,
|
||||
MX6UL_PAD_RESERVE16 = 16,
|
||||
MX6UL_PAD_JTAG_MOD = 17,
|
||||
MX6UL_PAD_JTAG_TMS = 18,
|
||||
MX6UL_PAD_JTAG_TDO = 19,
|
||||
MX6UL_PAD_JTAG_TDI = 20,
|
||||
MX6UL_PAD_JTAG_TCK = 21,
|
||||
MX6UL_PAD_JTAG_TRST_B = 22,
|
||||
MX6UL_PAD_GPIO1_IO00 = 23,
|
||||
MX6UL_PAD_GPIO1_IO01 = 24,
|
||||
MX6UL_PAD_GPIO1_IO02 = 25,
|
||||
MX6UL_PAD_GPIO1_IO03 = 26,
|
||||
MX6UL_PAD_GPIO1_IO04 = 27,
|
||||
MX6UL_PAD_GPIO1_IO05 = 28,
|
||||
MX6UL_PAD_GPIO1_IO06 = 29,
|
||||
MX6UL_PAD_GPIO1_IO07 = 30,
|
||||
MX6UL_PAD_GPIO1_IO08 = 31,
|
||||
MX6UL_PAD_GPIO1_IO09 = 32,
|
||||
MX6UL_PAD_UART1_TX_DATA = 33,
|
||||
MX6UL_PAD_UART1_RX_DATA = 34,
|
||||
MX6UL_PAD_UART1_CTS_B = 35,
|
||||
MX6UL_PAD_UART1_RTS_B = 36,
|
||||
MX6UL_PAD_UART2_TX_DATA = 37,
|
||||
MX6UL_PAD_UART2_RX_DATA = 38,
|
||||
MX6UL_PAD_UART2_CTS_B = 39,
|
||||
MX6UL_PAD_UART2_RTS_B = 40,
|
||||
MX6UL_PAD_UART3_TX_DATA = 41,
|
||||
MX6UL_PAD_UART3_RX_DATA = 42,
|
||||
MX6UL_PAD_UART3_CTS_B = 43,
|
||||
MX6UL_PAD_UART3_RTS_B = 44,
|
||||
MX6UL_PAD_UART4_TX_DATA = 45,
|
||||
MX6UL_PAD_UART4_RX_DATA = 46,
|
||||
MX6UL_PAD_UART5_TX_DATA = 47,
|
||||
MX6UL_PAD_UART5_RX_DATA = 48,
|
||||
MX6UL_PAD_ENET1_RX_DATA0 = 49,
|
||||
MX6UL_PAD_ENET1_RX_DATA1 = 50,
|
||||
MX6UL_PAD_ENET1_RX_EN = 51,
|
||||
MX6UL_PAD_ENET1_TX_DATA0 = 52,
|
||||
MX6UL_PAD_ENET1_TX_DATA1 = 53,
|
||||
MX6UL_PAD_ENET1_TX_EN = 54,
|
||||
MX6UL_PAD_ENET1_TX_CLK = 55,
|
||||
MX6UL_PAD_ENET1_RX_ER = 56,
|
||||
MX6UL_PAD_ENET2_RX_DATA0 = 57,
|
||||
MX6UL_PAD_ENET2_RX_DATA1 = 58,
|
||||
MX6UL_PAD_ENET2_RX_EN = 59,
|
||||
MX6UL_PAD_ENET2_TX_DATA0 = 60,
|
||||
MX6UL_PAD_ENET2_TX_DATA1 = 61,
|
||||
MX6UL_PAD_ENET2_TX_EN = 62,
|
||||
MX6UL_PAD_ENET2_TX_CLK = 63,
|
||||
MX6UL_PAD_ENET2_RX_ER = 64,
|
||||
MX6UL_PAD_LCD_CLK = 65,
|
||||
MX6UL_PAD_LCD_ENABLE = 66,
|
||||
MX6UL_PAD_LCD_HSYNC = 67,
|
||||
MX6UL_PAD_LCD_VSYNC = 68,
|
||||
MX6UL_PAD_LCD_RESET = 69,
|
||||
MX6UL_PAD_LCD_DATA00 = 70,
|
||||
MX6UL_PAD_LCD_DATA01 = 71,
|
||||
MX6UL_PAD_LCD_DATA02 = 72,
|
||||
MX6UL_PAD_LCD_DATA03 = 73,
|
||||
MX6UL_PAD_LCD_DATA04 = 74,
|
||||
MX6UL_PAD_LCD_DATA05 = 75,
|
||||
MX6UL_PAD_LCD_DATA06 = 76,
|
||||
MX6UL_PAD_LCD_DATA07 = 77,
|
||||
MX6UL_PAD_LCD_DATA08 = 78,
|
||||
MX6UL_PAD_LCD_DATA09 = 79,
|
||||
MX6UL_PAD_LCD_DATA10 = 80,
|
||||
MX6UL_PAD_LCD_DATA11 = 81,
|
||||
MX6UL_PAD_LCD_DATA12 = 82,
|
||||
MX6UL_PAD_LCD_DATA13 = 83,
|
||||
MX6UL_PAD_LCD_DATA14 = 84,
|
||||
MX6UL_PAD_LCD_DATA15 = 85,
|
||||
MX6UL_PAD_LCD_DATA16 = 86,
|
||||
MX6UL_PAD_LCD_DATA17 = 87,
|
||||
MX6UL_PAD_LCD_DATA18 = 88,
|
||||
MX6UL_PAD_LCD_DATA19 = 89,
|
||||
MX6UL_PAD_LCD_DATA20 = 90,
|
||||
MX6UL_PAD_LCD_DATA21 = 91,
|
||||
MX6UL_PAD_LCD_DATA22 = 92,
|
||||
MX6UL_PAD_LCD_DATA23 = 93,
|
||||
MX6UL_PAD_NAND_RE_B = 94,
|
||||
MX6UL_PAD_NAND_WE_B = 95,
|
||||
MX6UL_PAD_NAND_DATA00 = 96,
|
||||
MX6UL_PAD_NAND_DATA01 = 97,
|
||||
MX6UL_PAD_NAND_DATA02 = 98,
|
||||
MX6UL_PAD_NAND_DATA03 = 99,
|
||||
MX6UL_PAD_NAND_DATA04 = 100,
|
||||
MX6UL_PAD_NAND_DATA05 = 101,
|
||||
MX6UL_PAD_NAND_DATA06 = 102,
|
||||
MX6UL_PAD_NAND_DATA07 = 103,
|
||||
MX6UL_PAD_NAND_ALE = 104,
|
||||
MX6UL_PAD_NAND_WP_B = 105,
|
||||
MX6UL_PAD_NAND_READY_B = 106,
|
||||
MX6UL_PAD_NAND_CE0_B = 107,
|
||||
MX6UL_PAD_NAND_CE1_B = 108,
|
||||
MX6UL_PAD_NAND_CLE = 109,
|
||||
MX6UL_PAD_NAND_DQS = 110,
|
||||
MX6UL_PAD_SD1_CMD = 111,
|
||||
MX6UL_PAD_SD1_CLK = 112,
|
||||
MX6UL_PAD_SD1_DATA0 = 113,
|
||||
MX6UL_PAD_SD1_DATA1 = 114,
|
||||
MX6UL_PAD_SD1_DATA2 = 115,
|
||||
MX6UL_PAD_SD1_DATA3 = 116,
|
||||
MX6UL_PAD_CSI_MCLK = 117,
|
||||
MX6UL_PAD_CSI_PIXCLK = 118,
|
||||
MX6UL_PAD_CSI_VSYNC = 119,
|
||||
MX6UL_PAD_CSI_HSYNC = 120,
|
||||
MX6UL_PAD_CSI_DATA00 = 121,
|
||||
MX6UL_PAD_CSI_DATA01 = 122,
|
||||
MX6UL_PAD_CSI_DATA02 = 123,
|
||||
MX6UL_PAD_CSI_DATA03 = 124,
|
||||
MX6UL_PAD_CSI_DATA04 = 125,
|
||||
MX6UL_PAD_CSI_DATA05 = 126,
|
||||
MX6UL_PAD_CSI_DATA06 = 127,
|
||||
MX6UL_PAD_CSI_DATA07 = 128,
|
||||
};
|
||||
|
||||
/* Pad names for the pinmux subsystem */
|
||||
static const struct pinctrl_pin_desc imx6ul_pinctrl_pads[] = {
|
||||
IMX_PINCTRL_PIN(MX6UL_PAD_RESERVE0),
|
||||
IMX_PINCTRL_PIN(MX6UL_PAD_RESERVE1),
|
||||
IMX_PINCTRL_PIN(MX6UL_PAD_RESERVE2),
|
||||
IMX_PINCTRL_PIN(MX6UL_PAD_RESERVE3),
|
||||
IMX_PINCTRL_PIN(MX6UL_PAD_RESERVE4),
|
||||
IMX_PINCTRL_PIN(MX6UL_PAD_RESERVE5),
|
||||
IMX_PINCTRL_PIN(MX6UL_PAD_RESERVE6),
|
||||
IMX_PINCTRL_PIN(MX6UL_PAD_RESERVE7),
|
||||
IMX_PINCTRL_PIN(MX6UL_PAD_RESERVE8),
|
||||
IMX_PINCTRL_PIN(MX6UL_PAD_RESERVE9),
|
||||
IMX_PINCTRL_PIN(MX6UL_PAD_RESERVE10),
|
||||
IMX_PINCTRL_PIN(MX6UL_PAD_SNVS_TAMPER4),
|
||||
IMX_PINCTRL_PIN(MX6UL_PAD_RESERVE12),
|
||||
IMX_PINCTRL_PIN(MX6UL_PAD_RESERVE13),
|
||||
IMX_PINCTRL_PIN(MX6UL_PAD_RESERVE14),
|
||||
IMX_PINCTRL_PIN(MX6UL_PAD_RESERVE15),
|
||||
IMX_PINCTRL_PIN(MX6UL_PAD_RESERVE16),
|
||||
IMX_PINCTRL_PIN(MX6UL_PAD_JTAG_MOD),
|
||||
IMX_PINCTRL_PIN(MX6UL_PAD_JTAG_TMS),
|
||||
IMX_PINCTRL_PIN(MX6UL_PAD_JTAG_TDO),
|
||||
IMX_PINCTRL_PIN(MX6UL_PAD_JTAG_TDI),
|
||||
IMX_PINCTRL_PIN(MX6UL_PAD_JTAG_TCK),
|
||||
IMX_PINCTRL_PIN(MX6UL_PAD_JTAG_TRST_B),
|
||||
IMX_PINCTRL_PIN(MX6UL_PAD_GPIO1_IO00),
|
||||
IMX_PINCTRL_PIN(MX6UL_PAD_GPIO1_IO01),
|
||||
IMX_PINCTRL_PIN(MX6UL_PAD_GPIO1_IO02),
|
||||
IMX_PINCTRL_PIN(MX6UL_PAD_GPIO1_IO03),
|
||||
IMX_PINCTRL_PIN(MX6UL_PAD_GPIO1_IO04),
|
||||
IMX_PINCTRL_PIN(MX6UL_PAD_GPIO1_IO05),
|
||||
IMX_PINCTRL_PIN(MX6UL_PAD_GPIO1_IO06),
|
||||
IMX_PINCTRL_PIN(MX6UL_PAD_GPIO1_IO07),
|
||||
IMX_PINCTRL_PIN(MX6UL_PAD_GPIO1_IO08),
|
||||
IMX_PINCTRL_PIN(MX6UL_PAD_GPIO1_IO09),
|
||||
IMX_PINCTRL_PIN(MX6UL_PAD_UART1_TX_DATA),
|
||||
IMX_PINCTRL_PIN(MX6UL_PAD_UART1_RX_DATA),
|
||||
IMX_PINCTRL_PIN(MX6UL_PAD_UART1_CTS_B),
|
||||
IMX_PINCTRL_PIN(MX6UL_PAD_UART1_RTS_B),
|
||||
IMX_PINCTRL_PIN(MX6UL_PAD_UART2_TX_DATA),
|
||||
IMX_PINCTRL_PIN(MX6UL_PAD_UART2_RX_DATA),
|
||||
IMX_PINCTRL_PIN(MX6UL_PAD_UART2_CTS_B),
|
||||
IMX_PINCTRL_PIN(MX6UL_PAD_UART2_RTS_B),
|
||||
IMX_PINCTRL_PIN(MX6UL_PAD_UART3_TX_DATA),
|
||||
IMX_PINCTRL_PIN(MX6UL_PAD_UART3_RX_DATA),
|
||||
IMX_PINCTRL_PIN(MX6UL_PAD_UART3_CTS_B),
|
||||
IMX_PINCTRL_PIN(MX6UL_PAD_UART3_RTS_B),
|
||||
IMX_PINCTRL_PIN(MX6UL_PAD_UART4_TX_DATA),
|
||||
IMX_PINCTRL_PIN(MX6UL_PAD_UART4_RX_DATA),
|
||||
IMX_PINCTRL_PIN(MX6UL_PAD_UART5_TX_DATA),
|
||||
IMX_PINCTRL_PIN(MX6UL_PAD_UART5_RX_DATA),
|
||||
IMX_PINCTRL_PIN(MX6UL_PAD_ENET1_RX_DATA0),
|
||||
IMX_PINCTRL_PIN(MX6UL_PAD_ENET1_RX_DATA1),
|
||||
IMX_PINCTRL_PIN(MX6UL_PAD_ENET1_RX_EN),
|
||||
IMX_PINCTRL_PIN(MX6UL_PAD_ENET1_TX_DATA0),
|
||||
IMX_PINCTRL_PIN(MX6UL_PAD_ENET1_TX_DATA1),
|
||||
IMX_PINCTRL_PIN(MX6UL_PAD_ENET1_TX_EN),
|
||||
IMX_PINCTRL_PIN(MX6UL_PAD_ENET1_TX_CLK),
|
||||
IMX_PINCTRL_PIN(MX6UL_PAD_ENET1_RX_ER),
|
||||
IMX_PINCTRL_PIN(MX6UL_PAD_ENET2_RX_DATA0),
|
||||
IMX_PINCTRL_PIN(MX6UL_PAD_ENET2_RX_DATA1),
|
||||
IMX_PINCTRL_PIN(MX6UL_PAD_ENET2_RX_EN),
|
||||
IMX_PINCTRL_PIN(MX6UL_PAD_ENET2_TX_DATA0),
|
||||
IMX_PINCTRL_PIN(MX6UL_PAD_ENET2_TX_DATA1),
|
||||
IMX_PINCTRL_PIN(MX6UL_PAD_ENET2_TX_EN),
|
||||
IMX_PINCTRL_PIN(MX6UL_PAD_ENET2_TX_CLK),
|
||||
IMX_PINCTRL_PIN(MX6UL_PAD_ENET2_RX_ER),
|
||||
IMX_PINCTRL_PIN(MX6UL_PAD_LCD_CLK),
|
||||
IMX_PINCTRL_PIN(MX6UL_PAD_LCD_ENABLE),
|
||||
IMX_PINCTRL_PIN(MX6UL_PAD_LCD_HSYNC),
|
||||
IMX_PINCTRL_PIN(MX6UL_PAD_LCD_VSYNC),
|
||||
IMX_PINCTRL_PIN(MX6UL_PAD_LCD_RESET),
|
||||
IMX_PINCTRL_PIN(MX6UL_PAD_LCD_DATA00),
|
||||
IMX_PINCTRL_PIN(MX6UL_PAD_LCD_DATA01),
|
||||
IMX_PINCTRL_PIN(MX6UL_PAD_LCD_DATA02),
|
||||
IMX_PINCTRL_PIN(MX6UL_PAD_LCD_DATA03),
|
||||
IMX_PINCTRL_PIN(MX6UL_PAD_LCD_DATA04),
|
||||
IMX_PINCTRL_PIN(MX6UL_PAD_LCD_DATA05),
|
||||
IMX_PINCTRL_PIN(MX6UL_PAD_LCD_DATA06),
|
||||
IMX_PINCTRL_PIN(MX6UL_PAD_LCD_DATA07),
|
||||
IMX_PINCTRL_PIN(MX6UL_PAD_LCD_DATA08),
|
||||
IMX_PINCTRL_PIN(MX6UL_PAD_LCD_DATA09),
|
||||
IMX_PINCTRL_PIN(MX6UL_PAD_LCD_DATA10),
|
||||
IMX_PINCTRL_PIN(MX6UL_PAD_LCD_DATA11),
|
||||
IMX_PINCTRL_PIN(MX6UL_PAD_LCD_DATA12),
|
||||
IMX_PINCTRL_PIN(MX6UL_PAD_LCD_DATA13),
|
||||
IMX_PINCTRL_PIN(MX6UL_PAD_LCD_DATA14),
|
||||
IMX_PINCTRL_PIN(MX6UL_PAD_LCD_DATA15),
|
||||
IMX_PINCTRL_PIN(MX6UL_PAD_LCD_DATA16),
|
||||
IMX_PINCTRL_PIN(MX6UL_PAD_LCD_DATA17),
|
||||
IMX_PINCTRL_PIN(MX6UL_PAD_LCD_DATA18),
|
||||
IMX_PINCTRL_PIN(MX6UL_PAD_LCD_DATA19),
|
||||
IMX_PINCTRL_PIN(MX6UL_PAD_LCD_DATA20),
|
||||
IMX_PINCTRL_PIN(MX6UL_PAD_LCD_DATA21),
|
||||
IMX_PINCTRL_PIN(MX6UL_PAD_LCD_DATA22),
|
||||
IMX_PINCTRL_PIN(MX6UL_PAD_LCD_DATA23),
|
||||
IMX_PINCTRL_PIN(MX6UL_PAD_NAND_RE_B),
|
||||
IMX_PINCTRL_PIN(MX6UL_PAD_NAND_WE_B),
|
||||
IMX_PINCTRL_PIN(MX6UL_PAD_NAND_DATA00),
|
||||
IMX_PINCTRL_PIN(MX6UL_PAD_NAND_DATA01),
|
||||
IMX_PINCTRL_PIN(MX6UL_PAD_NAND_DATA02),
|
||||
IMX_PINCTRL_PIN(MX6UL_PAD_NAND_DATA03),
|
||||
IMX_PINCTRL_PIN(MX6UL_PAD_NAND_DATA04),
|
||||
IMX_PINCTRL_PIN(MX6UL_PAD_NAND_DATA05),
|
||||
IMX_PINCTRL_PIN(MX6UL_PAD_NAND_DATA06),
|
||||
IMX_PINCTRL_PIN(MX6UL_PAD_NAND_DATA07),
|
||||
IMX_PINCTRL_PIN(MX6UL_PAD_NAND_ALE),
|
||||
IMX_PINCTRL_PIN(MX6UL_PAD_NAND_WP_B),
|
||||
IMX_PINCTRL_PIN(MX6UL_PAD_NAND_READY_B),
|
||||
IMX_PINCTRL_PIN(MX6UL_PAD_NAND_CE0_B),
|
||||
IMX_PINCTRL_PIN(MX6UL_PAD_NAND_CE1_B),
|
||||
IMX_PINCTRL_PIN(MX6UL_PAD_NAND_CLE),
|
||||
IMX_PINCTRL_PIN(MX6UL_PAD_NAND_DQS),
|
||||
IMX_PINCTRL_PIN(MX6UL_PAD_SD1_CMD),
|
||||
IMX_PINCTRL_PIN(MX6UL_PAD_SD1_CLK),
|
||||
IMX_PINCTRL_PIN(MX6UL_PAD_SD1_DATA0),
|
||||
IMX_PINCTRL_PIN(MX6UL_PAD_SD1_DATA1),
|
||||
IMX_PINCTRL_PIN(MX6UL_PAD_SD1_DATA2),
|
||||
IMX_PINCTRL_PIN(MX6UL_PAD_SD1_DATA3),
|
||||
IMX_PINCTRL_PIN(MX6UL_PAD_CSI_MCLK),
|
||||
IMX_PINCTRL_PIN(MX6UL_PAD_CSI_PIXCLK),
|
||||
IMX_PINCTRL_PIN(MX6UL_PAD_CSI_VSYNC),
|
||||
IMX_PINCTRL_PIN(MX6UL_PAD_CSI_HSYNC),
|
||||
IMX_PINCTRL_PIN(MX6UL_PAD_CSI_DATA00),
|
||||
IMX_PINCTRL_PIN(MX6UL_PAD_CSI_DATA01),
|
||||
IMX_PINCTRL_PIN(MX6UL_PAD_CSI_DATA02),
|
||||
IMX_PINCTRL_PIN(MX6UL_PAD_CSI_DATA03),
|
||||
IMX_PINCTRL_PIN(MX6UL_PAD_CSI_DATA04),
|
||||
IMX_PINCTRL_PIN(MX6UL_PAD_CSI_DATA05),
|
||||
IMX_PINCTRL_PIN(MX6UL_PAD_CSI_DATA06),
|
||||
IMX_PINCTRL_PIN(MX6UL_PAD_CSI_DATA07),
|
||||
};
|
||||
|
||||
static struct imx_pinctrl_soc_info imx6ul_pinctrl_info = {
|
||||
.pins = imx6ul_pinctrl_pads,
|
||||
.npins = ARRAY_SIZE(imx6ul_pinctrl_pads),
|
||||
};
|
||||
|
||||
static struct of_device_id imx6ul_pinctrl_of_match[] = {
|
||||
{ .compatible = "fsl,imx6ul-iomuxc", },
|
||||
{ /* sentinel */ }
|
||||
};
|
||||
|
||||
static int imx6ul_pinctrl_probe(struct platform_device *pdev)
|
||||
{
|
||||
return imx_pinctrl_probe(pdev, &imx6ul_pinctrl_info);
|
||||
}
|
||||
|
||||
static struct platform_driver imx6ul_pinctrl_driver = {
|
||||
.driver = {
|
||||
.name = "imx6ul-pinctrl",
|
||||
.of_match_table = of_match_ptr(imx6ul_pinctrl_of_match),
|
||||
},
|
||||
.probe = imx6ul_pinctrl_probe,
|
||||
.remove = imx_pinctrl_remove,
|
||||
};
|
||||
|
||||
static int __init imx6ul_pinctrl_init(void)
|
||||
{
|
||||
return platform_driver_register(&imx6ul_pinctrl_driver);
|
||||
}
|
||||
arch_initcall(imx6ul_pinctrl_init);
|
||||
|
||||
static void __exit imx6ul_pinctrl_exit(void)
|
||||
{
|
||||
platform_driver_unregister(&imx6ul_pinctrl_driver);
|
||||
}
|
||||
module_exit(imx6ul_pinctrl_exit);
|
||||
|
||||
MODULE_AUTHOR("Anson Huang <Anson.Huang@freescale.com>");
|
||||
MODULE_DESCRIPTION("Freescale imx6ul pinctrl driver");
|
||||
MODULE_LICENSE("GPL v2");
|
||||
|
|
@ -12,11 +12,6 @@
|
|||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along with
|
||||
* this program; if not, write to the Free Software Foundation, Inc.,
|
||||
* 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
|
||||
*
|
||||
*/
|
||||
|
||||
#include <linux/kernel.h>
|
||||
|
|
@ -146,7 +141,7 @@ struct byt_gpio_pin_context {
|
|||
struct byt_gpio {
|
||||
struct gpio_chip chip;
|
||||
struct platform_device *pdev;
|
||||
spinlock_t lock;
|
||||
raw_spinlock_t lock;
|
||||
void __iomem *reg_base;
|
||||
struct pinctrl_gpio_range *range;
|
||||
struct byt_gpio_pin_context *saved_context;
|
||||
|
|
@ -174,11 +169,11 @@ static void byt_gpio_clear_triggering(struct byt_gpio *vg, unsigned offset)
|
|||
unsigned long flags;
|
||||
u32 value;
|
||||
|
||||
spin_lock_irqsave(&vg->lock, flags);
|
||||
raw_spin_lock_irqsave(&vg->lock, flags);
|
||||
value = readl(reg);
|
||||
value &= ~(BYT_TRIG_POS | BYT_TRIG_NEG | BYT_TRIG_LVL);
|
||||
writel(value, reg);
|
||||
spin_unlock_irqrestore(&vg->lock, flags);
|
||||
raw_spin_unlock_irqrestore(&vg->lock, flags);
|
||||
}
|
||||
|
||||
static u32 byt_get_gpio_mux(struct byt_gpio *vg, unsigned offset)
|
||||
|
|
@ -201,6 +196,9 @@ static int byt_gpio_request(struct gpio_chip *chip, unsigned offset)
|
|||
struct byt_gpio *vg = to_byt_gpio(chip);
|
||||
void __iomem *reg = byt_gpio_reg(chip, offset, BYT_CONF0_REG);
|
||||
u32 value, gpio_mux;
|
||||
unsigned long flags;
|
||||
|
||||
raw_spin_lock_irqsave(&vg->lock, flags);
|
||||
|
||||
/*
|
||||
* In most cases, func pin mux 000 means GPIO function.
|
||||
|
|
@ -214,18 +212,16 @@ static int byt_gpio_request(struct gpio_chip *chip, unsigned offset)
|
|||
value = readl(reg) & BYT_PIN_MUX;
|
||||
gpio_mux = byt_get_gpio_mux(vg, offset);
|
||||
if (WARN_ON(gpio_mux != value)) {
|
||||
unsigned long flags;
|
||||
|
||||
spin_lock_irqsave(&vg->lock, flags);
|
||||
value = readl(reg) & ~BYT_PIN_MUX;
|
||||
value |= gpio_mux;
|
||||
writel(value, reg);
|
||||
spin_unlock_irqrestore(&vg->lock, flags);
|
||||
|
||||
dev_warn(&vg->pdev->dev,
|
||||
"pin %u forcibly re-configured as GPIO\n", offset);
|
||||
}
|
||||
|
||||
raw_spin_unlock_irqrestore(&vg->lock, flags);
|
||||
|
||||
pm_runtime_get(&vg->pdev->dev);
|
||||
|
||||
return 0;
|
||||
|
|
@ -250,7 +246,7 @@ static int byt_irq_type(struct irq_data *d, unsigned type)
|
|||
if (offset >= vg->chip.ngpio)
|
||||
return -EINVAL;
|
||||
|
||||
spin_lock_irqsave(&vg->lock, flags);
|
||||
raw_spin_lock_irqsave(&vg->lock, flags);
|
||||
value = readl(reg);
|
||||
|
||||
WARN(value & BYT_DIRECT_IRQ_EN,
|
||||
|
|
@ -265,11 +261,11 @@ static int byt_irq_type(struct irq_data *d, unsigned type)
|
|||
writel(value, reg);
|
||||
|
||||
if (type & IRQ_TYPE_EDGE_BOTH)
|
||||
__irq_set_handler_locked(d->irq, handle_edge_irq);
|
||||
irq_set_handler_locked(d, handle_edge_irq);
|
||||
else if (type & IRQ_TYPE_LEVEL_MASK)
|
||||
__irq_set_handler_locked(d->irq, handle_level_irq);
|
||||
irq_set_handler_locked(d, handle_level_irq);
|
||||
|
||||
spin_unlock_irqrestore(&vg->lock, flags);
|
||||
raw_spin_unlock_irqrestore(&vg->lock, flags);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -277,7 +273,15 @@ static int byt_irq_type(struct irq_data *d, unsigned type)
|
|||
static int byt_gpio_get(struct gpio_chip *chip, unsigned offset)
|
||||
{
|
||||
void __iomem *reg = byt_gpio_reg(chip, offset, BYT_VAL_REG);
|
||||
return readl(reg) & BYT_LEVEL;
|
||||
struct byt_gpio *vg = to_byt_gpio(chip);
|
||||
unsigned long flags;
|
||||
u32 val;
|
||||
|
||||
raw_spin_lock_irqsave(&vg->lock, flags);
|
||||
val = readl(reg);
|
||||
raw_spin_unlock_irqrestore(&vg->lock, flags);
|
||||
|
||||
return val & BYT_LEVEL;
|
||||
}
|
||||
|
||||
static void byt_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
|
||||
|
|
@ -287,7 +291,7 @@ static void byt_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
|
|||
unsigned long flags;
|
||||
u32 old_val;
|
||||
|
||||
spin_lock_irqsave(&vg->lock, flags);
|
||||
raw_spin_lock_irqsave(&vg->lock, flags);
|
||||
|
||||
old_val = readl(reg);
|
||||
|
||||
|
|
@ -296,7 +300,7 @@ static void byt_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
|
|||
else
|
||||
writel(old_val & ~BYT_LEVEL, reg);
|
||||
|
||||
spin_unlock_irqrestore(&vg->lock, flags);
|
||||
raw_spin_unlock_irqrestore(&vg->lock, flags);
|
||||
}
|
||||
|
||||
static int byt_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
|
||||
|
|
@ -306,13 +310,13 @@ static int byt_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
|
|||
unsigned long flags;
|
||||
u32 value;
|
||||
|
||||
spin_lock_irqsave(&vg->lock, flags);
|
||||
raw_spin_lock_irqsave(&vg->lock, flags);
|
||||
|
||||
value = readl(reg) | BYT_DIR_MASK;
|
||||
value &= ~BYT_INPUT_EN; /* active low */
|
||||
writel(value, reg);
|
||||
|
||||
spin_unlock_irqrestore(&vg->lock, flags);
|
||||
raw_spin_unlock_irqrestore(&vg->lock, flags);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -326,7 +330,7 @@ static int byt_gpio_direction_output(struct gpio_chip *chip,
|
|||
unsigned long flags;
|
||||
u32 reg_val;
|
||||
|
||||
spin_lock_irqsave(&vg->lock, flags);
|
||||
raw_spin_lock_irqsave(&vg->lock, flags);
|
||||
|
||||
/*
|
||||
* Before making any direction modifications, do a check if gpio
|
||||
|
|
@ -345,7 +349,7 @@ static int byt_gpio_direction_output(struct gpio_chip *chip,
|
|||
else
|
||||
writel(reg_val & ~BYT_LEVEL, reg);
|
||||
|
||||
spin_unlock_irqrestore(&vg->lock, flags);
|
||||
raw_spin_unlock_irqrestore(&vg->lock, flags);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -354,18 +358,19 @@ static void byt_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip)
|
|||
{
|
||||
struct byt_gpio *vg = to_byt_gpio(chip);
|
||||
int i;
|
||||
unsigned long flags;
|
||||
u32 conf0, val, offs;
|
||||
|
||||
spin_lock_irqsave(&vg->lock, flags);
|
||||
|
||||
for (i = 0; i < vg->chip.ngpio; i++) {
|
||||
const char *pull_str = NULL;
|
||||
const char *pull = NULL;
|
||||
unsigned long flags;
|
||||
const char *label;
|
||||
offs = vg->range->pins[i] * 16;
|
||||
|
||||
raw_spin_lock_irqsave(&vg->lock, flags);
|
||||
conf0 = readl(vg->reg_base + offs + BYT_CONF0_REG);
|
||||
val = readl(vg->reg_base + offs + BYT_VAL_REG);
|
||||
raw_spin_unlock_irqrestore(&vg->lock, flags);
|
||||
|
||||
label = gpiochip_is_requested(chip, i);
|
||||
if (!label)
|
||||
|
|
@ -418,7 +423,6 @@ static void byt_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip)
|
|||
|
||||
seq_puts(s, "\n");
|
||||
}
|
||||
spin_unlock_irqrestore(&vg->lock, flags);
|
||||
}
|
||||
|
||||
static void byt_gpio_irq_handler(unsigned irq, struct irq_desc *desc)
|
||||
|
|
@ -450,8 +454,10 @@ static void byt_irq_ack(struct irq_data *d)
|
|||
unsigned offset = irqd_to_hwirq(d);
|
||||
void __iomem *reg;
|
||||
|
||||
raw_spin_lock(&vg->lock);
|
||||
reg = byt_gpio_reg(&vg->chip, offset, BYT_INT_STAT_REG);
|
||||
writel(BIT(offset % 32), reg);
|
||||
raw_spin_unlock(&vg->lock);
|
||||
}
|
||||
|
||||
static void byt_irq_unmask(struct irq_data *d)
|
||||
|
|
@ -463,9 +469,9 @@ static void byt_irq_unmask(struct irq_data *d)
|
|||
void __iomem *reg;
|
||||
u32 value;
|
||||
|
||||
spin_lock_irqsave(&vg->lock, flags);
|
||||
|
||||
reg = byt_gpio_reg(&vg->chip, offset, BYT_CONF0_REG);
|
||||
|
||||
raw_spin_lock_irqsave(&vg->lock, flags);
|
||||
value = readl(reg);
|
||||
|
||||
switch (irqd_get_trigger_type(d)) {
|
||||
|
|
@ -486,7 +492,7 @@ static void byt_irq_unmask(struct irq_data *d)
|
|||
|
||||
writel(value, reg);
|
||||
|
||||
spin_unlock_irqrestore(&vg->lock, flags);
|
||||
raw_spin_unlock_irqrestore(&vg->lock, flags);
|
||||
}
|
||||
|
||||
static void byt_irq_mask(struct irq_data *d)
|
||||
|
|
@ -578,7 +584,7 @@ static int byt_gpio_probe(struct platform_device *pdev)
|
|||
if (IS_ERR(vg->reg_base))
|
||||
return PTR_ERR(vg->reg_base);
|
||||
|
||||
spin_lock_init(&vg->lock);
|
||||
raw_spin_lock_init(&vg->lock);
|
||||
|
||||
gc = &vg->chip;
|
||||
gc->label = dev_name(&pdev->dev);
|
||||
|
|
|
|||
Some files were not shown because too many files have changed in this diff Show more
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Reference in a new issue