Merge branch 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/jikos/trivial
Pull trivial tree updates from Jiri Kosina: "The usual stuff from trivial tree" * 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/jikos/trivial: (34 commits) treewide: relase -> release Documentation/cgroups/memory.txt: fix stat file documentation sysctl/net.txt: delete reference to obsolete 2.4.x kernel spinlock_api_smp.h: fix preprocessor comments treewide: Fix typo in printk doc: device tree: clarify stuff in usage-model.txt. open firmware: "/aliasas" -> "/aliases" md: bcache: Fixed a typo with the word 'arithmetic' irq/generic-chip: fix a few kernel-doc entries frv: Convert use of typedef ctl_table to struct ctl_table sgi: xpc: Convert use of typedef ctl_table to struct ctl_table doc: clk: Fix incorrect wording Documentation/arm/IXP4xx fix a typo Documentation/networking/ieee802154 fix a typo Documentation/DocBook/media/v4l fix a typo Documentation/video4linux/si476x.txt fix a typo Documentation/virtual/kvm/api.txt fix a typo Documentation/early-userspace/README fix a typo Documentation/video4linux/soc-camera.txt fix a typo lguest: fix CONFIG_PAE -> CONFIG_x86_PAE in comment ...
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96 changed files with 142 additions and 151 deletions
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@ -434,7 +434,7 @@ char *date;</synopsis>
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The DRM core includes two memory managers, namely Translation Table Maps
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(TTM) and Graphics Execution Manager (GEM). TTM was the first DRM memory
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manager to be developed and tried to be a one-size-fits-them all
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solution. It provides a single userspace API to accomodate the need of
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solution. It provides a single userspace API to accommodate the need of
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all hardware, supporting both Unified Memory Architecture (UMA) devices
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and devices with dedicated video RAM (i.e. most discrete video cards).
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This resulted in a large, complex piece of code that turned out to be
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@ -701,7 +701,7 @@ char *date;</synopsis>
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<para>
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Similar to global names, GEM file descriptors are also used to share GEM
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objects across processes. They offer additional security: as file
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descriptors must be explictly sent over UNIX domain sockets to be shared
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descriptors must be explicitly sent over UNIX domain sockets to be shared
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between applications, they can't be guessed like the globally unique GEM
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names.
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</para>
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@ -1154,7 +1154,7 @@ int max_width, max_height;</synopsis>
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</para>
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<para>
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The <methodname>page_flip</methodname> operation schedules a page flip.
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Once any pending rendering targetting the new frame buffer has
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Once any pending rendering targeting the new frame buffer has
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completed, the CRTC will be reprogrammed to display that frame buffer
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after the next vertical refresh. The operation must return immediately
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without waiting for rendering or page flip to complete and must block
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@ -233,7 +233,7 @@ typedef enum fe_status {
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<entry align="char">The frontend FEC inner coding (Viterbi, LDPC or other inner code) is stable</entry>
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</row><row>
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<entry align="char">FE_HAS_SYNC</entry>
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<entry align="char">Syncronization bytes was found</entry>
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<entry align="char">Synchronization bytes was found</entry>
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</row><row>
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<entry align="char">FE_HAS_LOCK</entry>
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<entry align="char">The DVB were locked and everything is working</entry>
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@ -3147,7 +3147,7 @@ giving priority to the center of the metered area.</entry>
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<entry>A multi-zone metering. The light intensity is measured
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in several points of the frame and the the results are combined. The
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algorithm of the zones selection and their significance in calculating the
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final value is device dependant.</entry>
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final value is device dependent.</entry>
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</row>
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</tbody>
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</entrytbl>
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@ -24,7 +24,7 @@ into 64x32 macroblocks. The CbCr plane has the same width, in bytes, as the Y
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plane (and the image), but is half as tall in pixels. The chroma plane is also
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grouped into 64x32 macroblocks.</para>
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<para>Width of the buffer has to be aligned to the multiple of 128, and
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height alignment is 32. Every four adjactent buffers - two horizontally and two
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height alignment is 32. Every four adjacent buffers - two horizontally and two
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vertically are grouped together and are located in memory in Z or flipped Z
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order. </para>
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<para>Layout of macroblocks in memory is presented in the following
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@ -83,7 +83,7 @@
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</para>
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<para>
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Because each different protocol causes a new driver to be created, I have
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written a generic USB driver skeleton, modeled after the pci-skeleton.c
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written a generic USB driver skeleton, modelled after the pci-skeleton.c
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file in the kernel source tree upon which many PCI network drivers have
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been based. This USB skeleton can be found at drivers/usb/usb-skeleton.c
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in the kernel source tree. In this article I will walk through the basics
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@ -36,7 +36,7 @@ Linux currently supports the following features on the IXP4xx chips:
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- Timers (watchdog, OS)
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The following components of the chips are not supported by Linux and
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require the use of Intel's proprietary CSR softare:
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require the use of Intel's proprietary CSR software:
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- USB device interface
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- Network interfaces (HSS, Utopia, NPEs, etc)
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@ -181,7 +181,7 @@ want for getting the best possible numbers when benchmarking.
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In practice this isn't an issue because as soon as a write comes along it'll
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cause the btree node to be split, and you need almost no write traffic for
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this to not show up enough to be noticable (especially since bcache's btree
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this to not show up enough to be noticeable (especially since bcache's btree
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nodes are huge and index large regions of the device). But when you're
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benchmarking, if you're trying to warm the cache by reading a bunch of data
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and there's no other traffic - that can be a problem.
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@ -222,7 +222,7 @@ running
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it's in passthrough mode or caching).
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sequential_cutoff
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A sequential IO will bypass the cache once it passes this threshhold; the
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A sequential IO will bypass the cache once it passes this threshold; the
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most recent 128 IOs are tracked so sequential IO can be detected even when
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it isn't all done at once.
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@ -296,7 +296,7 @@ cache_miss_collisions
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since the synchronization for cache misses was rewritten)
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cache_readaheads
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Count of times readahead occured.
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Count of times readahead occurred.
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SYSFS - CACHE SET:
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@ -362,7 +362,7 @@ unregister
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SYSFS - CACHE SET INTERNAL:
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This directory also exposes timings for a number of internal operations, with
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separate files for average duration, average frequency, last occurence and max
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separate files for average duration, average frequency, last occurrence and max
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duration: garbage collection, btree read, btree node sorts and btree splits.
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active_journal_entries
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@ -417,7 +417,7 @@ freelist_percent
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space.
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io_errors
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Number of errors that have occured, decayed by io_error_halflife.
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Number of errors that have occurred, decayed by io_error_halflife.
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metadata_written
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Sum of all non data writes (btree writes and all other metadata).
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@ -93,7 +93,7 @@ To avoid priority inversion through request starvation, a request
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queue maintains a separate request pool per each cgroup when
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CONFIG_BLK_CGROUP is enabled, and this parameter applies to each such
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per-block-cgroup request pool. IOW, if there are N block cgroups,
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each request queue may have upto N request pools, each independently
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each request queue may have up to N request pools, each independently
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regulated by nr_requests.
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optimal_io_size (RO)
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@ -304,7 +304,7 @@ kernel memory, we prevent new processes from being created when the kernel
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memory usage is too high.
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* slab pages: pages allocated by the SLAB or SLUB allocator are tracked. A copy
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of each kmem_cache is created everytime the cache is touched by the first time
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of each kmem_cache is created every time the cache is touched by the first time
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from inside the memcg. The creation is done lazily, so some objects can still be
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skipped while the cache is being created. All objects in a slab page should
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belong to the same memcg. This only fails to hold when a task is migrated to a
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@ -490,10 +490,10 @@ pgpgin - # of charging events to the memory cgroup. The charging
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pgpgout - # of uncharging events to the memory cgroup. The uncharging
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event happens each time a page is unaccounted from the cgroup.
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swap - # of bytes of swap usage
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inactive_anon - # of bytes of anonymous memory and swap cache memory on
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inactive_anon - # of bytes of anonymous and swap cache memory on inactive
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LRU list.
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active_anon - # of bytes of anonymous and swap cache memory on active
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inactive LRU list.
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LRU list.
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inactive_file - # of bytes of file-backed memory on inactive LRU list.
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active_file - # of bytes of file-backed memory on active LRU list.
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unevictable - # of bytes of memory that cannot be reclaimed (mlocked etc).
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@ -32,7 +32,7 @@ hardware-specific bits for the hypothetical "foo" hardware.
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Tying the two halves of this interface together is struct clk_hw, which
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is defined in struct clk_foo and pointed to within struct clk. This
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allows easy for navigation between the two discrete halves of the common
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allows for easy navigation between the two discrete halves of the common
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clock interface.
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Part 2 - common data structures and api
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@ -87,7 +87,7 @@ Migration throttling
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Migrating data between the origin and cache device uses bandwidth.
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The user can set a throttle to prevent more than a certain amount of
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migration occuring at any one time. Currently we're not taking any
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migration occurring at any one time. Currently we're not taking any
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account of normal io traffic going to the devices. More work needs
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doing here to avoid migrating during those peak io moments.
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@ -5,7 +5,7 @@ can combine interrupt sources as a group and provide a single interrupt request
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for the group. The interrupt request from each group are connected to a parent
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interrupt controller, such as GIC in case of Exynos4210.
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The interrupt combiner controller consists of multiple combiners. Upto eight
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The interrupt combiner controller consists of multiple combiners. Up to eight
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interrupt sources can be connected to a combiner. The combiner outputs one
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combined interrupt for its eight interrupt sources. The combined interrupt
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is usually connected to a parent interrupt controller.
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@ -14,8 +14,8 @@ A single node in the device tree is used to describe the interrupt combiner
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controller module (which includes multiple combiners). A combiner in the
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interrupt controller module shares config/control registers with other
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combiners. For example, a 32-bit interrupt enable/disable config register
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can accommodate upto 4 interrupt combiners (with each combiner supporting
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upto 8 interrupt sources).
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can accommodate up to 4 interrupt combiners (with each combiner supporting
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up to 8 interrupt sources).
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Required properties:
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- compatible: should be "samsung,exynos4210-combiner".
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@ -14,7 +14,7 @@ A single node in the device tree is used to describe the shared
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interrupt multiplexor (one node for all groups). A group in the
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interrupt controller shares config/control registers with other groups.
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For example, a 32-bit interrupt enable/disable config register can
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accommodate upto 4 interrupt groups.
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accommodate up to 4 interrupt groups.
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Required properties:
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- compatible: should be, either of
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@ -4,7 +4,7 @@ Reference
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[1] Si5351A/B/C Data Sheet
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http://www.silabs.com/Support%20Documents/TechnicalDocs/Si5351.pdf
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The Si5351a/b/c are programmable i2c clock generators with upto 8 output
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The Si5351a/b/c are programmable i2c clock generators with up to 8 output
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clocks. Si5351a also has a reduced pin-count package (MSOP10) where only
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3 output clocks are accessible. The internal structure of the clock
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generators can be found in [1].
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@ -51,7 +51,7 @@ Optional properties:
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* card-detect-delay: Delay in milli-seconds before detecting card after card
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insert event. The default value is 0.
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* supports-highspeed: Enables support for high speed cards (upto 50MHz)
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* supports-highspeed: Enables support for high speed cards (up to 50MHz)
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* broken-cd: as documented in mmc core bindings.
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@ -1,7 +1,7 @@
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4xx/Axon EMAC ethernet nodes
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The EMAC ethernet controller in IBM and AMCC 4xx chips, and also
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the Axon bridge. To operate this needs to interact with a ths
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the Axon bridge. To operate this needs to interact with a this
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special McMAL DMA controller, and sometimes an RGMII or ZMII
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interface. In addition to the nodes and properties described
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below, the node for the OPB bus on which the EMAC sits must have a
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@ -2,7 +2,7 @@ Broadcom BCM2835 SPI0 controller
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The BCM2835 contains two forms of SPI master controller, one known simply as
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SPI0, and the other known as the "Universal SPI Master"; part of the
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auxilliary block. This binding applies to the SPI0 controller.
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auxiliary block. This binding applies to the SPI0 controller.
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Required properties:
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- compatible: Should be "brcm,bcm2835-spi".
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@ -44,7 +44,7 @@ Example 1: In this example, the system uses only the first global timer
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};
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Example 2: In this example, the MCT global and local timer interrupts are
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connected to two seperate interrupt controllers. Hence, an
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connected to two separate interrupt controllers. Hence, an
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interrupt-map is created to map the interrupts to the respective
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interrupt controllers.
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@ -12,7 +12,7 @@ AM33XX MUSB GLUE
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represents PERIPHERAL.
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- port1-mode : Should be "1" to represent HOST. "3" signifies OTG and "2"
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represents PERIPHERAL.
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- power : Should be "250". This signifies the controller can supply upto
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- power : Should be "250". This signifies the controller can supply up to
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500mA when operating in host mode.
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Example:
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@ -16,7 +16,7 @@ OMAP MUSB GLUE
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specifying ULPI and UTMI respectively.
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- mode : Should be "3" to represent OTG. "1" signifies HOST and "2"
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represents PERIPHERAL.
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- power : Should be "50". This signifies the controller can supply upto
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- power : Should be "50". This signifies the controller can supply up to
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100mA when operating in host mode.
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- usb-phy : the phandle for the PHY device
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