ARM i.MX: Merge i.MX5 support into mach-imx
This patch moves the contents of arch/arm/mach-mx5 to arch/arm/mach-imx and adjusts the Makefile/Kconfig entries in a way that it's possible to compile i.MX5 together with i.MX3/6. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Tested-by: Shawn Guo <shawn.guo@linaro.org> Tested-by: Dirk Behme <dirk.behme@de.bosch.com>
This commit is contained in:
Sascha Hauer
parent
035c17dac4
commit
784a90c0a7
37 changed files with 356 additions and 385 deletions
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@ -160,7 +160,6 @@ machine-$(CONFIG_ARCH_MSM) := msm
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machine-$(CONFIG_ARCH_MV78XX0) := mv78xx0
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machine-$(CONFIG_ARCH_IMX_V4_V5) := imx
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machine-$(CONFIG_ARCH_IMX_V6_V7) := imx
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machine-$(CONFIG_ARCH_MX5) := mx5
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machine-$(CONFIG_ARCH_MXS) := mxs
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machine-$(CONFIG_ARCH_NETX) := netx
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machine-$(CONFIG_ARCH_NOMADIK) := nomadik
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@ -33,6 +33,18 @@ config ARCH_MX31
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config ARCH_MX35
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bool
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config ARCH_MX5
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bool
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config ARCH_MX50
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bool
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config ARCH_MX51
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bool
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config ARCH_MX53
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bool
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config SOC_IMX1
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bool
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select ARCH_MX1
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@ -86,6 +98,32 @@ config SOC_IMX35
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select MXC_AVIC
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select SMP_ON_UP if SMP
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config SOC_IMX5
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select CPU_V7
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select ARM_L1_CACHE_SHIFT_6
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select MXC_TZIC
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select ARCH_MXC_IOMUX_V3
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select ARCH_MXC_AUDMUX_V2
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select ARCH_HAS_CPUFREQ
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select ARCH_MX5
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bool
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config SOC_IMX50
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bool
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select SOC_IMX5
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select ARCH_MX50
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config SOC_IMX51
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bool
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select SOC_IMX5
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select ARCH_MX5
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select ARCH_MX51
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config SOC_IMX53
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bool
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select SOC_IMX5
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select ARCH_MX5
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select ARCH_MX53
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if ARCH_IMX_V4_V5
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@ -604,6 +642,207 @@ config MACH_VPR200
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Include support for VPR200 platform. This includes specific
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configurations for the board and its peripherals.
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comment "i.MX5 platforms:"
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config MACH_MX50_RDP
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bool "Support MX50 reference design platform"
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depends on BROKEN
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select SOC_IMX50
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select IMX_HAVE_PLATFORM_IMX_I2C
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select IMX_HAVE_PLATFORM_IMX_UART
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select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX
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select IMX_HAVE_PLATFORM_SPI_IMX
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help
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Include support for MX50 reference design platform (RDP) board. This
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includes specific configurations for the board and its peripherals.
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comment "i.MX51 machines:"
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config MACH_IMX51_DT
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bool "Support i.MX51 platforms from device tree"
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select SOC_IMX51
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select USE_OF
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select MACH_MX51_BABBAGE
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help
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Include support for Freescale i.MX51 based platforms
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using the device tree for discovery
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config MACH_MX51_BABBAGE
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bool "Support MX51 BABBAGE platforms"
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select SOC_IMX51
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select IMX_HAVE_PLATFORM_FSL_USB2_UDC
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select IMX_HAVE_PLATFORM_IMX2_WDT
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select IMX_HAVE_PLATFORM_IMX_I2C
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select IMX_HAVE_PLATFORM_IMX_UART
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select IMX_HAVE_PLATFORM_MXC_EHCI
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select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX
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select IMX_HAVE_PLATFORM_SPI_IMX
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help
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Include support for MX51 Babbage platform, also known as MX51EVK in
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u-boot. This includes specific configurations for the board and its
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peripherals.
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config MACH_MX51_3DS
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bool "Support MX51PDK (3DS)"
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select SOC_IMX51
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select IMX_HAVE_PLATFORM_IMX2_WDT
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select IMX_HAVE_PLATFORM_IMX_KEYPAD
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select IMX_HAVE_PLATFORM_IMX_UART
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select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX
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select IMX_HAVE_PLATFORM_SPI_IMX
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select MXC_DEBUG_BOARD
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help
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Include support for MX51PDK (3DS) platform. This includes specific
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configurations for the board and its peripherals.
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config MACH_EUKREA_CPUIMX51
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bool "Support Eukrea CPUIMX51 module"
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select SOC_IMX51
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select IMX_HAVE_PLATFORM_FSL_USB2_UDC
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select IMX_HAVE_PLATFORM_IMX_I2C
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select IMX_HAVE_PLATFORM_IMX_UART
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select IMX_HAVE_PLATFORM_MXC_EHCI
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select IMX_HAVE_PLATFORM_MXC_NAND
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select IMX_HAVE_PLATFORM_SPI_IMX
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help
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Include support for Eukrea CPUIMX51 platform. This includes
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specific configurations for the module and its peripherals.
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choice
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prompt "Baseboard"
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depends on MACH_EUKREA_CPUIMX51
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default MACH_EUKREA_MBIMX51_BASEBOARD
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config MACH_EUKREA_MBIMX51_BASEBOARD
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prompt "Eukrea MBIMX51 development board"
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bool
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select IMX_HAVE_PLATFORM_IMX_KEYPAD
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select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX
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select LEDS_GPIO_REGISTER
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help
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This adds board specific devices that can be found on Eukrea's
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MBIMX51 evaluation board.
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endchoice
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config MACH_EUKREA_CPUIMX51SD
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bool "Support Eukrea CPUIMX51SD module"
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select SOC_IMX51
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select IMX_HAVE_PLATFORM_FSL_USB2_UDC
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select IMX_HAVE_PLATFORM_IMX_I2C
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select IMX_HAVE_PLATFORM_IMX_UART
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select IMX_HAVE_PLATFORM_MXC_EHCI
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select IMX_HAVE_PLATFORM_MXC_NAND
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select IMX_HAVE_PLATFORM_SPI_IMX
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help
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Include support for Eukrea CPUIMX51SD platform. This includes
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specific configurations for the module and its peripherals.
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choice
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prompt "Baseboard"
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depends on MACH_EUKREA_CPUIMX51SD
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default MACH_EUKREA_MBIMXSD51_BASEBOARD
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config MACH_EUKREA_MBIMXSD51_BASEBOARD
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prompt "Eukrea MBIMXSD development board"
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bool
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select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX
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select LEDS_GPIO_REGISTER
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help
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This adds board specific devices that can be found on Eukrea's
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MBIMXSD evaluation board.
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endchoice
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config MX51_EFIKA_COMMON
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bool
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select SOC_IMX51
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select IMX_HAVE_PLATFORM_IMX_UART
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select IMX_HAVE_PLATFORM_MXC_EHCI
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select IMX_HAVE_PLATFORM_PATA_IMX
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select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX
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select IMX_HAVE_PLATFORM_SPI_IMX
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select MXC_ULPI if USB_ULPI
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config MACH_MX51_EFIKAMX
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bool "Support MX51 Genesi Efika MX nettop"
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select LEDS_GPIO_REGISTER
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select MX51_EFIKA_COMMON
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help
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Include support for Genesi Efika MX nettop. This includes specific
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configurations for the board and its peripherals.
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config MACH_MX51_EFIKASB
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bool "Support MX51 Genesi Efika Smartbook"
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select LEDS_GPIO_REGISTER
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select MX51_EFIKA_COMMON
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help
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Include support for Genesi Efika Smartbook. This includes specific
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configurations for the board and its peripherals.
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comment "i.MX53 machines:"
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config MACH_IMX53_DT
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bool "Support i.MX53 platforms from device tree"
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select SOC_IMX53
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select USE_OF
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select MACH_MX53_ARD
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select MACH_MX53_EVK
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select MACH_MX53_LOCO
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select MACH_MX53_SMD
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help
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Include support for Freescale i.MX53 based platforms
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using the device tree for discovery
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config MACH_MX53_EVK
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bool "Support MX53 EVK platforms"
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select SOC_IMX53
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select IMX_HAVE_PLATFORM_IMX2_WDT
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select IMX_HAVE_PLATFORM_IMX_UART
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select IMX_HAVE_PLATFORM_IMX_I2C
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select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX
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select IMX_HAVE_PLATFORM_SPI_IMX
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select LEDS_GPIO_REGISTER
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help
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Include support for MX53 EVK platform. This includes specific
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configurations for the board and its peripherals.
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config MACH_MX53_SMD
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bool "Support MX53 SMD platforms"
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select SOC_IMX53
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select IMX_HAVE_PLATFORM_IMX2_WDT
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select IMX_HAVE_PLATFORM_IMX_I2C
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select IMX_HAVE_PLATFORM_IMX_UART
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select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX
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help
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Include support for MX53 SMD platform. This includes specific
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configurations for the board and its peripherals.
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config MACH_MX53_LOCO
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bool "Support MX53 LOCO platforms"
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select SOC_IMX53
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select IMX_HAVE_PLATFORM_IMX2_WDT
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select IMX_HAVE_PLATFORM_IMX_I2C
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select IMX_HAVE_PLATFORM_IMX_UART
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select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX
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select IMX_HAVE_PLATFORM_GPIO_KEYS
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select LEDS_GPIO_REGISTER
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help
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Include support for MX53 LOCO platform. This includes specific
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configurations for the board and its peripherals.
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config MACH_MX53_ARD
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bool "Support MX53 ARD platforms"
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select SOC_IMX53
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select IMX_HAVE_PLATFORM_IMX2_WDT
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select IMX_HAVE_PLATFORM_IMX_I2C
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select IMX_HAVE_PLATFORM_IMX_UART
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select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX
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select IMX_HAVE_PLATFORM_GPIO_KEYS
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help
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Include support for MX53 ARD platform. This includes specific
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configurations for the board and its peripherals.
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comment "i.MX6 family:"
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config SOC_IMX6Q
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@ -11,6 +11,8 @@ obj-$(CONFIG_SOC_IMX27) += clock-imx27.o mm-imx27.o ehci-imx27.o
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obj-$(CONFIG_SOC_IMX31) += mm-imx3.o cpu-imx31.o clock-imx31.o iomux-imx31.o ehci-imx31.o
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obj-$(CONFIG_SOC_IMX35) += mm-imx3.o cpu-imx35.o clock-imx35.o ehci-imx35.o
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obj-$(CONFIG_SOC_IMX5) += cpu-imx5.o mm-imx5.o clock-mx51-mx53.o ehci-imx5.o pm-imx5.o cpu_op-mx51.o
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# Support for CMOS sensor interface
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obj-$(CONFIG_MX1_VIDEO) += mx1-camera-fiq.o mx1-camera-fiq-ksym.o
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@ -71,3 +73,22 @@ obj-$(CONFIG_SMP) += platsmp.o
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obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o
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obj-$(CONFIG_LOCAL_TIMERS) += localtimer.o
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obj-$(CONFIG_SOC_IMX6Q) += clock-imx6q.o mach-imx6q.o pm-imx6q.o
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# i.MX5 based machines
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obj-$(CONFIG_MACH_MX51_BABBAGE) += mach-mx51_babbage.o
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obj-$(CONFIG_MACH_MX51_3DS) += mach-mx51_3ds.o
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obj-$(CONFIG_MACH_MX53_EVK) += mach-mx53_evk.o
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obj-$(CONFIG_MACH_MX53_SMD) += mach-mx53_smd.o
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obj-$(CONFIG_MACH_MX53_LOCO) += mach-mx53_loco.o
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obj-$(CONFIG_MACH_MX53_ARD) += mach-mx53_ard.o
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obj-$(CONFIG_MACH_EUKREA_CPUIMX51) += mach-cpuimx51.o
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obj-$(CONFIG_MACH_EUKREA_MBIMX51_BASEBOARD) += eukrea_mbimx51-baseboard.o
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obj-$(CONFIG_MACH_EUKREA_CPUIMX51SD) += mach-cpuimx51sd.o
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obj-$(CONFIG_MACH_EUKREA_MBIMXSD51_BASEBOARD) += eukrea_mbimxsd-baseboard.o
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obj-$(CONFIG_MX51_EFIKA_COMMON) += mx51_efika.o
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obj-$(CONFIG_MACH_MX51_EFIKAMX) += mach-mx51_efikamx.o
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obj-$(CONFIG_MACH_MX51_EFIKASB) += mach-mx51_efikasb.o
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obj-$(CONFIG_MACH_MX50_RDP) += mach-mx50_rdp.o
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obj-$(CONFIG_MACH_IMX51_DT) += imx51-dt.o
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obj-$(CONFIG_MACH_IMX53_DT) += imx53-dt.o
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@ -18,6 +18,18 @@ zreladdr-$(CONFIG_ARCH_MX3) += 0x80008000
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params_phys-$(CONFIG_ARCH_MX3) := 0x80000100
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initrd_phys-$(CONFIG_ARCH_MX3) := 0x80800000
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zreladdr-$(CONFIG_SOC_IMX50) += 0x70008000
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params_phys-$(CONFIG_SOC_IMX50) := 0x70000100
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initrd_phys-$(CONFIG_SOC_IMX50) := 0x70800000
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zreladdr-$(CONFIG_SOC_IMX51) += 0x90008000
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params_phys-$(CONFIG_SOC_IMX51) := 0x90000100
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initrd_phys-$(CONFIG_SOC_IMX51) := 0x90800000
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zreladdr-$(CONFIG_SOC_IMX53) += 0x70008000
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params_phys-$(CONFIG_SOC_IMX53) := 0x70000100
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initrd_phys-$(CONFIG_SOC_IMX53) := 0x70800000
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zreladdr-$(CONFIG_SOC_IMX6Q) += 0x10008000
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params_phys-$(CONFIG_SOC_IMX6Q) := 0x10000100
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initrd_phys-$(CONFIG_SOC_IMX6Q) := 0x10800000
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1673
arch/arm/mach-imx/clock-mx51-mx53.c
Normal file
1673
arch/arm/mach-imx/clock-mx51-mx53.c
Normal file
File diff suppressed because it is too large
Load diff
186
arch/arm/mach-imx/cpu-imx5.c
Normal file
186
arch/arm/mach-imx/cpu-imx5.c
Normal file
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@ -0,0 +1,186 @@
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/*
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* Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved.
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*
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* The code contained herein is licensed under the GNU General Public
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* License. You may obtain a copy of the GNU General Public License
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* Version 2 or later at the following locations:
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*
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* http://www.opensource.org/licenses/gpl-license.html
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* http://www.gnu.org/copyleft/gpl.html
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*
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* This file contains the CPU initialization code.
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*/
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#include <linux/types.h>
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/module.h>
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#include <mach/hardware.h>
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#include <asm/io.h>
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static int mx5_cpu_rev = -1;
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#define IIM_SREV 0x24
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#define MX50_HW_ADADIG_DIGPROG 0xB0
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static int get_mx51_srev(void)
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{
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void __iomem *iim_base = MX51_IO_ADDRESS(MX51_IIM_BASE_ADDR);
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u32 rev = readl(iim_base + IIM_SREV) & 0xff;
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switch (rev) {
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case 0x0:
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return IMX_CHIP_REVISION_2_0;
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case 0x10:
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return IMX_CHIP_REVISION_3_0;
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default:
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return IMX_CHIP_REVISION_UNKNOWN;
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}
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}
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/*
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* Returns:
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* the silicon revision of the cpu
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* -EINVAL - not a mx51
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*/
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int mx51_revision(void)
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{
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if (!cpu_is_mx51())
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return -EINVAL;
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if (mx5_cpu_rev == -1)
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mx5_cpu_rev = get_mx51_srev();
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return mx5_cpu_rev;
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}
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EXPORT_SYMBOL(mx51_revision);
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#ifdef CONFIG_NEON
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/*
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* All versions of the silicon before Rev. 3 have broken NEON implementations.
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* Dependent on link order - so the assumption is that vfp_init is called
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* before us.
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*/
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static int __init mx51_neon_fixup(void)
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{
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if (!cpu_is_mx51())
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return 0;
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if (mx51_revision() < IMX_CHIP_REVISION_3_0 && (elf_hwcap & HWCAP_NEON)) {
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elf_hwcap &= ~HWCAP_NEON;
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pr_info("Turning off NEON support, detected broken NEON implementation\n");
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}
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return 0;
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}
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late_initcall(mx51_neon_fixup);
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#endif
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static int get_mx53_srev(void)
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{
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void __iomem *iim_base = MX51_IO_ADDRESS(MX53_IIM_BASE_ADDR);
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u32 rev = readl(iim_base + IIM_SREV) & 0xff;
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switch (rev) {
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case 0x0:
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return IMX_CHIP_REVISION_1_0;
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case 0x2:
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return IMX_CHIP_REVISION_2_0;
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case 0x3:
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return IMX_CHIP_REVISION_2_1;
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default:
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return IMX_CHIP_REVISION_UNKNOWN;
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}
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}
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/*
|
||||
* Returns:
|
||||
* the silicon revision of the cpu
|
||||
* -EINVAL - not a mx53
|
||||
*/
|
||||
int mx53_revision(void)
|
||||
{
|
||||
if (!cpu_is_mx53())
|
||||
return -EINVAL;
|
||||
|
||||
if (mx5_cpu_rev == -1)
|
||||
mx5_cpu_rev = get_mx53_srev();
|
||||
|
||||
return mx5_cpu_rev;
|
||||
}
|
||||
EXPORT_SYMBOL(mx53_revision);
|
||||
|
||||
static int get_mx50_srev(void)
|
||||
{
|
||||
void __iomem *anatop = ioremap(MX50_ANATOP_BASE_ADDR, SZ_8K);
|
||||
u32 rev;
|
||||
|
||||
if (!anatop) {
|
||||
mx5_cpu_rev = -EINVAL;
|
||||
return 0;
|
||||
}
|
||||
|
||||
rev = readl(anatop + MX50_HW_ADADIG_DIGPROG);
|
||||
rev &= 0xff;
|
||||
|
||||
iounmap(anatop);
|
||||
if (rev == 0x0)
|
||||
return IMX_CHIP_REVISION_1_0;
|
||||
else if (rev == 0x1)
|
||||
return IMX_CHIP_REVISION_1_1;
|
||||
return 0;
|
||||
}
|
||||
|
||||
/*
|
||||
* Returns:
|
||||
* the silicon revision of the cpu
|
||||
* -EINVAL - not a mx50
|
||||
*/
|
||||
int mx50_revision(void)
|
||||
{
|
||||
if (!cpu_is_mx50())
|
||||
return -EINVAL;
|
||||
|
||||
if (mx5_cpu_rev == -1)
|
||||
mx5_cpu_rev = get_mx50_srev();
|
||||
|
||||
return mx5_cpu_rev;
|
||||
}
|
||||
EXPORT_SYMBOL(mx50_revision);
|
||||
|
||||
static int __init post_cpu_init(void)
|
||||
{
|
||||
unsigned int reg;
|
||||
void __iomem *base;
|
||||
|
||||
if (cpu_is_mx51() || cpu_is_mx53()) {
|
||||
if (cpu_is_mx51())
|
||||
base = MX51_IO_ADDRESS(MX51_AIPS1_BASE_ADDR);
|
||||
else
|
||||
base = MX53_IO_ADDRESS(MX53_AIPS1_BASE_ADDR);
|
||||
|
||||
__raw_writel(0x0, base + 0x40);
|
||||
__raw_writel(0x0, base + 0x44);
|
||||
__raw_writel(0x0, base + 0x48);
|
||||
__raw_writel(0x0, base + 0x4C);
|
||||
reg = __raw_readl(base + 0x50) & 0x00FFFFFF;
|
||||
__raw_writel(reg, base + 0x50);
|
||||
|
||||
if (cpu_is_mx51())
|
||||
base = MX51_IO_ADDRESS(MX51_AIPS2_BASE_ADDR);
|
||||
else
|
||||
base = MX53_IO_ADDRESS(MX53_AIPS2_BASE_ADDR);
|
||||
|
||||
__raw_writel(0x0, base + 0x40);
|
||||
__raw_writel(0x0, base + 0x44);
|
||||
__raw_writel(0x0, base + 0x48);
|
||||
__raw_writel(0x0, base + 0x4C);
|
||||
reg = __raw_readl(base + 0x50) & 0x00FFFFFF;
|
||||
__raw_writel(reg, base + 0x50);
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
postcore_initcall(post_cpu_init);
|
||||
29
arch/arm/mach-imx/cpu_op-mx51.c
Normal file
29
arch/arm/mach-imx/cpu_op-mx51.c
Normal file
|
|
@ -0,0 +1,29 @@
|
|||
/*
|
||||
* Copyright (C) 2010 Freescale Semiconductor, Inc. All Rights Reserved.
|
||||
*/
|
||||
|
||||
/*
|
||||
* The code contained herein is licensed under the GNU General Public
|
||||
* License. You may obtain a copy of the GNU General Public License
|
||||
* Version 2 or later at the following locations:
|
||||
*
|
||||
* http://www.opensource.org/licenses/gpl-license.html
|
||||
* http://www.gnu.org/copyleft/gpl.html
|
||||
*/
|
||||
|
||||
#include <linux/types.h>
|
||||
#include <mach/hardware.h>
|
||||
#include <linux/kernel.h>
|
||||
|
||||
static struct cpu_op mx51_cpu_op[] = {
|
||||
{
|
||||
.cpu_rate = 160000000,},
|
||||
{
|
||||
.cpu_rate = 800000000,},
|
||||
};
|
||||
|
||||
struct cpu_op *mx51_get_cpu_op(int *op)
|
||||
{
|
||||
*op = ARRAY_SIZE(mx51_cpu_op);
|
||||
return mx51_cpu_op;
|
||||
}
|
||||
14
arch/arm/mach-imx/cpu_op-mx51.h
Normal file
14
arch/arm/mach-imx/cpu_op-mx51.h
Normal file
|
|
@ -0,0 +1,14 @@
|
|||
/*
|
||||
* Copyright (C) 2010 Freescale Semiconductor, Inc. All Rights Reserved.
|
||||
*/
|
||||
|
||||
/*
|
||||
* The code contained herein is licensed under the GNU General Public
|
||||
* License. You may obtain a copy of the GNU General Public License
|
||||
* Version 2 or later at the following locations:
|
||||
*
|
||||
* http://www.opensource.org/licenses/gpl-license.html
|
||||
* http://www.gnu.org/copyleft/gpl.html
|
||||
*/
|
||||
|
||||
extern struct cpu_op *mx51_get_cpu_op(int *op);
|
||||
600
arch/arm/mach-imx/crm-regs-imx5.h
Normal file
600
arch/arm/mach-imx/crm-regs-imx5.h
Normal file
|
|
@ -0,0 +1,600 @@
|
|||
/*
|
||||
* Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved.
|
||||
*
|
||||
* The code contained herein is licensed under the GNU General Public
|
||||
* License. You may obtain a copy of the GNU General Public License
|
||||
* Version 2 or later at the following locations:
|
||||
*
|
||||
* http://www.opensource.org/licenses/gpl-license.html
|
||||
* http://www.gnu.org/copyleft/gpl.html
|
||||
*/
|
||||
#ifndef __ARCH_ARM_MACH_MX51_CRM_REGS_H__
|
||||
#define __ARCH_ARM_MACH_MX51_CRM_REGS_H__
|
||||
|
||||
#define MX51_CCM_BASE MX51_IO_ADDRESS(MX51_CCM_BASE_ADDR)
|
||||
#define MX51_DPLL1_BASE MX51_IO_ADDRESS(MX51_PLL1_BASE_ADDR)
|
||||
#define MX51_DPLL2_BASE MX51_IO_ADDRESS(MX51_PLL2_BASE_ADDR)
|
||||
#define MX51_DPLL3_BASE MX51_IO_ADDRESS(MX51_PLL3_BASE_ADDR)
|
||||
#define MX51_CORTEXA8_BASE MX51_IO_ADDRESS(MX51_ARM_BASE_ADDR)
|
||||
#define MX51_GPC_BASE MX51_IO_ADDRESS(MX51_GPC_BASE_ADDR)
|
||||
|
||||
/*MX53*/
|
||||
#define MX53_CCM_BASE MX53_IO_ADDRESS(MX53_CCM_BASE_ADDR)
|
||||
#define MX53_DPLL1_BASE MX53_IO_ADDRESS(MX53_PLL1_BASE_ADDR)
|
||||
#define MX53_DPLL2_BASE MX53_IO_ADDRESS(MX53_PLL2_BASE_ADDR)
|
||||
#define MX53_DPLL3_BASE MX53_IO_ADDRESS(MX53_PLL3_BASE_ADDR)
|
||||
#define MX53_DPLL4_BASE MX53_IO_ADDRESS(MX53_PLL3_BASE_ADDR)
|
||||
|
||||
/* PLL Register Offsets */
|
||||
#define MXC_PLL_DP_CTL 0x00
|
||||
#define MXC_PLL_DP_CONFIG 0x04
|
||||
#define MXC_PLL_DP_OP 0x08
|
||||
#define MXC_PLL_DP_MFD 0x0C
|
||||
#define MXC_PLL_DP_MFN 0x10
|
||||
#define MXC_PLL_DP_MFNMINUS 0x14
|
||||
#define MXC_PLL_DP_MFNPLUS 0x18
|
||||
#define MXC_PLL_DP_HFS_OP 0x1C
|
||||
#define MXC_PLL_DP_HFS_MFD 0x20
|
||||
#define MXC_PLL_DP_HFS_MFN 0x24
|
||||
#define MXC_PLL_DP_MFN_TOGC 0x28
|
||||
#define MXC_PLL_DP_DESTAT 0x2c
|
||||
|
||||
/* PLL Register Bit definitions */
|
||||
#define MXC_PLL_DP_CTL_MUL_CTRL 0x2000
|
||||
#define MXC_PLL_DP_CTL_DPDCK0_2_EN 0x1000
|
||||
#define MXC_PLL_DP_CTL_DPDCK0_2_OFFSET 12
|
||||
#define MXC_PLL_DP_CTL_ADE 0x800
|
||||
#define MXC_PLL_DP_CTL_REF_CLK_DIV 0x400
|
||||
#define MXC_PLL_DP_CTL_REF_CLK_SEL_MASK (3 << 8)
|
||||
#define MXC_PLL_DP_CTL_REF_CLK_SEL_OFFSET 8
|
||||
#define MXC_PLL_DP_CTL_HFSM 0x80
|
||||
#define MXC_PLL_DP_CTL_PRE 0x40
|
||||
#define MXC_PLL_DP_CTL_UPEN 0x20
|
||||
#define MXC_PLL_DP_CTL_RST 0x10
|
||||
#define MXC_PLL_DP_CTL_RCP 0x8
|
||||
#define MXC_PLL_DP_CTL_PLM 0x4
|
||||
#define MXC_PLL_DP_CTL_BRM0 0x2
|
||||
#define MXC_PLL_DP_CTL_LRF 0x1
|
||||
|
||||
#define MXC_PLL_DP_CONFIG_BIST 0x8
|
||||
#define MXC_PLL_DP_CONFIG_SJC_CE 0x4
|
||||
#define MXC_PLL_DP_CONFIG_AREN 0x2
|
||||
#define MXC_PLL_DP_CONFIG_LDREQ 0x1
|
||||
|
||||
#define MXC_PLL_DP_OP_MFI_OFFSET 4
|
||||
#define MXC_PLL_DP_OP_MFI_MASK (0xF << 4)
|
||||
#define MXC_PLL_DP_OP_PDF_OFFSET 0
|
||||
#define MXC_PLL_DP_OP_PDF_MASK 0xF
|
||||
|
||||
#define MXC_PLL_DP_MFD_OFFSET 0
|
||||
#define MXC_PLL_DP_MFD_MASK 0x07FFFFFF
|
||||
|
||||
#define MXC_PLL_DP_MFN_OFFSET 0x0
|
||||
#define MXC_PLL_DP_MFN_MASK 0x07FFFFFF
|
||||
|
||||
#define MXC_PLL_DP_MFN_TOGC_TOG_DIS (1 << 17)
|
||||
#define MXC_PLL_DP_MFN_TOGC_TOG_EN (1 << 16)
|
||||
#define MXC_PLL_DP_MFN_TOGC_CNT_OFFSET 0x0
|
||||
#define MXC_PLL_DP_MFN_TOGC_CNT_MASK 0xFFFF
|
||||
|
||||
#define MXC_PLL_DP_DESTAT_TOG_SEL (1 << 31)
|
||||
#define MXC_PLL_DP_DESTAT_MFN 0x07FFFFFF
|
||||
|
||||
/* Register addresses of CCM*/
|
||||
#define MXC_CCM_CCR (MX51_CCM_BASE + 0x00)
|
||||
#define MXC_CCM_CCDR (MX51_CCM_BASE + 0x04)
|
||||
#define MXC_CCM_CSR (MX51_CCM_BASE + 0x08)
|
||||
#define MXC_CCM_CCSR (MX51_CCM_BASE + 0x0C)
|
||||
#define MXC_CCM_CACRR (MX51_CCM_BASE + 0x10)
|
||||
#define MXC_CCM_CBCDR (MX51_CCM_BASE + 0x14)
|
||||
#define MXC_CCM_CBCMR (MX51_CCM_BASE + 0x18)
|
||||
#define MXC_CCM_CSCMR1 (MX51_CCM_BASE + 0x1C)
|
||||
#define MXC_CCM_CSCMR2 (MX51_CCM_BASE + 0x20)
|
||||
#define MXC_CCM_CSCDR1 (MX51_CCM_BASE + 0x24)
|
||||
#define MXC_CCM_CS1CDR (MX51_CCM_BASE + 0x28)
|
||||
#define MXC_CCM_CS2CDR (MX51_CCM_BASE + 0x2C)
|
||||
#define MXC_CCM_CDCDR (MX51_CCM_BASE + 0x30)
|
||||
#define MXC_CCM_CHSCDR (MX51_CCM_BASE + 0x34)
|
||||
#define MXC_CCM_CSCDR2 (MX51_CCM_BASE + 0x38)
|
||||
#define MXC_CCM_CSCDR3 (MX51_CCM_BASE + 0x3C)
|
||||
#define MXC_CCM_CSCDR4 (MX51_CCM_BASE + 0x40)
|
||||
#define MXC_CCM_CWDR (MX51_CCM_BASE + 0x44)
|
||||
#define MXC_CCM_CDHIPR (MX51_CCM_BASE + 0x48)
|
||||
#define MXC_CCM_CDCR (MX51_CCM_BASE + 0x4C)
|
||||
#define MXC_CCM_CTOR (MX51_CCM_BASE + 0x50)
|
||||
#define MXC_CCM_CLPCR (MX51_CCM_BASE + 0x54)
|
||||
#define MXC_CCM_CISR (MX51_CCM_BASE + 0x58)
|
||||
#define MXC_CCM_CIMR (MX51_CCM_BASE + 0x5C)
|
||||
#define MXC_CCM_CCOSR (MX51_CCM_BASE + 0x60)
|
||||
#define MXC_CCM_CGPR (MX51_CCM_BASE + 0x64)
|
||||
#define MXC_CCM_CCGR0 (MX51_CCM_BASE + 0x68)
|
||||
#define MXC_CCM_CCGR1 (MX51_CCM_BASE + 0x6C)
|
||||
#define MXC_CCM_CCGR2 (MX51_CCM_BASE + 0x70)
|
||||
#define MXC_CCM_CCGR3 (MX51_CCM_BASE + 0x74)
|
||||
#define MXC_CCM_CCGR4 (MX51_CCM_BASE + 0x78)
|
||||
#define MXC_CCM_CCGR5 (MX51_CCM_BASE + 0x7C)
|
||||
#define MXC_CCM_CCGR6 (MX51_CCM_BASE + 0x80)
|
||||
#define MXC_CCM_CCGR7 (MX51_CCM_BASE + 0x84)
|
||||
|
||||
#define MXC_CCM_CMEOR (MX51_CCM_BASE + 0x84)
|
||||
|
||||
/* Define the bits in register CCR */
|
||||
#define MXC_CCM_CCR_COSC_EN (1 << 12)
|
||||
#define MXC_CCM_CCR_FPM_MULT_MASK (1 << 11)
|
||||
#define MXC_CCM_CCR_CAMP2_EN (1 << 10)
|
||||
#define MXC_CCM_CCR_CAMP1_EN (1 << 9)
|
||||
#define MXC_CCM_CCR_FPM_EN (1 << 8)
|
||||
#define MXC_CCM_CCR_OSCNT_OFFSET (0)
|
||||
#define MXC_CCM_CCR_OSCNT_MASK (0xFF)
|
||||
|
||||
/* Define the bits in register CCDR */
|
||||
#define MXC_CCM_CCDR_HSC_HS_MASK (0x1 << 18)
|
||||
#define MXC_CCM_CCDR_IPU_HS_MASK (0x1 << 17)
|
||||
#define MXC_CCM_CCDR_EMI_HS_MASK (0x1 << 16)
|
||||
|
||||
/* Define the bits in register CSR */
|
||||
#define MXC_CCM_CSR_COSR_READY (1 << 5)
|
||||
#define MXC_CCM_CSR_LVS_VALUE (1 << 4)
|
||||
#define MXC_CCM_CSR_CAMP2_READY (1 << 3)
|
||||
#define MXC_CCM_CSR_CAMP1_READY (1 << 2)
|
||||
#define MXC_CCM_CSR_FPM_READY (1 << 1)
|
||||
#define MXC_CCM_CSR_REF_EN_B (1 << 0)
|
||||
|
||||
/* Define the bits in register CCSR */
|
||||
#define MXC_CCM_CCSR_LP_APM_SEL (0x1 << 9)
|
||||
#define MXC_CCM_CCSR_STEP_SEL_OFFSET (7)
|
||||
#define MXC_CCM_CCSR_STEP_SEL_MASK (0x3 << 7)
|
||||
#define MXC_CCM_CCSR_STEP_SEL_LP_APM 0
|
||||
#define MXC_CCM_CCSR_STEP_SEL_PLL1_BYPASS 1 /* Only when JTAG connected? */
|
||||
#define MXC_CCM_CCSR_STEP_SEL_PLL2_DIVIDED 2
|
||||
#define MXC_CCM_CCSR_STEP_SEL_PLL3_DIVIDED 3
|
||||
#define MXC_CCM_CCSR_PLL2_PODF_OFFSET (5)
|
||||
#define MXC_CCM_CCSR_PLL2_PODF_MASK (0x3 << 5)
|
||||
#define MXC_CCM_CCSR_PLL3_PODF_OFFSET (3)
|
||||
#define MXC_CCM_CCSR_PLL3_PODF_MASK (0x3 << 3)
|
||||
#define MXC_CCM_CCSR_PLL1_SW_CLK_SEL (1 << 2) /* 0: pll1_main_clk,
|
||||
1: step_clk */
|
||||
#define MXC_CCM_CCSR_PLL2_SW_CLK_SEL (1 << 1)
|
||||
#define MXC_CCM_CCSR_PLL3_SW_CLK_SEL (1 << 0)
|
||||
|
||||
/* Define the bits in register CACRR */
|
||||
#define MXC_CCM_CACRR_ARM_PODF_OFFSET (0)
|
||||
#define MXC_CCM_CACRR_ARM_PODF_MASK (0x7)
|
||||
|
||||
/* Define the bits in register CBCDR */
|
||||
#define MXC_CCM_CBCDR_EMI_CLK_SEL (0x1 << 26)
|
||||
#define MXC_CCM_CBCDR_PERIPH_CLK_SEL (0x1 << 25)
|
||||
#define MXC_CCM_CBCDR_DDR_HF_SEL_OFFSET (30)
|
||||
#define MXC_CCM_CBCDR_DDR_HF_SEL (0x1 << 30)
|
||||
#define MXC_CCM_CBCDR_DDR_PODF_OFFSET (27)
|
||||
#define MXC_CCM_CBCDR_DDR_PODF_MASK (0x7 << 27)
|
||||
#define MXC_CCM_CBCDR_EMI_PODF_OFFSET (22)
|
||||
#define MXC_CCM_CBCDR_EMI_PODF_MASK (0x7 << 22)
|
||||
#define MXC_CCM_CBCDR_AXI_B_PODF_OFFSET (19)
|
||||
#define MXC_CCM_CBCDR_AXI_B_PODF_MASK (0x7 << 19)
|
||||
#define MXC_CCM_CBCDR_AXI_A_PODF_OFFSET (16)
|
||||
#define MXC_CCM_CBCDR_AXI_A_PODF_MASK (0x7 << 16)
|
||||
#define MXC_CCM_CBCDR_NFC_PODF_OFFSET (13)
|
||||
#define MXC_CCM_CBCDR_NFC_PODF_MASK (0x7 << 13)
|
||||
#define MXC_CCM_CBCDR_AHB_PODF_OFFSET (10)
|
||||
#define MXC_CCM_CBCDR_AHB_PODF_MASK (0x7 << 10)
|
||||
#define MXC_CCM_CBCDR_IPG_PODF_OFFSET (8)
|
||||
#define MXC_CCM_CBCDR_IPG_PODF_MASK (0x3 << 8)
|
||||
#define MXC_CCM_CBCDR_PERCLK_PRED1_OFFSET (6)
|
||||
#define MXC_CCM_CBCDR_PERCLK_PRED1_MASK (0x3 << 6)
|
||||
#define MXC_CCM_CBCDR_PERCLK_PRED2_OFFSET (3)
|
||||
#define MXC_CCM_CBCDR_PERCLK_PRED2_MASK (0x7 << 3)
|
||||
#define MXC_CCM_CBCDR_PERCLK_PODF_OFFSET (0)
|
||||
#define MXC_CCM_CBCDR_PERCLK_PODF_MASK (0x7)
|
||||
|
||||
/* Define the bits in register CBCMR */
|
||||
#define MXC_CCM_CBCMR_VPU_AXI_CLK_SEL_OFFSET (14)
|
||||
#define MXC_CCM_CBCMR_VPU_AXI_CLK_SEL_MASK (0x3 << 14)
|
||||
#define MXC_CCM_CBCMR_PERIPH_CLK_SEL_OFFSET (12)
|
||||
#define MXC_CCM_CBCMR_PERIPH_CLK_SEL_MASK (0x3 << 12)
|
||||
#define MXC_CCM_CBCMR_DDR_CLK_SEL_OFFSET (10)
|
||||
#define MXC_CCM_CBCMR_DDR_CLK_SEL_MASK (0x3 << 10)
|
||||
#define MXC_CCM_CBCMR_ARM_AXI_CLK_SEL_OFFSET (8)
|
||||
#define MXC_CCM_CBCMR_ARM_AXI_CLK_SEL_MASK (0x3 << 8)
|
||||
#define MXC_CCM_CBCMR_IPU_HSP_CLK_SEL_OFFSET (6)
|
||||
#define MXC_CCM_CBCMR_IPU_HSP_CLK_SEL_MASK (0x3 << 6)
|
||||
#define MXC_CCM_CBCMR_GPU_CLK_SEL_OFFSET (4)
|
||||
#define MXC_CCM_CBCMR_GPU_CLK_SEL_MASK (0x3 << 4)
|
||||
#define MXC_CCM_CBCMR_GPU2D_CLK_SEL_OFFSET (14)
|
||||
#define MXC_CCM_CBCMR_GPU2D_CLK_SEL_MASK (0x3 << 14)
|
||||
#define MXC_CCM_CBCMR_PERCLK_LP_APM_CLK_SEL (0x1 << 1)
|
||||
#define MXC_CCM_CBCMR_PERCLK_IPG_CLK_SEL (0x1 << 0)
|
||||
|
||||
/* Define the bits in register CSCMR1 */
|
||||
#define MXC_CCM_CSCMR1_SSI_EXT2_CLK_SEL_OFFSET (30)
|
||||
#define MXC_CCM_CSCMR1_SSI_EXT2_CLK_SEL_MASK (0x3 << 30)
|
||||
#define MXC_CCM_CSCMR1_SSI_EXT1_CLK_SEL_OFFSET (28)
|
||||
#define MXC_CCM_CSCMR1_SSI_EXT1_CLK_SEL_MASK (0x3 << 28)
|
||||
#define MXC_CCM_CSCMR1_USB_PHY_CLK_SEL_OFFSET (26)
|
||||
#define MXC_CCM_CSCMR1_USB_PHY_CLK_SEL (0x1 << 26)
|
||||
#define MXC_CCM_CSCMR1_UART_CLK_SEL_OFFSET (24)
|
||||
#define MXC_CCM_CSCMR1_UART_CLK_SEL_MASK (0x3 << 24)
|
||||
#define MXC_CCM_CSCMR1_USBOH3_CLK_SEL_OFFSET (22)
|
||||
#define MXC_CCM_CSCMR1_USBOH3_CLK_SEL_MASK (0x3 << 22)
|
||||
#define MXC_CCM_CSCMR1_ESDHC1_MSHC1_CLK_SEL_OFFSET (20)
|
||||
#define MXC_CCM_CSCMR1_ESDHC1_MSHC1_CLK_SEL_MASK (0x3 << 20)
|
||||
#define MXC_CCM_CSCMR1_ESDHC3_CLK_SEL (0x1 << 19)
|
||||
#define MXC_CCM_CSCMR1_ESDHC2_MSHC2_MX53_CLK_SEL (0x1 << 19)
|
||||
#define MXC_CCM_CSCMR1_ESDHC4_CLK_SEL (0x1 << 18)
|
||||
#define MXC_CCM_CSCMR1_ESDHC2_MSHC2_CLK_SEL_OFFSET (16)
|
||||
#define MXC_CCM_CSCMR1_ESDHC2_MSHC2_CLK_SEL_MASK (0x3 << 16)
|
||||
#define MXC_CCM_CSCMR1_ESDHC3_MX53_CLK_SEL_OFFSET (16)
|
||||
#define MXC_CCM_CSCMR1_ESDHC3_MX53_CLK_SEL_MASK (0x3 << 16)
|
||||
#define MXC_CCM_CSCMR1_SSI1_CLK_SEL_OFFSET (14)
|
||||
#define MXC_CCM_CSCMR1_SSI1_CLK_SEL_MASK (0x3 << 14)
|
||||
#define MXC_CCM_CSCMR1_SSI2_CLK_SEL_OFFSET (12)
|
||||
#define MXC_CCM_CSCMR1_SSI2_CLK_SEL_MASK (0x3 << 12)
|
||||
#define MXC_CCM_CSCMR1_SSI3_CLK_SEL (0x1 << 11)
|
||||
#define MXC_CCM_CSCMR1_VPU_RCLK_SEL (0x1 << 10)
|
||||
#define MXC_CCM_CSCMR1_SSI_APM_CLK_SEL_OFFSET (8)
|
||||
#define MXC_CCM_CSCMR1_SSI_APM_CLK_SEL_MASK (0x3 << 8)
|
||||
#define MXC_CCM_CSCMR1_TVE_CLK_SEL (0x1 << 7)
|
||||
#define MXC_CCM_CSCMR1_TVE_EXT_CLK_SEL (0x1 << 6)
|
||||
#define MXC_CCM_CSCMR1_CSPI_CLK_SEL_OFFSET (4)
|
||||
#define MXC_CCM_CSCMR1_CSPI_CLK_SEL_MASK (0x3 << 4)
|
||||
#define MXC_CCM_CSCMR1_SPDIF_CLK_SEL_OFFSET (2)
|
||||
#define MXC_CCM_CSCMR1_SPDIF_CLK_SEL_MASK (0x3 << 2)
|
||||
#define MXC_CCM_CSCMR1_SSI_EXT2_COM_CLK_SEL (0x1 << 1)
|
||||
#define MXC_CCM_CSCMR1_SSI_EXT1_COM_CLK_SEL (0x1)
|
||||
|
||||
/* Define the bits in register CSCMR2 */
|
||||
#define MXC_CCM_CSCMR2_DI_CLK_SEL_OFFSET(n) (26+n*3)
|
||||
#define MXC_CCM_CSCMR2_DI_CLK_SEL_MASK(n) (0x7 << (26+n*3))
|
||||
#define MXC_CCM_CSCMR2_CSI_MCLK2_CLK_SEL_OFFSET (24)
|
||||
#define MXC_CCM_CSCMR2_CSI_MCLK2_CLK_SEL_MASK (0x3 << 24)
|
||||
#define MXC_CCM_CSCMR2_CSI_MCLK1_CLK_SEL_OFFSET (22)
|
||||
#define MXC_CCM_CSCMR2_CSI_MCLK1_CLK_SEL_MASK (0x3 << 22)
|
||||
#define MXC_CCM_CSCMR2_ESC_CLK_SEL_OFFSET (20)
|
||||
#define MXC_CCM_CSCMR2_ESC_CLK_SEL_MASK (0x3 << 20)
|
||||
#define MXC_CCM_CSCMR2_HSC2_CLK_SEL_OFFSET (18)
|
||||
#define MXC_CCM_CSCMR2_HSC2_CLK_SEL_MASK (0x3 << 18)
|
||||
#define MXC_CCM_CSCMR2_HSC1_CLK_SEL_OFFSET (16)
|
||||
#define MXC_CCM_CSCMR2_HSC1_CLK_SEL_MASK (0x3 << 16)
|
||||
#define MXC_CCM_CSCMR2_HSI2C_CLK_SEL_OFFSET (14)
|
||||
#define MXC_CCM_CSCMR2_HSI2C_CLK_SEL_MASK (0x3 << 14)
|
||||
#define MXC_CCM_CSCMR2_FIRI_CLK_SEL_OFFSET (12)
|
||||
#define MXC_CCM_CSCMR2_FIRI_CLK_SEL_MASK (0x3 << 12)
|
||||
#define MXC_CCM_CSCMR2_SIM_CLK_SEL_OFFSET (10)
|
||||
#define MXC_CCM_CSCMR2_SIM_CLK_SEL_MASK (0x3 << 10)
|
||||
#define MXC_CCM_CSCMR2_SLIMBUS_COM (0x1 << 9)
|
||||
#define MXC_CCM_CSCMR2_SLIMBUS_CLK_SEL_OFFSET (6)
|
||||
#define MXC_CCM_CSCMR2_SLIMBUS_CLK_SEL_MASK (0x7 << 6)
|
||||
#define MXC_CCM_CSCMR2_SPDIF1_COM (1 << 5)
|
||||
#define MXC_CCM_CSCMR2_SPDIF0_COM (1 << 4)
|
||||
#define MXC_CCM_CSCMR2_SPDIF1_CLK_SEL_OFFSET (2)
|
||||
#define MXC_CCM_CSCMR2_SPDIF1_CLK_SEL_MASK (0x3 << 2)
|
||||
#define MXC_CCM_CSCMR2_SPDIF0_CLK_SEL_OFFSET (0)
|
||||
#define MXC_CCM_CSCMR2_SPDIF0_CLK_SEL_MASK (0x3)
|
||||
|
||||
/* Define the bits in register CSCDR1 */
|
||||
#define MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PRED_OFFSET (22)
|
||||
#define MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PRED_MASK (0x7 << 22)
|
||||
#define MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PODF_OFFSET (19)
|
||||
#define MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PODF_MASK (0x7 << 19)
|
||||
#define MXC_CCM_CSCDR1_ESDHC3_MX53_CLK_PRED_OFFSET (22)
|
||||
#define MXC_CCM_CSCDR1_ESDHC3_MX53_CLK_PRED_MASK (0x7 << 22)
|
||||
#define MXC_CCM_CSCDR1_ESDHC3_MX53_CLK_PODF_OFFSET (19)
|
||||
#define MXC_CCM_CSCDR1_ESDHC3_MX53_CLK_PODF_MASK (0x7 << 19)
|
||||
#define MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PRED_OFFSET (16)
|
||||
#define MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PRED_MASK (0x7 << 16)
|
||||
#define MXC_CCM_CSCDR1_PGC_CLK_PODF_OFFSET (14)
|
||||
#define MXC_CCM_CSCDR1_PGC_CLK_PODF_MASK (0x3 << 14)
|
||||
#define MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PODF_OFFSET (11)
|
||||
#define MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PODF_MASK (0x7 << 11)
|
||||
#define MXC_CCM_CSCDR1_USBOH3_CLK_PRED_OFFSET (8)
|
||||
#define MXC_CCM_CSCDR1_USBOH3_CLK_PRED_MASK (0x7 << 8)
|
||||
#define MXC_CCM_CSCDR1_USBOH3_CLK_PODF_OFFSET (6)
|
||||
#define MXC_CCM_CSCDR1_USBOH3_CLK_PODF_MASK (0x3 << 6)
|
||||
#define MXC_CCM_CSCDR1_UART_CLK_PRED_OFFSET (3)
|
||||
#define MXC_CCM_CSCDR1_UART_CLK_PRED_MASK (0x7 << 3)
|
||||
#define MXC_CCM_CSCDR1_UART_CLK_PODF_OFFSET (0)
|
||||
#define MXC_CCM_CSCDR1_UART_CLK_PODF_MASK (0x7)
|
||||
|
||||
/* Define the bits in register CS1CDR and CS2CDR */
|
||||
#define MXC_CCM_CS1CDR_SSI_EXT1_CLK_PRED_OFFSET (22)
|
||||
#define MXC_CCM_CS1CDR_SSI_EXT1_CLK_PRED_MASK (0x7 << 22)
|
||||
#define MXC_CCM_CS1CDR_SSI_EXT1_CLK_PODF_OFFSET (16)
|
||||
#define MXC_CCM_CS1CDR_SSI_EXT1_CLK_PODF_MASK (0x3F << 16)
|
||||
#define MXC_CCM_CS1CDR_SSI1_CLK_PRED_OFFSET (6)
|
||||
#define MXC_CCM_CS1CDR_SSI1_CLK_PRED_MASK (0x7 << 6)
|
||||
#define MXC_CCM_CS1CDR_SSI1_CLK_PODF_OFFSET (0)
|
||||
#define MXC_CCM_CS1CDR_SSI1_CLK_PODF_MASK (0x3F)
|
||||
|
||||
#define MXC_CCM_CS2CDR_SSI_EXT2_CLK_PRED_OFFSET (22)
|
||||
#define MXC_CCM_CS2CDR_SSI_EXT2_CLK_PRED_MASK (0x7 << 22)
|
||||
#define MXC_CCM_CS2CDR_SSI_EXT2_CLK_PODF_OFFSET (16)
|
||||
#define MXC_CCM_CS2CDR_SSI_EXT2_CLK_PODF_MASK (0x3F << 16)
|
||||
#define MXC_CCM_CS2CDR_SSI2_CLK_PRED_OFFSET (6)
|
||||
#define MXC_CCM_CS2CDR_SSI2_CLK_PRED_MASK (0x7 << 6)
|
||||
#define MXC_CCM_CS2CDR_SSI2_CLK_PODF_OFFSET (0)
|
||||
#define MXC_CCM_CS2CDR_SSI2_CLK_PODF_MASK (0x3F)
|
||||
|
||||
/* Define the bits in register CDCDR */
|
||||
#define MXC_CCM_CDCDR_TVE_CLK_PRED_OFFSET (28)
|
||||
#define MXC_CCM_CDCDR_TVE_CLK_PRED_MASK (0x7 << 28)
|
||||
#define MXC_CCM_CDCDR_SPDIF0_CLK_PRED_OFFSET (25)
|
||||
#define MXC_CCM_CDCDR_SPDIF0_CLK_PRED_MASK (0x7 << 25)
|
||||
#define MXC_CCM_CDCDR_SPDIF0_CLK_PODF_OFFSET (19)
|
||||
#define MXC_CCM_CDCDR_SPDIF0_CLK_PODF_MASK (0x3F << 19)
|
||||
#define MXC_CCM_CDCDR_SPDIF1_CLK_PRED_OFFSET (16)
|
||||
#define MXC_CCM_CDCDR_SPDIF1_CLK_PRED_MASK (0x7 << 16)
|
||||
#define MXC_CCM_CDCDR_SPDIF1_CLK_PODF_OFFSET (9)
|
||||
#define MXC_CCM_CDCDR_SPDIF1_CLK_PODF_MASK (0x3F << 9)
|
||||
#define MXC_CCM_CDCDR_DI_CLK_PRED_OFFSET (6)
|
||||
#define MXC_CCM_CDCDR_DI_CLK_PRED_MASK (0x7 << 6)
|
||||
#define MXC_CCM_CDCDR_USB_PHY_PRED_OFFSET (3)
|
||||
#define MXC_CCM_CDCDR_USB_PHY_PRED_MASK (0x7 << 3)
|
||||
#define MXC_CCM_CDCDR_USB_PHY_PODF_OFFSET (0)
|
||||
#define MXC_CCM_CDCDR_USB_PHY_PODF_MASK (0x7)
|
||||
|
||||
/* Define the bits in register CHSCCDR */
|
||||
#define MXC_CCM_CHSCCDR_ESC_CLK_PRED_OFFSET (12)
|
||||
#define MXC_CCM_CHSCCDR_ESC_CLK_PRED_MASK (0x7 << 12)
|
||||
#define MXC_CCM_CHSCCDR_ESC_CLK_PODF_OFFSET (6)
|
||||
#define MXC_CCM_CHSCCDR_ESC_CLK_PODF_MASK (0x3F << 6)
|
||||
#define MXC_CCM_CHSCCDR_HSC2_CLK_PODF_OFFSET (3)
|
||||
#define MXC_CCM_CHSCCDR_HSC2_CLK_PODF_MASK (0x7 << 3)
|
||||
#define MXC_CCM_CHSCCDR_HSC1_CLK_PODF_OFFSET (0)
|
||||
#define MXC_CCM_CHSCCDR_HSC1_CLK_PODF_MASK (0x7)
|
||||
|
||||
/* Define the bits in register CSCDR2 */
|
||||
#define MXC_CCM_CSCDR2_CSPI_CLK_PRED_OFFSET (25)
|
||||
#define MXC_CCM_CSCDR2_CSPI_CLK_PRED_MASK (0x7 << 25)
|
||||
#define MXC_CCM_CSCDR2_CSPI_CLK_PODF_OFFSET (19)
|
||||
#define MXC_CCM_CSCDR2_CSPI_CLK_PODF_MASK (0x3F << 19)
|
||||
#define MXC_CCM_CSCDR2_SIM_CLK_PRED_OFFSET (16)
|
||||
#define MXC_CCM_CSCDR2_SIM_CLK_PRED_MASK (0x7 << 16)
|
||||
#define MXC_CCM_CSCDR2_SIM_CLK_PODF_OFFSET (9)
|
||||
#define MXC_CCM_CSCDR2_SIM_CLK_PODF_MASK (0x3F << 9)
|
||||
#define MXC_CCM_CSCDR2_SLIMBUS_CLK_PRED_OFFSET (6)
|
||||
#define MXC_CCM_CSCDR2_SLIMBUS_PRED_MASK (0x7 << 6)
|
||||
#define MXC_CCM_CSCDR2_SLIMBUS_PODF_OFFSET (0)
|
||||
#define MXC_CCM_CSCDR2_SLIMBUS_PODF_MASK (0x3F)
|
||||
|
||||
/* Define the bits in register CSCDR3 */
|
||||
#define MXC_CCM_CSCDR3_HSI2C_CLK_PRED_OFFSET (16)
|
||||
#define MXC_CCM_CSCDR3_HSI2C_CLK_PRED_MASK (0x7 << 16)
|
||||
#define MXC_CCM_CSCDR3_HSI2C_CLK_PODF_OFFSET (9)
|
||||
#define MXC_CCM_CSCDR3_HSI2C_CLK_PODF_MASK (0x3F << 9)
|
||||
#define MXC_CCM_CSCDR3_FIRI_CLK_PRED_OFFSET (6)
|
||||
#define MXC_CCM_CSCDR3_FIRI_CLK_PRED_MASK (0x7 << 6)
|
||||
#define MXC_CCM_CSCDR3_FIRI_CLK_PODF_OFFSET (0)
|
||||
#define MXC_CCM_CSCDR3_FIRI_CLK_PODF_MASK (0x3F)
|
||||
|
||||
/* Define the bits in register CSCDR4 */
|
||||
#define MXC_CCM_CSCDR4_CSI_MCLK2_CLK_PRED_OFFSET (16)
|
||||
#define MXC_CCM_CSCDR4_CSI_MCLK2_CLK_PRED_MASK (0x7 << 16)
|
||||
#define MXC_CCM_CSCDR4_CSI_MCLK2_CLK_PODF_OFFSET (9)
|
||||
#define MXC_CCM_CSCDR4_CSI_MCLK2_CLK_PODF_MASK (0x3F << 9)
|
||||
#define MXC_CCM_CSCDR4_CSI_MCLK1_CLK_PRED_OFFSET (6)
|
||||
#define MXC_CCM_CSCDR4_CSI_MCLK1_CLK_PRED_MASK (0x7 << 6)
|
||||
#define MXC_CCM_CSCDR4_CSI_MCLK1_CLK_PODF_OFFSET (0)
|
||||
#define MXC_CCM_CSCDR4_CSI_MCLK1_CLK_PODF_MASK (0x3F)
|
||||
|
||||
/* Define the bits in register CDHIPR */
|
||||
#define MXC_CCM_CDHIPR_ARM_PODF_BUSY (1 << 16)
|
||||
#define MXC_CCM_CDHIPR_DDR_HF_CLK_SEL_BUSY (1 << 8)
|
||||
#define MXC_CCM_CDHIPR_DDR_PODF_BUSY (1 << 7)
|
||||
#define MXC_CCM_CDHIPR_EMI_CLK_SEL_BUSY (1 << 6)
|
||||
#define MXC_CCM_CDHIPR_PERIPH_CLK_SEL_BUSY (1 << 5)
|
||||
#define MXC_CCM_CDHIPR_NFC_IPG_INT_MEM_PODF_BUSY (1 << 4)
|
||||
#define MXC_CCM_CDHIPR_AHB_PODF_BUSY (1 << 3)
|
||||
#define MXC_CCM_CDHIPR_EMI_PODF_BUSY (1 << 2)
|
||||
#define MXC_CCM_CDHIPR_AXI_B_PODF_BUSY (1 << 1)
|
||||
#define MXC_CCM_CDHIPR_AXI_A_PODF_BUSY (1 << 0)
|
||||
|
||||
/* Define the bits in register CDCR */
|
||||
#define MXC_CCM_CDCR_ARM_FREQ_SHIFT_DIVIDER (0x1 << 2)
|
||||
#define MXC_CCM_CDCR_PERIPH_CLK_DVFS_PODF_OFFSET (0)
|
||||
#define MXC_CCM_CDCR_PERIPH_CLK_DVFS_PODF_MASK (0x3)
|
||||
|
||||
/* Define the bits in register CLPCR */
|
||||
#define MXC_CCM_CLPCR_BYPASS_HSC_LPM_HS (0x1 << 23)
|
||||
#define MXC_CCM_CLPCR_BYPASS_SCC_LPM_HS (0x1 << 22)
|
||||
#define MX51_CCM_CLPCR_BYPASS_MAX_LPM_HS (0x1 << 21)
|
||||
#define MX53_CCM_CLPCR_BYPASS_MAX_LPM_HS (0x1 << 25)
|
||||
#define MXC_CCM_CLPCR_BYPASS_SDMA_LPM_HS (0x1 << 20)
|
||||
#define MXC_CCM_CLPCR_BYPASS_EMI_LPM_HS (0x1 << 19)
|
||||
#define MXC_CCM_CLPCR_BYPASS_IPU_LPM_HS (0x1 << 18)
|
||||
#define MXC_CCM_CLPCR_BYPASS_RTIC_LPM_HS (0x1 << 17)
|
||||
#define MXC_CCM_CLPCR_BYPASS_RNGC_LPM_HS (0x1 << 16)
|
||||
#define MXC_CCM_CLPCR_COSC_PWRDOWN (0x1 << 11)
|
||||
#define MXC_CCM_CLPCR_STBY_COUNT_OFFSET (9)
|
||||
#define MXC_CCM_CLPCR_STBY_COUNT_MASK (0x3 << 9)
|
||||
#define MXC_CCM_CLPCR_VSTBY (0x1 << 8)
|
||||
#define MXC_CCM_CLPCR_DIS_REF_OSC (0x1 << 7)
|
||||
#define MXC_CCM_CLPCR_SBYOS (0x1 << 6)
|
||||
#define MXC_CCM_CLPCR_ARM_CLK_DIS_ON_LPM (0x1 << 5)
|
||||
#define MXC_CCM_CLPCR_LPSR_CLK_SEL_OFFSET (3)
|
||||
#define MXC_CCM_CLPCR_LPSR_CLK_SEL_MASK (0x3 << 3)
|
||||
#define MXC_CCM_CLPCR_LPM_OFFSET (0)
|
||||
#define MXC_CCM_CLPCR_LPM_MASK (0x3)
|
||||
|
||||
/* Define the bits in register CISR */
|
||||
#define MXC_CCM_CISR_ARM_PODF_LOADED (0x1 << 25)
|
||||
#define MXC_CCM_CISR_NFC_IPG_INT_MEM_PODF_LOADED (0x1 << 21)
|
||||
#define MXC_CCM_CISR_AHB_PODF_LOADED (0x1 << 20)
|
||||
#define MXC_CCM_CISR_EMI_PODF_LOADED (0x1 << 19)
|
||||
#define MXC_CCM_CISR_AXI_B_PODF_LOADED (0x1 << 18)
|
||||
#define MXC_CCM_CISR_AXI_A_PODF_LOADED (0x1 << 17)
|
||||
#define MXC_CCM_CISR_DIVIDER_LOADED (0x1 << 16)
|
||||
#define MXC_CCM_CISR_COSC_READY (0x1 << 6)
|
||||
#define MXC_CCM_CISR_CKIH2_READY (0x1 << 5)
|
||||
#define MXC_CCM_CISR_CKIH_READY (0x1 << 4)
|
||||
#define MXC_CCM_CISR_FPM_READY (0x1 << 3)
|
||||
#define MXC_CCM_CISR_LRF_PLL3 (0x1 << 2)
|
||||
#define MXC_CCM_CISR_LRF_PLL2 (0x1 << 1)
|
||||
#define MXC_CCM_CISR_LRF_PLL1 (0x1)
|
||||
|
||||
/* Define the bits in register CIMR */
|
||||
#define MXC_CCM_CIMR_MASK_ARM_PODF_LOADED (0x1 << 25)
|
||||
#define MXC_CCM_CIMR_MASK_NFC_IPG_INT_MEM_PODF_LOADED (0x1 << 21)
|
||||
#define MXC_CCM_CIMR_MASK_EMI_PODF_LOADED (0x1 << 20)
|
||||
#define MXC_CCM_CIMR_MASK_AXI_C_PODF_LOADED (0x1 << 19)
|
||||
#define MXC_CCM_CIMR_MASK_AXI_B_PODF_LOADED (0x1 << 18)
|
||||
#define MXC_CCM_CIMR_MASK_AXI_A_PODF_LOADED (0x1 << 17)
|
||||
#define MXC_CCM_CIMR_MASK_DIVIDER_LOADED (0x1 << 16)
|
||||
#define MXC_CCM_CIMR_MASK_COSC_READY (0x1 << 5)
|
||||
#define MXC_CCM_CIMR_MASK_CKIH_READY (0x1 << 4)
|
||||
#define MXC_CCM_CIMR_MASK_FPM_READY (0x1 << 3)
|
||||
#define MXC_CCM_CIMR_MASK_LRF_PLL3 (0x1 << 2)
|
||||
#define MXC_CCM_CIMR_MASK_LRF_PLL2 (0x1 << 1)
|
||||
#define MXC_CCM_CIMR_MASK_LRF_PLL1 (0x1)
|
||||
|
||||
/* Define the bits in register CCOSR */
|
||||
#define MXC_CCM_CCOSR_CKO2_EN_OFFSET (0x1 << 24)
|
||||
#define MXC_CCM_CCOSR_CKO2_DIV_OFFSET (21)
|
||||
#define MXC_CCM_CCOSR_CKO2_DIV_MASK (0x7 << 21)
|
||||
#define MXC_CCM_CCOSR_CKO2_SEL_OFFSET (16)
|
||||
#define MXC_CCM_CCOSR_CKO2_SEL_MASK (0x1F << 16)
|
||||
#define MXC_CCM_CCOSR_CKOL_EN (0x1 << 7)
|
||||
#define MXC_CCM_CCOSR_CKOL_DIV_OFFSET (4)
|
||||
#define MXC_CCM_CCOSR_CKOL_DIV_MASK (0x7 << 4)
|
||||
#define MXC_CCM_CCOSR_CKOL_SEL_OFFSET (0)
|
||||
#define MXC_CCM_CCOSR_CKOL_SEL_MASK (0xF)
|
||||
|
||||
/* Define the bits in registers CGPR */
|
||||
#define MXC_CCM_CGPR_EFUSE_PROG_SUPPLY_GATE (0x1 << 4)
|
||||
#define MXC_CCM_CGPR_FPM_SEL (0x1 << 3)
|
||||
#define MXC_CCM_CGPR_VL_L2BIST_CLKDIV_OFFSET (0)
|
||||
#define MXC_CCM_CGPR_VL_L2BIST_CLKDIV_MASK (0x7)
|
||||
|
||||
/* Define the bits in registers CCGRx */
|
||||
#define MXC_CCM_CCGRx_CG_MASK 0x3
|
||||
#define MXC_CCM_CCGRx_MOD_OFF 0x0
|
||||
#define MXC_CCM_CCGRx_MOD_ON 0x3
|
||||
#define MXC_CCM_CCGRx_MOD_IDLE 0x1
|
||||
|
||||
#define MXC_CCM_CCGRx_CG15_MASK (0x3 << 30)
|
||||
#define MXC_CCM_CCGRx_CG14_MASK (0x3 << 28)
|
||||
#define MXC_CCM_CCGRx_CG13_MASK (0x3 << 26)
|
||||
#define MXC_CCM_CCGRx_CG12_MASK (0x3 << 24)
|
||||
#define MXC_CCM_CCGRx_CG11_MASK (0x3 << 22)
|
||||
#define MXC_CCM_CCGRx_CG10_MASK (0x3 << 20)
|
||||
#define MXC_CCM_CCGRx_CG9_MASK (0x3 << 18)
|
||||
#define MXC_CCM_CCGRx_CG8_MASK (0x3 << 16)
|
||||
#define MXC_CCM_CCGRx_CG5_MASK (0x3 << 10)
|
||||
#define MXC_CCM_CCGRx_CG4_MASK (0x3 << 8)
|
||||
#define MXC_CCM_CCGRx_CG3_MASK (0x3 << 6)
|
||||
#define MXC_CCM_CCGRx_CG2_MASK (0x3 << 4)
|
||||
#define MXC_CCM_CCGRx_CG1_MASK (0x3 << 2)
|
||||
#define MXC_CCM_CCGRx_CG0_MASK (0x3 << 0)
|
||||
|
||||
#define MXC_CCM_CCGRx_CG15_OFFSET 30
|
||||
#define MXC_CCM_CCGRx_CG14_OFFSET 28
|
||||
#define MXC_CCM_CCGRx_CG13_OFFSET 26
|
||||
#define MXC_CCM_CCGRx_CG12_OFFSET 24
|
||||
#define MXC_CCM_CCGRx_CG11_OFFSET 22
|
||||
#define MXC_CCM_CCGRx_CG10_OFFSET 20
|
||||
#define MXC_CCM_CCGRx_CG9_OFFSET 18
|
||||
#define MXC_CCM_CCGRx_CG8_OFFSET 16
|
||||
#define MXC_CCM_CCGRx_CG7_OFFSET 14
|
||||
#define MXC_CCM_CCGRx_CG6_OFFSET 12
|
||||
#define MXC_CCM_CCGRx_CG5_OFFSET 10
|
||||
#define MXC_CCM_CCGRx_CG4_OFFSET 8
|
||||
#define MXC_CCM_CCGRx_CG3_OFFSET 6
|
||||
#define MXC_CCM_CCGRx_CG2_OFFSET 4
|
||||
#define MXC_CCM_CCGRx_CG1_OFFSET 2
|
||||
#define MXC_CCM_CCGRx_CG0_OFFSET 0
|
||||
|
||||
#define MXC_DPTC_LP_BASE (MX51_GPC_BASE + 0x80)
|
||||
#define MXC_DPTC_GP_BASE (MX51_GPC_BASE + 0x100)
|
||||
#define MXC_DVFS_CORE_BASE (MX51_GPC_BASE + 0x180)
|
||||
#define MXC_DPTC_PER_BASE (MX51_GPC_BASE + 0x1C0)
|
||||
#define MXC_PGC_IPU_BASE (MX51_GPC_BASE + 0x220)
|
||||
#define MXC_PGC_VPU_BASE (MX51_GPC_BASE + 0x240)
|
||||
#define MXC_PGC_GPU_BASE (MX51_GPC_BASE + 0x260)
|
||||
#define MXC_SRPG_NEON_BASE (MX51_GPC_BASE + 0x280)
|
||||
#define MXC_SRPG_ARM_BASE (MX51_GPC_BASE + 0x2A0)
|
||||
#define MXC_SRPG_EMPGC0_BASE (MX51_GPC_BASE + 0x2C0)
|
||||
#define MXC_SRPG_EMPGC1_BASE (MX51_GPC_BASE + 0x2D0)
|
||||
#define MXC_SRPG_MEGAMIX_BASE (MX51_GPC_BASE + 0x2E0)
|
||||
#define MXC_SRPG_EMI_BASE (MX51_GPC_BASE + 0x300)
|
||||
|
||||
/* CORTEXA8 platform */
|
||||
#define MXC_CORTEXA8_PLAT_PVID (MX51_CORTEXA8_BASE + 0x0)
|
||||
#define MXC_CORTEXA8_PLAT_GPC (MX51_CORTEXA8_BASE + 0x4)
|
||||
#define MXC_CORTEXA8_PLAT_PIC (MX51_CORTEXA8_BASE + 0x8)
|
||||
#define MXC_CORTEXA8_PLAT_LPC (MX51_CORTEXA8_BASE + 0xC)
|
||||
#define MXC_CORTEXA8_PLAT_NEON_LPC (MX51_CORTEXA8_BASE + 0x10)
|
||||
#define MXC_CORTEXA8_PLAT_ICGC (MX51_CORTEXA8_BASE + 0x14)
|
||||
#define MXC_CORTEXA8_PLAT_AMC (MX51_CORTEXA8_BASE + 0x18)
|
||||
#define MXC_CORTEXA8_PLAT_NMC (MX51_CORTEXA8_BASE + 0x20)
|
||||
#define MXC_CORTEXA8_PLAT_NMS (MX51_CORTEXA8_BASE + 0x24)
|
||||
|
||||
/* DVFS CORE */
|
||||
#define MXC_DVFSTHRS (MXC_DVFS_CORE_BASE + 0x00)
|
||||
#define MXC_DVFSCOUN (MXC_DVFS_CORE_BASE + 0x04)
|
||||
#define MXC_DVFSSIG1 (MXC_DVFS_CORE_BASE + 0x08)
|
||||
#define MXC_DVFSSIG0 (MXC_DVFS_CORE_BASE + 0x0C)
|
||||
#define MXC_DVFSGPC0 (MXC_DVFS_CORE_BASE + 0x10)
|
||||
#define MXC_DVFSGPC1 (MXC_DVFS_CORE_BASE + 0x14)
|
||||
#define MXC_DVFSGPBT (MXC_DVFS_CORE_BASE + 0x18)
|
||||
#define MXC_DVFSEMAC (MXC_DVFS_CORE_BASE + 0x1C)
|
||||
#define MXC_DVFSCNTR (MXC_DVFS_CORE_BASE + 0x20)
|
||||
#define MXC_DVFSLTR0_0 (MXC_DVFS_CORE_BASE + 0x24)
|
||||
#define MXC_DVFSLTR0_1 (MXC_DVFS_CORE_BASE + 0x28)
|
||||
#define MXC_DVFSLTR1_0 (MXC_DVFS_CORE_BASE + 0x2C)
|
||||
#define MXC_DVFSLTR1_1 (MXC_DVFS_CORE_BASE + 0x30)
|
||||
#define MXC_DVFSPT0 (MXC_DVFS_CORE_BASE + 0x34)
|
||||
#define MXC_DVFSPT1 (MXC_DVFS_CORE_BASE + 0x38)
|
||||
#define MXC_DVFSPT2 (MXC_DVFS_CORE_BASE + 0x3C)
|
||||
#define MXC_DVFSPT3 (MXC_DVFS_CORE_BASE + 0x40)
|
||||
|
||||
/* GPC */
|
||||
#define MXC_GPC_CNTR (MX51_GPC_BASE + 0x0)
|
||||
#define MXC_GPC_PGR (MX51_GPC_BASE + 0x4)
|
||||
#define MXC_GPC_VCR (MX51_GPC_BASE + 0x8)
|
||||
#define MXC_GPC_ALL_PU (MX51_GPC_BASE + 0xC)
|
||||
#define MXC_GPC_NEON (MX51_GPC_BASE + 0x10)
|
||||
#define MXC_GPC_PGR_ARMPG_OFFSET 8
|
||||
#define MXC_GPC_PGR_ARMPG_MASK (3 << 8)
|
||||
|
||||
/* PGC */
|
||||
#define MXC_PGC_IPU_PGCR (MXC_PGC_IPU_BASE + 0x0)
|
||||
#define MXC_PGC_IPU_PGSR (MXC_PGC_IPU_BASE + 0xC)
|
||||
#define MXC_PGC_VPU_PGCR (MXC_PGC_VPU_BASE + 0x0)
|
||||
#define MXC_PGC_VPU_PGSR (MXC_PGC_VPU_BASE + 0xC)
|
||||
#define MXC_PGC_GPU_PGCR (MXC_PGC_GPU_BASE + 0x0)
|
||||
#define MXC_PGC_GPU_PGSR (MXC_PGC_GPU_BASE + 0xC)
|
||||
|
||||
#define MXC_PGCR_PCR 1
|
||||
#define MXC_SRPGCR_PCR 1
|
||||
#define MXC_EMPGCR_PCR 1
|
||||
#define MXC_PGSR_PSR 1
|
||||
|
||||
|
||||
#define MXC_CORTEXA8_PLAT_LPC_DSM (1 << 0)
|
||||
#define MXC_CORTEXA8_PLAT_LPC_DBG_DSM (1 << 1)
|
||||
|
||||
/* SRPG */
|
||||
#define MXC_SRPG_NEON_SRPGCR (MXC_SRPG_NEON_BASE + 0x0)
|
||||
#define MXC_SRPG_NEON_PUPSCR (MXC_SRPG_NEON_BASE + 0x4)
|
||||
#define MXC_SRPG_NEON_PDNSCR (MXC_SRPG_NEON_BASE + 0x8)
|
||||
|
||||
#define MXC_SRPG_ARM_SRPGCR (MXC_SRPG_ARM_BASE + 0x0)
|
||||
#define MXC_SRPG_ARM_PUPSCR (MXC_SRPG_ARM_BASE + 0x4)
|
||||
#define MXC_SRPG_ARM_PDNSCR (MXC_SRPG_ARM_BASE + 0x8)
|
||||
|
||||
#define MXC_SRPG_EMPGC0_SRPGCR (MXC_SRPG_EMPGC0_BASE + 0x0)
|
||||
#define MXC_SRPG_EMPGC0_PUPSCR (MXC_SRPG_EMPGC0_BASE + 0x4)
|
||||
#define MXC_SRPG_EMPGC0_PDNSCR (MXC_SRPG_EMPGC0_BASE + 0x8)
|
||||
|
||||
#define MXC_SRPG_EMPGC1_SRPGCR (MXC_SRPG_EMPGC1_BASE + 0x0)
|
||||
#define MXC_SRPG_EMPGC1_PUPSCR (MXC_SRPG_EMPGC1_BASE + 0x4)
|
||||
#define MXC_SRPG_EMPGC1_PDNSCR (MXC_SRPG_EMPGC1_BASE + 0x8)
|
||||
|
||||
#define MXC_SRPG_MEGAMIX_SRPGCR (MXC_SRPG_MEGAMIX_BASE + 0x0)
|
||||
#define MXC_SRPG_MEGAMIX_PUPSCR (MXC_SRPG_MEGAMIX_BASE + 0x4)
|
||||
#define MXC_SRPG_MEGAMIX_PDNSCR (MXC_SRPG_MEGAMIX_BASE + 0x8)
|
||||
|
||||
#define MXC_SRPGC_EMI_SRPGCR (MXC_SRPGC_EMI_BASE + 0x0)
|
||||
#define MXC_SRPGC_EMI_PUPSCR (MXC_SRPGC_EMI_BASE + 0x4)
|
||||
#define MXC_SRPGC_EMI_PDNSCR (MXC_SRPGC_EMI_BASE + 0x8)
|
||||
|
||||
#endif /* __ARCH_ARM_MACH_MX51_CRM_REGS_H__ */
|
||||
34
arch/arm/mach-imx/devices-imx50.h
Normal file
34
arch/arm/mach-imx/devices-imx50.h
Normal file
|
|
@ -0,0 +1,34 @@
|
|||
/*
|
||||
* Copyright (C) 2010 Freescale Semiconductor, Inc. All Rights Reserved.
|
||||
*/
|
||||
|
||||
/*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
|
||||
* You should have received a copy of the GNU General Public License along
|
||||
* with this program; if not, write to the Free Software Foundation, Inc.,
|
||||
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
|
||||
*/
|
||||
|
||||
#include <mach/mx50.h>
|
||||
#include <mach/devices-common.h>
|
||||
|
||||
extern const struct imx_imx_uart_1irq_data imx50_imx_uart_data[];
|
||||
#define imx50_add_imx_uart(id, pdata) \
|
||||
imx_add_imx_uart_1irq(&imx50_imx_uart_data[id], pdata)
|
||||
|
||||
extern const struct imx_fec_data imx50_fec_data;
|
||||
#define imx50_add_fec(pdata) \
|
||||
imx_add_fec(&imx50_fec_data, pdata)
|
||||
|
||||
extern const struct imx_imx_i2c_data imx50_imx_i2c_data[];
|
||||
#define imx50_add_imx_i2c(id, pdata) \
|
||||
imx_add_imx_i2c(&imx50_imx_i2c_data[id], pdata)
|
||||
71
arch/arm/mach-imx/devices-imx51.h
Normal file
71
arch/arm/mach-imx/devices-imx51.h
Normal file
|
|
@ -0,0 +1,71 @@
|
|||
/*
|
||||
* Copyright (C) 2010 Pengutronix
|
||||
* Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it under
|
||||
* the terms of the GNU General Public License version 2 as published by the
|
||||
* Free Software Foundation.
|
||||
*/
|
||||
#include <mach/mx51.h>
|
||||
#include <mach/devices-common.h>
|
||||
|
||||
extern const struct imx_fec_data imx51_fec_data;
|
||||
#define imx51_add_fec(pdata) \
|
||||
imx_add_fec(&imx51_fec_data, pdata)
|
||||
|
||||
extern const struct imx_fsl_usb2_udc_data imx51_fsl_usb2_udc_data;
|
||||
#define imx51_add_fsl_usb2_udc(pdata) \
|
||||
imx_add_fsl_usb2_udc(&imx51_fsl_usb2_udc_data, pdata)
|
||||
|
||||
extern const struct imx_imx_i2c_data imx51_imx_i2c_data[];
|
||||
#define imx51_add_imx_i2c(id, pdata) \
|
||||
imx_add_imx_i2c(&imx51_imx_i2c_data[id], pdata)
|
||||
#define imx51_add_hsi2c(pdata) \
|
||||
imx51_add_imx_i2c(2, pdata)
|
||||
|
||||
extern const struct imx_imx_ssi_data imx51_imx_ssi_data[];
|
||||
#define imx51_add_imx_ssi(id, pdata) \
|
||||
imx_add_imx_ssi(&imx51_imx_ssi_data[id], pdata)
|
||||
|
||||
extern const struct imx_imx_uart_1irq_data imx51_imx_uart_data[];
|
||||
#define imx51_add_imx_uart(id, pdata) \
|
||||
imx_add_imx_uart_1irq(&imx51_imx_uart_data[id], pdata)
|
||||
|
||||
extern const struct imx_mxc_ehci_data imx51_mxc_ehci_otg_data;
|
||||
#define imx51_add_mxc_ehci_otg(pdata) \
|
||||
imx_add_mxc_ehci(&imx51_mxc_ehci_otg_data, pdata)
|
||||
extern const struct imx_mxc_ehci_data imx51_mxc_ehci_hs_data[];
|
||||
#define imx51_add_mxc_ehci_hs(id, pdata) \
|
||||
imx_add_mxc_ehci(&imx51_mxc_ehci_hs_data[id - 1], pdata)
|
||||
|
||||
extern const struct imx_mxc_nand_data imx51_mxc_nand_data;
|
||||
#define imx51_add_mxc_nand(pdata) \
|
||||
imx_add_mxc_nand(&imx51_mxc_nand_data, pdata)
|
||||
|
||||
extern const struct imx_sdhci_esdhc_imx_data imx51_sdhci_esdhc_imx_data[];
|
||||
#define imx51_add_sdhci_esdhc_imx(id, pdata) \
|
||||
imx_add_sdhci_esdhc_imx(&imx51_sdhci_esdhc_imx_data[id], pdata)
|
||||
|
||||
extern const struct imx_spi_imx_data imx51_cspi_data;
|
||||
#define imx51_add_cspi(pdata) \
|
||||
imx_add_spi_imx(&imx51_cspi_data, pdata)
|
||||
|
||||
extern const struct imx_spi_imx_data imx51_ecspi_data[];
|
||||
#define imx51_add_ecspi(id, pdata) \
|
||||
imx_add_spi_imx(&imx51_ecspi_data[id], pdata)
|
||||
|
||||
extern const struct imx_imx2_wdt_data imx51_imx2_wdt_data[];
|
||||
#define imx51_add_imx2_wdt(id, pdata) \
|
||||
imx_add_imx2_wdt(&imx51_imx2_wdt_data[id])
|
||||
|
||||
extern const struct imx_mxc_pwm_data imx51_mxc_pwm_data[];
|
||||
#define imx51_add_mxc_pwm(id) \
|
||||
imx_add_mxc_pwm(&imx51_mxc_pwm_data[id])
|
||||
|
||||
extern const struct imx_imx_keypad_data imx51_imx_keypad_data;
|
||||
#define imx51_add_imx_keypad(pdata) \
|
||||
imx_add_imx_keypad(&imx51_imx_keypad_data, pdata)
|
||||
|
||||
extern const struct imx_pata_imx_data imx51_pata_imx_data;
|
||||
#define imx51_add_pata_imx() \
|
||||
imx_add_pata_imx(&imx51_pata_imx_data)
|
||||
48
arch/arm/mach-imx/devices-imx53.h
Normal file
48
arch/arm/mach-imx/devices-imx53.h
Normal file
|
|
@ -0,0 +1,48 @@
|
|||
/*
|
||||
* Copyright (C) 2010 Yong Shen. <Yong.Shen@linaro.org>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it under
|
||||
* the terms of the GNU General Public License version 2 as published by the
|
||||
* Free Software Foundation.
|
||||
*/
|
||||
#include <mach/mx53.h>
|
||||
#include <mach/devices-common.h>
|
||||
|
||||
extern const struct imx_fec_data imx53_fec_data;
|
||||
#define imx53_add_fec(pdata) \
|
||||
imx_add_fec(&imx53_fec_data, pdata)
|
||||
|
||||
extern const struct imx_imx_uart_1irq_data imx53_imx_uart_data[];
|
||||
#define imx53_add_imx_uart(id, pdata) \
|
||||
imx_add_imx_uart_1irq(&imx53_imx_uart_data[id], pdata)
|
||||
|
||||
|
||||
extern const struct imx_imx_i2c_data imx53_imx_i2c_data[];
|
||||
#define imx53_add_imx_i2c(id, pdata) \
|
||||
imx_add_imx_i2c(&imx53_imx_i2c_data[id], pdata)
|
||||
|
||||
extern const struct imx_sdhci_esdhc_imx_data imx53_sdhci_esdhc_imx_data[];
|
||||
#define imx53_add_sdhci_esdhc_imx(id, pdata) \
|
||||
imx_add_sdhci_esdhc_imx(&imx53_sdhci_esdhc_imx_data[id], pdata)
|
||||
|
||||
extern const struct imx_spi_imx_data imx53_ecspi_data[];
|
||||
#define imx53_add_ecspi(id, pdata) \
|
||||
imx_add_spi_imx(&imx53_ecspi_data[id], pdata)
|
||||
|
||||
extern const struct imx_imx2_wdt_data imx53_imx2_wdt_data[];
|
||||
#define imx53_add_imx2_wdt(id, pdata) \
|
||||
imx_add_imx2_wdt(&imx53_imx2_wdt_data[id])
|
||||
|
||||
extern const struct imx_imx_ssi_data imx53_imx_ssi_data[];
|
||||
#define imx53_add_imx_ssi(id, pdata) \
|
||||
imx_add_imx_ssi(&imx53_imx_ssi_data[id], pdata)
|
||||
|
||||
extern const struct imx_imx_keypad_data imx53_imx_keypad_data;
|
||||
#define imx53_add_imx_keypad(pdata) \
|
||||
imx_add_imx_keypad(&imx53_imx_keypad_data, pdata)
|
||||
|
||||
extern const struct imx_pata_imx_data imx53_pata_imx_data;
|
||||
#define imx53_add_pata_imx() \
|
||||
imx_add_pata_imx(&imx53_pata_imx_data)
|
||||
|
||||
extern struct platform_device *__init imx53_add_ahci_imx(void);
|
||||
10
arch/arm/mach-imx/efika.h
Normal file
10
arch/arm/mach-imx/efika.h
Normal file
|
|
@ -0,0 +1,10 @@
|
|||
#ifndef _EFIKA_H
|
||||
#define _EFIKA_H
|
||||
|
||||
#define EFIKA_WLAN_EN IMX_GPIO_NR(2, 16)
|
||||
#define EFIKA_WLAN_RESET IMX_GPIO_NR(2, 10)
|
||||
#define EFIKA_USB_PHY_RESET IMX_GPIO_NR(2, 9)
|
||||
|
||||
void __init efika_board_common_init(void);
|
||||
|
||||
#endif
|
||||
156
arch/arm/mach-imx/ehci-imx5.c
Normal file
156
arch/arm/mach-imx/ehci-imx5.c
Normal file
|
|
@ -0,0 +1,156 @@
|
|||
/*
|
||||
* Copyright (c) 2009 Daniel Mack <daniel@caiaq.de>
|
||||
* Copyright (C) 2010 Freescale Semiconductor, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of the GNU General Public License as published by the
|
||||
* Free Software Foundation; either version 2 of the License, or (at your
|
||||
* option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but
|
||||
* WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
|
||||
* or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
|
||||
* for more details.
|
||||
*/
|
||||
|
||||
#include <linux/platform_device.h>
|
||||
#include <linux/io.h>
|
||||
|
||||
#include <mach/hardware.h>
|
||||
#include <mach/mxc_ehci.h>
|
||||
|
||||
#define MXC_OTG_OFFSET 0
|
||||
#define MXC_H1_OFFSET 0x200
|
||||
#define MXC_H2_OFFSET 0x400
|
||||
|
||||
/* USB_CTRL */
|
||||
#define MXC_OTG_UCTRL_OWIE_BIT (1 << 27) /* OTG wakeup intr enable */
|
||||
#define MXC_OTG_UCTRL_OPM_BIT (1 << 24) /* OTG power mask */
|
||||
#define MXC_H1_UCTRL_H1UIE_BIT (1 << 12) /* Host1 ULPI interrupt enable */
|
||||
#define MXC_H1_UCTRL_H1WIE_BIT (1 << 11) /* HOST1 wakeup intr enable */
|
||||
#define MXC_H1_UCTRL_H1PM_BIT (1 << 8) /* HOST1 power mask */
|
||||
|
||||
/* USB_PHY_CTRL_FUNC */
|
||||
#define MXC_OTG_PHYCTRL_OC_DIS_BIT (1 << 8) /* OTG Disable Overcurrent Event */
|
||||
#define MXC_H1_OC_DIS_BIT (1 << 5) /* UH1 Disable Overcurrent Event */
|
||||
|
||||
/* USBH2CTRL */
|
||||
#define MXC_H2_UCTRL_H2UIE_BIT (1 << 8)
|
||||
#define MXC_H2_UCTRL_H2WIE_BIT (1 << 7)
|
||||
#define MXC_H2_UCTRL_H2PM_BIT (1 << 4)
|
||||
|
||||
#define MXC_USBCMD_OFFSET 0x140
|
||||
|
||||
/* USBCMD */
|
||||
#define MXC_UCMD_ITC_NO_THRESHOLD_MASK (~(0xff << 16)) /* Interrupt Threshold Control */
|
||||
|
||||
int mx51_initialize_usb_hw(int port, unsigned int flags)
|
||||
{
|
||||
unsigned int v;
|
||||
void __iomem *usb_base;
|
||||
void __iomem *usbotg_base;
|
||||
void __iomem *usbother_base;
|
||||
int ret = 0;
|
||||
|
||||
usb_base = ioremap(MX51_USB_OTG_BASE_ADDR, SZ_4K);
|
||||
if (!usb_base) {
|
||||
printk(KERN_ERR "%s(): ioremap failed\n", __func__);
|
||||
return -ENOMEM;
|
||||
}
|
||||
|
||||
switch (port) {
|
||||
case 0: /* OTG port */
|
||||
usbotg_base = usb_base + MXC_OTG_OFFSET;
|
||||
break;
|
||||
case 1: /* Host 1 port */
|
||||
usbotg_base = usb_base + MXC_H1_OFFSET;
|
||||
break;
|
||||
case 2: /* Host 2 port */
|
||||
usbotg_base = usb_base + MXC_H2_OFFSET;
|
||||
break;
|
||||
default:
|
||||
printk(KERN_ERR"%s no such port %d\n", __func__, port);
|
||||
ret = -ENOENT;
|
||||
goto error;
|
||||
}
|
||||
usbother_base = usb_base + MX5_USBOTHER_REGS_OFFSET;
|
||||
|
||||
switch (port) {
|
||||
case 0: /*OTG port */
|
||||
if (flags & MXC_EHCI_INTERNAL_PHY) {
|
||||
v = __raw_readl(usbother_base + MXC_USB_PHY_CTR_FUNC_OFFSET);
|
||||
|
||||
if (flags & MXC_EHCI_POWER_PINS_ENABLED) {
|
||||
/* OC/USBPWR is not used */
|
||||
v |= MXC_OTG_PHYCTRL_OC_DIS_BIT;
|
||||
} else {
|
||||
/* OC/USBPWR is used */
|
||||
v &= ~MXC_OTG_PHYCTRL_OC_DIS_BIT;
|
||||
}
|
||||
__raw_writel(v, usbother_base + MXC_USB_PHY_CTR_FUNC_OFFSET);
|
||||
|
||||
v = __raw_readl(usbother_base + MXC_USBCTRL_OFFSET);
|
||||
if (flags & MXC_EHCI_WAKEUP_ENABLED)
|
||||
v |= MXC_OTG_UCTRL_OWIE_BIT;/* OTG wakeup enable */
|
||||
else
|
||||
v &= ~MXC_OTG_UCTRL_OWIE_BIT;/* OTG wakeup disable */
|
||||
if (flags & MXC_EHCI_POWER_PINS_ENABLED)
|
||||
v |= MXC_OTG_UCTRL_OPM_BIT;
|
||||
else
|
||||
v &= ~MXC_OTG_UCTRL_OPM_BIT;
|
||||
__raw_writel(v, usbother_base + MXC_USBCTRL_OFFSET);
|
||||
}
|
||||
break;
|
||||
case 1: /* Host 1 */
|
||||
/*Host ULPI */
|
||||
v = __raw_readl(usbother_base + MXC_USBCTRL_OFFSET);
|
||||
if (flags & MXC_EHCI_WAKEUP_ENABLED) {
|
||||
/* HOST1 wakeup/ULPI intr enable */
|
||||
v |= (MXC_H1_UCTRL_H1WIE_BIT | MXC_H1_UCTRL_H1UIE_BIT);
|
||||
} else {
|
||||
/* HOST1 wakeup/ULPI intr disable */
|
||||
v &= ~(MXC_H1_UCTRL_H1WIE_BIT | MXC_H1_UCTRL_H1UIE_BIT);
|
||||
}
|
||||
|
||||
if (flags & MXC_EHCI_POWER_PINS_ENABLED)
|
||||
v &= ~MXC_H1_UCTRL_H1PM_BIT; /* HOST1 power mask used*/
|
||||
else
|
||||
v |= MXC_H1_UCTRL_H1PM_BIT; /* HOST1 power mask used*/
|
||||
__raw_writel(v, usbother_base + MXC_USBCTRL_OFFSET);
|
||||
|
||||
v = __raw_readl(usbother_base + MXC_USB_PHY_CTR_FUNC_OFFSET);
|
||||
if (flags & MXC_EHCI_POWER_PINS_ENABLED)
|
||||
v &= ~MXC_H1_OC_DIS_BIT; /* OC is used */
|
||||
else
|
||||
v |= MXC_H1_OC_DIS_BIT; /* OC is not used */
|
||||
__raw_writel(v, usbother_base + MXC_USB_PHY_CTR_FUNC_OFFSET);
|
||||
|
||||
v = __raw_readl(usbotg_base + MXC_USBCMD_OFFSET);
|
||||
if (flags & MXC_EHCI_ITC_NO_THRESHOLD)
|
||||
/* Interrupt Threshold Control:Immediate (no threshold) */
|
||||
v &= MXC_UCMD_ITC_NO_THRESHOLD_MASK;
|
||||
__raw_writel(v, usbotg_base + MXC_USBCMD_OFFSET);
|
||||
break;
|
||||
case 2: /* Host 2 ULPI */
|
||||
v = __raw_readl(usbother_base + MXC_USBH2CTRL_OFFSET);
|
||||
if (flags & MXC_EHCI_WAKEUP_ENABLED) {
|
||||
/* HOST1 wakeup/ULPI intr enable */
|
||||
v |= (MXC_H2_UCTRL_H2WIE_BIT | MXC_H2_UCTRL_H2UIE_BIT);
|
||||
} else {
|
||||
/* HOST1 wakeup/ULPI intr disable */
|
||||
v &= ~(MXC_H2_UCTRL_H2WIE_BIT | MXC_H2_UCTRL_H2UIE_BIT);
|
||||
}
|
||||
|
||||
if (flags & MXC_EHCI_POWER_PINS_ENABLED)
|
||||
v &= ~MXC_H2_UCTRL_H2PM_BIT; /* HOST2 power mask used*/
|
||||
else
|
||||
v |= MXC_H2_UCTRL_H2PM_BIT; /* HOST2 power mask used*/
|
||||
__raw_writel(v, usbother_base + MXC_USBH2CTRL_OFFSET);
|
||||
break;
|
||||
}
|
||||
|
||||
error:
|
||||
iounmap(usb_base);
|
||||
return ret;
|
||||
}
|
||||
|
||||
206
arch/arm/mach-imx/eukrea_mbimx51-baseboard.c
Normal file
206
arch/arm/mach-imx/eukrea_mbimx51-baseboard.c
Normal file
|
|
@ -0,0 +1,206 @@
|
|||
/*
|
||||
*
|
||||
* Copyright (C) 2010 Eric Bénard <eric@eukrea.com>
|
||||
*
|
||||
* The code contained herein is licensed under the GNU General Public
|
||||
* License. You may obtain a copy of the GNU General Public License
|
||||
* Version 2 or later at the following locations:
|
||||
*
|
||||
* http://www.opensource.org/licenses/gpl-license.html
|
||||
* http://www.gnu.org/copyleft/gpl.html
|
||||
*/
|
||||
|
||||
#include <linux/init.h>
|
||||
#include <linux/platform_device.h>
|
||||
#include <linux/serial_8250.h>
|
||||
#include <linux/i2c.h>
|
||||
#include <linux/gpio.h>
|
||||
#include <linux/io.h>
|
||||
#include <linux/interrupt.h>
|
||||
#include <linux/irq.h>
|
||||
#include <linux/i2c/tsc2007.h>
|
||||
#include <linux/leds.h>
|
||||
|
||||
#include <mach/common.h>
|
||||
#include <mach/hardware.h>
|
||||
#include <mach/iomux-mx51.h>
|
||||
|
||||
#include <asm/mach/arch.h>
|
||||
|
||||
#include "devices-imx51.h"
|
||||
|
||||
#define MBIMX51_TSC2007_GPIO IMX_GPIO_NR(3, 30)
|
||||
#define MBIMX51_LED0 IMX_GPIO_NR(3, 5)
|
||||
#define MBIMX51_LED1 IMX_GPIO_NR(3, 6)
|
||||
#define MBIMX51_LED2 IMX_GPIO_NR(3, 7)
|
||||
#define MBIMX51_LED3 IMX_GPIO_NR(3, 8)
|
||||
|
||||
static const struct gpio_led mbimx51_leds[] __initconst = {
|
||||
{
|
||||
.name = "led0",
|
||||
.default_trigger = "heartbeat",
|
||||
.active_low = 1,
|
||||
.gpio = MBIMX51_LED0,
|
||||
},
|
||||
{
|
||||
.name = "led1",
|
||||
.default_trigger = "nand-disk",
|
||||
.active_low = 1,
|
||||
.gpio = MBIMX51_LED1,
|
||||
},
|
||||
{
|
||||
.name = "led2",
|
||||
.default_trigger = "mmc0",
|
||||
.active_low = 1,
|
||||
.gpio = MBIMX51_LED2,
|
||||
},
|
||||
{
|
||||
.name = "led3",
|
||||
.default_trigger = "default-on",
|
||||
.active_low = 1,
|
||||
.gpio = MBIMX51_LED3,
|
||||
},
|
||||
};
|
||||
|
||||
static const struct gpio_led_platform_data mbimx51_leds_info __initconst = {
|
||||
.leds = mbimx51_leds,
|
||||
.num_leds = ARRAY_SIZE(mbimx51_leds),
|
||||
};
|
||||
|
||||
static iomux_v3_cfg_t mbimx51_pads[] = {
|
||||
/* UART2 */
|
||||
MX51_PAD_UART2_RXD__UART2_RXD,
|
||||
MX51_PAD_UART2_TXD__UART2_TXD,
|
||||
|
||||
/* UART3 */
|
||||
MX51_PAD_UART3_RXD__UART3_RXD,
|
||||
MX51_PAD_UART3_TXD__UART3_TXD,
|
||||
MX51_PAD_KEY_COL4__UART3_RTS,
|
||||
MX51_PAD_KEY_COL5__UART3_CTS,
|
||||
|
||||
/* TSC2007 IRQ */
|
||||
MX51_PAD_NANDF_D10__GPIO3_30,
|
||||
|
||||
/* LEDS */
|
||||
MX51_PAD_DISPB2_SER_DIN__GPIO3_5,
|
||||
MX51_PAD_DISPB2_SER_DIO__GPIO3_6,
|
||||
MX51_PAD_DISPB2_SER_CLK__GPIO3_7,
|
||||
MX51_PAD_DISPB2_SER_RS__GPIO3_8,
|
||||
|
||||
/* KPP */
|
||||
MX51_PAD_KEY_ROW0__KEY_ROW0,
|
||||
MX51_PAD_KEY_ROW1__KEY_ROW1,
|
||||
MX51_PAD_KEY_ROW2__KEY_ROW2,
|
||||
MX51_PAD_KEY_ROW3__KEY_ROW3,
|
||||
MX51_PAD_KEY_COL0__KEY_COL0,
|
||||
MX51_PAD_KEY_COL1__KEY_COL1,
|
||||
MX51_PAD_KEY_COL2__KEY_COL2,
|
||||
MX51_PAD_KEY_COL3__KEY_COL3,
|
||||
|
||||
/* SD 1 */
|
||||
MX51_PAD_SD1_CMD__SD1_CMD,
|
||||
MX51_PAD_SD1_CLK__SD1_CLK,
|
||||
MX51_PAD_SD1_DATA0__SD1_DATA0,
|
||||
MX51_PAD_SD1_DATA1__SD1_DATA1,
|
||||
MX51_PAD_SD1_DATA2__SD1_DATA2,
|
||||
MX51_PAD_SD1_DATA3__SD1_DATA3,
|
||||
|
||||
/* SD 2 */
|
||||
MX51_PAD_SD2_CMD__SD2_CMD,
|
||||
MX51_PAD_SD2_CLK__SD2_CLK,
|
||||
MX51_PAD_SD2_DATA0__SD2_DATA0,
|
||||
MX51_PAD_SD2_DATA1__SD2_DATA1,
|
||||
MX51_PAD_SD2_DATA2__SD2_DATA2,
|
||||
MX51_PAD_SD2_DATA3__SD2_DATA3,
|
||||
};
|
||||
|
||||
static const struct imxuart_platform_data uart_pdata __initconst = {
|
||||
.flags = IMXUART_HAVE_RTSCTS,
|
||||
};
|
||||
|
||||
static int mbimx51_keymap[] = {
|
||||
KEY(0, 0, KEY_1),
|
||||
KEY(0, 1, KEY_2),
|
||||
KEY(0, 2, KEY_3),
|
||||
KEY(0, 3, KEY_UP),
|
||||
|
||||
KEY(1, 0, KEY_4),
|
||||
KEY(1, 1, KEY_5),
|
||||
KEY(1, 2, KEY_6),
|
||||
KEY(1, 3, KEY_LEFT),
|
||||
|
||||
KEY(2, 0, KEY_7),
|
||||
KEY(2, 1, KEY_8),
|
||||
KEY(2, 2, KEY_9),
|
||||
KEY(2, 3, KEY_RIGHT),
|
||||
|
||||
KEY(3, 0, KEY_0),
|
||||
KEY(3, 1, KEY_DOWN),
|
||||
KEY(3, 2, KEY_ESC),
|
||||
KEY(3, 3, KEY_ENTER),
|
||||
};
|
||||
|
||||
static const struct matrix_keymap_data mbimx51_map_data __initconst = {
|
||||
.keymap = mbimx51_keymap,
|
||||
.keymap_size = ARRAY_SIZE(mbimx51_keymap),
|
||||
};
|
||||
|
||||
static int tsc2007_get_pendown_state(void)
|
||||
{
|
||||
return !gpio_get_value(MBIMX51_TSC2007_GPIO);
|
||||
}
|
||||
|
||||
struct tsc2007_platform_data tsc2007_data = {
|
||||
.model = 2007,
|
||||
.x_plate_ohms = 180,
|
||||
.get_pendown_state = tsc2007_get_pendown_state,
|
||||
};
|
||||
|
||||
static struct i2c_board_info mbimx51_i2c_devices[] = {
|
||||
{
|
||||
I2C_BOARD_INFO("tsc2007", 0x49),
|
||||
.irq = IMX_GPIO_TO_IRQ(MBIMX51_TSC2007_GPIO),
|
||||
.platform_data = &tsc2007_data,
|
||||
}, {
|
||||
I2C_BOARD_INFO("tlv320aic23", 0x1a),
|
||||
},
|
||||
};
|
||||
|
||||
/*
|
||||
* baseboard initialization.
|
||||
*/
|
||||
void __init eukrea_mbimx51_baseboard_init(void)
|
||||
{
|
||||
mxc_iomux_v3_setup_multiple_pads(mbimx51_pads,
|
||||
ARRAY_SIZE(mbimx51_pads));
|
||||
|
||||
imx51_add_imx_uart(1, NULL);
|
||||
imx51_add_imx_uart(2, &uart_pdata);
|
||||
|
||||
gpio_request(MBIMX51_LED0, "LED0");
|
||||
gpio_direction_output(MBIMX51_LED0, 1);
|
||||
gpio_free(MBIMX51_LED0);
|
||||
gpio_request(MBIMX51_LED1, "LED1");
|
||||
gpio_direction_output(MBIMX51_LED1, 1);
|
||||
gpio_free(MBIMX51_LED1);
|
||||
gpio_request(MBIMX51_LED2, "LED2");
|
||||
gpio_direction_output(MBIMX51_LED2, 1);
|
||||
gpio_free(MBIMX51_LED2);
|
||||
gpio_request(MBIMX51_LED3, "LED3");
|
||||
gpio_direction_output(MBIMX51_LED3, 1);
|
||||
gpio_free(MBIMX51_LED3);
|
||||
|
||||
gpio_led_register_device(-1, &mbimx51_leds_info);
|
||||
|
||||
imx51_add_imx_keypad(&mbimx51_map_data);
|
||||
|
||||
gpio_request(MBIMX51_TSC2007_GPIO, "tsc2007_irq");
|
||||
gpio_direction_input(MBIMX51_TSC2007_GPIO);
|
||||
irq_set_irq_type(gpio_to_irq(MBIMX51_TSC2007_GPIO),
|
||||
IRQF_TRIGGER_FALLING);
|
||||
i2c_register_board_info(1, mbimx51_i2c_devices,
|
||||
ARRAY_SIZE(mbimx51_i2c_devices));
|
||||
|
||||
imx51_add_sdhci_esdhc_imx(0, NULL);
|
||||
imx51_add_sdhci_esdhc_imx(1, NULL);
|
||||
}
|
||||
146
arch/arm/mach-imx/eukrea_mbimxsd-baseboard.c
Normal file
146
arch/arm/mach-imx/eukrea_mbimxsd-baseboard.c
Normal file
|
|
@ -0,0 +1,146 @@
|
|||
/*
|
||||
* Copyright (C) 2010 Eric Benard - eric@eukrea.com
|
||||
*
|
||||
* Based on pcm970-baseboard.c which is :
|
||||
* Copyright (C) 2008 Juergen Beisert (kernel@pengutronix.de)
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License
|
||||
* as published by the Free Software Foundation; either version 2
|
||||
* of the License, or (at your option) any later version.
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
|
||||
* MA 02110-1301, USA.
|
||||
*/
|
||||
|
||||
#include <linux/types.h>
|
||||
#include <linux/init.h>
|
||||
|
||||
#include <linux/gpio.h>
|
||||
#include <linux/interrupt.h>
|
||||
#include <linux/leds.h>
|
||||
#include <linux/platform_device.h>
|
||||
#include <linux/input.h>
|
||||
#include <linux/i2c.h>
|
||||
|
||||
#include <asm/mach-types.h>
|
||||
#include <asm/mach/arch.h>
|
||||
#include <asm/mach/time.h>
|
||||
#include <asm/mach/map.h>
|
||||
|
||||
#include <mach/hardware.h>
|
||||
#include <mach/common.h>
|
||||
#include <mach/iomux-mx51.h>
|
||||
#include <mach/audmux.h>
|
||||
|
||||
#include "devices-imx51.h"
|
||||
|
||||
static iomux_v3_cfg_t eukrea_mbimxsd_pads[] = {
|
||||
/* LED */
|
||||
MX51_PAD_NANDF_D10__GPIO3_30,
|
||||
/* SWITCH */
|
||||
NEW_PAD_CTRL(MX51_PAD_NANDF_D9__GPIO3_31, PAD_CTL_PUS_22K_UP |
|
||||
PAD_CTL_PKE | PAD_CTL_SRE_FAST |
|
||||
PAD_CTL_DSE_HIGH | PAD_CTL_PUE | PAD_CTL_HYS),
|
||||
/* UART2 */
|
||||
MX51_PAD_UART2_RXD__UART2_RXD,
|
||||
MX51_PAD_UART2_TXD__UART2_TXD,
|
||||
/* UART 3 */
|
||||
MX51_PAD_UART3_RXD__UART3_RXD,
|
||||
MX51_PAD_UART3_TXD__UART3_TXD,
|
||||
MX51_PAD_KEY_COL4__UART3_RTS,
|
||||
MX51_PAD_KEY_COL5__UART3_CTS,
|
||||
/* SD */
|
||||
MX51_PAD_SD1_CMD__SD1_CMD,
|
||||
MX51_PAD_SD1_CLK__SD1_CLK,
|
||||
MX51_PAD_SD1_DATA0__SD1_DATA0,
|
||||
MX51_PAD_SD1_DATA1__SD1_DATA1,
|
||||
MX51_PAD_SD1_DATA2__SD1_DATA2,
|
||||
MX51_PAD_SD1_DATA3__SD1_DATA3,
|
||||
/* SD1 CD */
|
||||
NEW_PAD_CTRL(MX51_PAD_GPIO1_0__SD1_CD, PAD_CTL_PUS_22K_UP |
|
||||
PAD_CTL_PKE | PAD_CTL_SRE_FAST |
|
||||
PAD_CTL_DSE_HIGH | PAD_CTL_PUE | PAD_CTL_HYS),
|
||||
};
|
||||
|
||||
#define GPIO_LED1 IMX_GPIO_NR(3, 30)
|
||||
#define GPIO_SWITCH1 IMX_GPIO_NR(3, 31)
|
||||
|
||||
static const struct gpio_led eukrea_mbimxsd_leds[] __initconst = {
|
||||
{
|
||||
.name = "led1",
|
||||
.default_trigger = "heartbeat",
|
||||
.active_low = 1,
|
||||
.gpio = GPIO_LED1,
|
||||
},
|
||||
};
|
||||
|
||||
static const struct gpio_led_platform_data
|
||||
eukrea_mbimxsd_led_info __initconst = {
|
||||
.leds = eukrea_mbimxsd_leds,
|
||||
.num_leds = ARRAY_SIZE(eukrea_mbimxsd_leds),
|
||||
};
|
||||
|
||||
static struct gpio_keys_button eukrea_mbimxsd_gpio_buttons[] = {
|
||||
{
|
||||
.gpio = GPIO_SWITCH1,
|
||||
.code = BTN_0,
|
||||
.desc = "BP1",
|
||||
.active_low = 1,
|
||||
.wakeup = 1,
|
||||
},
|
||||
};
|
||||
|
||||
static const struct gpio_keys_platform_data
|
||||
eukrea_mbimxsd_button_data __initconst = {
|
||||
.buttons = eukrea_mbimxsd_gpio_buttons,
|
||||
.nbuttons = ARRAY_SIZE(eukrea_mbimxsd_gpio_buttons),
|
||||
};
|
||||
|
||||
static const struct imxuart_platform_data uart_pdata __initconst = {
|
||||
.flags = IMXUART_HAVE_RTSCTS,
|
||||
};
|
||||
|
||||
static struct i2c_board_info eukrea_mbimxsd_i2c_devices[] = {
|
||||
{
|
||||
I2C_BOARD_INFO("tlv320aic23", 0x1a),
|
||||
},
|
||||
};
|
||||
|
||||
/*
|
||||
* system init for baseboard usage. Will be called by cpuimx51sd init.
|
||||
*
|
||||
* Add platform devices present on this baseboard and init
|
||||
* them from CPU side as far as required to use them later on
|
||||
*/
|
||||
void __init eukrea_mbimxsd51_baseboard_init(void)
|
||||
{
|
||||
if (mxc_iomux_v3_setup_multiple_pads(eukrea_mbimxsd_pads,
|
||||
ARRAY_SIZE(eukrea_mbimxsd_pads)))
|
||||
printk(KERN_ERR "error setting mbimxsd pads !\n");
|
||||
|
||||
imx51_add_imx_uart(1, NULL);
|
||||
imx51_add_imx_uart(2, &uart_pdata);
|
||||
|
||||
imx51_add_sdhci_esdhc_imx(0, NULL);
|
||||
|
||||
gpio_request(GPIO_LED1, "LED1");
|
||||
gpio_direction_output(GPIO_LED1, 1);
|
||||
gpio_free(GPIO_LED1);
|
||||
|
||||
gpio_request(GPIO_SWITCH1, "SWITCH1");
|
||||
gpio_direction_input(GPIO_SWITCH1);
|
||||
gpio_free(GPIO_SWITCH1);
|
||||
|
||||
i2c_register_board_info(0, eukrea_mbimxsd_i2c_devices,
|
||||
ARRAY_SIZE(eukrea_mbimxsd_i2c_devices));
|
||||
|
||||
gpio_led_register_device(-1, &eukrea_mbimxsd_led_info);
|
||||
imx_add_gpio_keys(&eukrea_mbimxsd_button_data);
|
||||
}
|
||||
116
arch/arm/mach-imx/imx51-dt.c
Normal file
116
arch/arm/mach-imx/imx51-dt.c
Normal file
|
|
@ -0,0 +1,116 @@
|
|||
/*
|
||||
* Copyright 2011 Freescale Semiconductor, Inc. All Rights Reserved.
|
||||
* Copyright 2011 Linaro Ltd.
|
||||
*
|
||||
* The code contained herein is licensed under the GNU General Public
|
||||
* License. You may obtain a copy of the GNU General Public License
|
||||
* Version 2 or later at the following locations:
|
||||
*
|
||||
* http://www.opensource.org/licenses/gpl-license.html
|
||||
* http://www.gnu.org/copyleft/gpl.html
|
||||
*/
|
||||
|
||||
#include <linux/irq.h>
|
||||
#include <linux/irqdomain.h>
|
||||
#include <linux/of_irq.h>
|
||||
#include <linux/of_platform.h>
|
||||
#include <asm/mach/arch.h>
|
||||
#include <asm/mach/time.h>
|
||||
#include <mach/common.h>
|
||||
#include <mach/mx51.h>
|
||||
|
||||
/*
|
||||
* Lookup table for attaching a specific name and platform_data pointer to
|
||||
* devices as they get created by of_platform_populate(). Ideally this table
|
||||
* would not exist, but the current clock implementation depends on some devices
|
||||
* having a specific name.
|
||||
*/
|
||||
static const struct of_dev_auxdata imx51_auxdata_lookup[] __initconst = {
|
||||
OF_DEV_AUXDATA("fsl,imx51-uart", MX51_UART1_BASE_ADDR, "imx21-uart.0", NULL),
|
||||
OF_DEV_AUXDATA("fsl,imx51-uart", MX51_UART2_BASE_ADDR, "imx21-uart.1", NULL),
|
||||
OF_DEV_AUXDATA("fsl,imx51-uart", MX51_UART3_BASE_ADDR, "imx21-uart.2", NULL),
|
||||
OF_DEV_AUXDATA("fsl,imx51-fec", MX51_FEC_BASE_ADDR, "imx27-fec.0", NULL),
|
||||
OF_DEV_AUXDATA("fsl,imx51-esdhc", MX51_ESDHC1_BASE_ADDR, "sdhci-esdhc-imx51.0", NULL),
|
||||
OF_DEV_AUXDATA("fsl,imx51-esdhc", MX51_ESDHC2_BASE_ADDR, "sdhci-esdhc-imx51.1", NULL),
|
||||
OF_DEV_AUXDATA("fsl,imx51-esdhc", MX51_ESDHC3_BASE_ADDR, "sdhci-esdhc-imx51.2", NULL),
|
||||
OF_DEV_AUXDATA("fsl,imx51-esdhc", MX51_ESDHC4_BASE_ADDR, "sdhci-esdhc-imx51.3", NULL),
|
||||
OF_DEV_AUXDATA("fsl,imx51-ecspi", MX51_ECSPI1_BASE_ADDR, "imx51-ecspi.0", NULL),
|
||||
OF_DEV_AUXDATA("fsl,imx51-ecspi", MX51_ECSPI2_BASE_ADDR, "imx51-ecspi.1", NULL),
|
||||
OF_DEV_AUXDATA("fsl,imx51-cspi", MX51_CSPI_BASE_ADDR, "imx35-cspi.0", NULL),
|
||||
OF_DEV_AUXDATA("fsl,imx51-i2c", MX51_I2C1_BASE_ADDR, "imx-i2c.0", NULL),
|
||||
OF_DEV_AUXDATA("fsl,imx51-i2c", MX51_I2C2_BASE_ADDR, "imx-i2c.1", NULL),
|
||||
OF_DEV_AUXDATA("fsl,imx51-sdma", MX51_SDMA_BASE_ADDR, "imx35-sdma", NULL),
|
||||
OF_DEV_AUXDATA("fsl,imx51-wdt", MX51_WDOG1_BASE_ADDR, "imx2-wdt.0", NULL),
|
||||
{ /* sentinel */ }
|
||||
};
|
||||
|
||||
static void __init imx51_tzic_add_irq_domain(struct device_node *np,
|
||||
struct device_node *interrupt_parent)
|
||||
{
|
||||
irq_domain_add_simple(np, 0);
|
||||
}
|
||||
|
||||
static void __init imx51_gpio_add_irq_domain(struct device_node *np,
|
||||
struct device_node *interrupt_parent)
|
||||
{
|
||||
static int gpio_irq_base = MXC_GPIO_IRQ_START + ARCH_NR_GPIOS -
|
||||
32 * 4; /* imx51 gets 4 gpio ports */
|
||||
|
||||
irq_domain_add_simple(np, gpio_irq_base);
|
||||
gpio_irq_base += 32;
|
||||
}
|
||||
|
||||
static const struct of_device_id imx51_irq_match[] __initconst = {
|
||||
{ .compatible = "fsl,imx51-tzic", .data = imx51_tzic_add_irq_domain, },
|
||||
{ .compatible = "fsl,imx51-gpio", .data = imx51_gpio_add_irq_domain, },
|
||||
{ /* sentinel */ }
|
||||
};
|
||||
|
||||
static const struct of_device_id imx51_iomuxc_of_match[] __initconst = {
|
||||
{ .compatible = "fsl,imx51-iomuxc-babbage", .data = imx51_babbage_common_init, },
|
||||
{ /* sentinel */ }
|
||||
};
|
||||
|
||||
static void __init imx51_dt_init(void)
|
||||
{
|
||||
struct device_node *node;
|
||||
const struct of_device_id *of_id;
|
||||
void (*func)(void);
|
||||
|
||||
of_irq_init(imx51_irq_match);
|
||||
|
||||
node = of_find_matching_node(NULL, imx51_iomuxc_of_match);
|
||||
if (node) {
|
||||
of_id = of_match_node(imx51_iomuxc_of_match, node);
|
||||
func = of_id->data;
|
||||
func();
|
||||
of_node_put(node);
|
||||
}
|
||||
|
||||
of_platform_populate(NULL, of_default_bus_match_table,
|
||||
imx51_auxdata_lookup, NULL);
|
||||
}
|
||||
|
||||
static void __init imx51_timer_init(void)
|
||||
{
|
||||
mx51_clocks_init_dt();
|
||||
}
|
||||
|
||||
static struct sys_timer imx51_timer = {
|
||||
.init = imx51_timer_init,
|
||||
};
|
||||
|
||||
static const char *imx51_dt_board_compat[] __initdata = {
|
||||
"fsl,imx51-babbage",
|
||||
NULL
|
||||
};
|
||||
|
||||
DT_MACHINE_START(IMX51_DT, "Freescale i.MX51 (Device Tree Support)")
|
||||
.map_io = mx51_map_io,
|
||||
.init_early = imx51_init_early,
|
||||
.init_irq = mx51_init_irq,
|
||||
.handle_irq = imx51_handle_irq,
|
||||
.timer = &imx51_timer,
|
||||
.init_machine = imx51_dt_init,
|
||||
.dt_compat = imx51_dt_board_compat,
|
||||
MACHINE_END
|
||||
126
arch/arm/mach-imx/imx53-dt.c
Normal file
126
arch/arm/mach-imx/imx53-dt.c
Normal file
|
|
@ -0,0 +1,126 @@
|
|||
/*
|
||||
* Copyright 2011 Freescale Semiconductor, Inc. All Rights Reserved.
|
||||
* Copyright 2011 Linaro Ltd.
|
||||
*
|
||||
* The code contained herein is licensed under the GNU General Public
|
||||
* License. You may obtain a copy of the GNU General Public License
|
||||
* Version 2 or later at the following locations:
|
||||
*
|
||||
* http://www.opensource.org/licenses/gpl-license.html
|
||||
* http://www.gnu.org/copyleft/gpl.html
|
||||
*/
|
||||
|
||||
#include <linux/io.h>
|
||||
#include <linux/irq.h>
|
||||
#include <linux/irqdomain.h>
|
||||
#include <linux/of_irq.h>
|
||||
#include <linux/of_platform.h>
|
||||
#include <asm/mach/arch.h>
|
||||
#include <asm/mach/time.h>
|
||||
#include <mach/common.h>
|
||||
#include <mach/mx53.h>
|
||||
|
||||
/*
|
||||
* Lookup table for attaching a specific name and platform_data pointer to
|
||||
* devices as they get created by of_platform_populate(). Ideally this table
|
||||
* would not exist, but the current clock implementation depends on some devices
|
||||
* having a specific name.
|
||||
*/
|
||||
static const struct of_dev_auxdata imx53_auxdata_lookup[] __initconst = {
|
||||
OF_DEV_AUXDATA("fsl,imx53-uart", MX53_UART1_BASE_ADDR, "imx21-uart.0", NULL),
|
||||
OF_DEV_AUXDATA("fsl,imx53-uart", MX53_UART2_BASE_ADDR, "imx21-uart.1", NULL),
|
||||
OF_DEV_AUXDATA("fsl,imx53-uart", MX53_UART3_BASE_ADDR, "imx21-uart.2", NULL),
|
||||
OF_DEV_AUXDATA("fsl,imx53-uart", MX53_UART4_BASE_ADDR, "imx21-uart.3", NULL),
|
||||
OF_DEV_AUXDATA("fsl,imx53-uart", MX53_UART5_BASE_ADDR, "imx21-uart.4", NULL),
|
||||
OF_DEV_AUXDATA("fsl,imx53-fec", MX53_FEC_BASE_ADDR, "imx25-fec.0", NULL),
|
||||
OF_DEV_AUXDATA("fsl,imx53-esdhc", MX53_ESDHC1_BASE_ADDR, "sdhci-esdhc-imx53.0", NULL),
|
||||
OF_DEV_AUXDATA("fsl,imx53-esdhc", MX53_ESDHC2_BASE_ADDR, "sdhci-esdhc-imx53.1", NULL),
|
||||
OF_DEV_AUXDATA("fsl,imx53-esdhc", MX53_ESDHC3_BASE_ADDR, "sdhci-esdhc-imx53.2", NULL),
|
||||
OF_DEV_AUXDATA("fsl,imx53-esdhc", MX53_ESDHC4_BASE_ADDR, "sdhci-esdhc-imx53.3", NULL),
|
||||
OF_DEV_AUXDATA("fsl,imx53-ecspi", MX53_ECSPI1_BASE_ADDR, "imx51-ecspi.0", NULL),
|
||||
OF_DEV_AUXDATA("fsl,imx53-ecspi", MX53_ECSPI2_BASE_ADDR, "imx51-ecspi.1", NULL),
|
||||
OF_DEV_AUXDATA("fsl,imx53-cspi", MX53_CSPI_BASE_ADDR, "imx35-cspi.0", NULL),
|
||||
OF_DEV_AUXDATA("fsl,imx53-i2c", MX53_I2C1_BASE_ADDR, "imx-i2c.0", NULL),
|
||||
OF_DEV_AUXDATA("fsl,imx53-i2c", MX53_I2C2_BASE_ADDR, "imx-i2c.1", NULL),
|
||||
OF_DEV_AUXDATA("fsl,imx53-i2c", MX53_I2C3_BASE_ADDR, "imx-i2c.2", NULL),
|
||||
OF_DEV_AUXDATA("fsl,imx53-sdma", MX53_SDMA_BASE_ADDR, "imx35-sdma", NULL),
|
||||
OF_DEV_AUXDATA("fsl,imx53-wdt", MX53_WDOG1_BASE_ADDR, "imx2-wdt.0", NULL),
|
||||
{ /* sentinel */ }
|
||||
};
|
||||
|
||||
static void __init imx53_tzic_add_irq_domain(struct device_node *np,
|
||||
struct device_node *interrupt_parent)
|
||||
{
|
||||
irq_domain_add_simple(np, 0);
|
||||
}
|
||||
|
||||
static void __init imx53_gpio_add_irq_domain(struct device_node *np,
|
||||
struct device_node *interrupt_parent)
|
||||
{
|
||||
static int gpio_irq_base = MXC_GPIO_IRQ_START + ARCH_NR_GPIOS -
|
||||
32 * 7; /* imx53 gets 7 gpio ports */
|
||||
|
||||
irq_domain_add_simple(np, gpio_irq_base);
|
||||
gpio_irq_base += 32;
|
||||
}
|
||||
|
||||
static const struct of_device_id imx53_irq_match[] __initconst = {
|
||||
{ .compatible = "fsl,imx53-tzic", .data = imx53_tzic_add_irq_domain, },
|
||||
{ .compatible = "fsl,imx53-gpio", .data = imx53_gpio_add_irq_domain, },
|
||||
{ /* sentinel */ }
|
||||
};
|
||||
|
||||
static const struct of_device_id imx53_iomuxc_of_match[] __initconst = {
|
||||
{ .compatible = "fsl,imx53-iomuxc-ard", .data = imx53_ard_common_init, },
|
||||
{ .compatible = "fsl,imx53-iomuxc-evk", .data = imx53_evk_common_init, },
|
||||
{ .compatible = "fsl,imx53-iomuxc-qsb", .data = imx53_qsb_common_init, },
|
||||
{ .compatible = "fsl,imx53-iomuxc-smd", .data = imx53_smd_common_init, },
|
||||
{ /* sentinel */ }
|
||||
};
|
||||
|
||||
static void __init imx53_dt_init(void)
|
||||
{
|
||||
struct device_node *node;
|
||||
const struct of_device_id *of_id;
|
||||
void (*func)(void);
|
||||
|
||||
of_irq_init(imx53_irq_match);
|
||||
|
||||
node = of_find_matching_node(NULL, imx53_iomuxc_of_match);
|
||||
if (node) {
|
||||
of_id = of_match_node(imx53_iomuxc_of_match, node);
|
||||
func = of_id->data;
|
||||
func();
|
||||
of_node_put(node);
|
||||
}
|
||||
|
||||
of_platform_populate(NULL, of_default_bus_match_table,
|
||||
imx53_auxdata_lookup, NULL);
|
||||
}
|
||||
|
||||
static void __init imx53_timer_init(void)
|
||||
{
|
||||
mx53_clocks_init_dt();
|
||||
}
|
||||
|
||||
static struct sys_timer imx53_timer = {
|
||||
.init = imx53_timer_init,
|
||||
};
|
||||
|
||||
static const char *imx53_dt_board_compat[] __initdata = {
|
||||
"fsl,imx53-ard",
|
||||
"fsl,imx53-evk",
|
||||
"fsl,imx53-qsb",
|
||||
"fsl,imx53-smd",
|
||||
NULL
|
||||
};
|
||||
|
||||
DT_MACHINE_START(IMX53_DT, "Freescale i.MX53 (Device Tree Support)")
|
||||
.map_io = mx53_map_io,
|
||||
.init_early = imx53_init_early,
|
||||
.init_irq = mx53_init_irq,
|
||||
.handle_irq = imx53_handle_irq,
|
||||
.timer = &imx53_timer,
|
||||
.init_machine = imx53_dt_init,
|
||||
.dt_compat = imx53_dt_board_compat,
|
||||
MACHINE_END
|
||||
300
arch/arm/mach-imx/mach-cpuimx51.c
Normal file
300
arch/arm/mach-imx/mach-cpuimx51.c
Normal file
|
|
@ -0,0 +1,300 @@
|
|||
/*
|
||||
*
|
||||
* Copyright (C) 2010 Eric Bénard <eric@eukrea.com>
|
||||
*
|
||||
* based on board-mx51_babbage.c which is
|
||||
* Copyright 2009 Freescale Semiconductor, Inc. All Rights Reserved.
|
||||
* Copyright (C) 2009-2010 Amit Kucheria <amit.kucheria@canonical.com>
|
||||
*
|
||||
* The code contained herein is licensed under the GNU General Public
|
||||
* License. You may obtain a copy of the GNU General Public License
|
||||
* Version 2 or later at the following locations:
|
||||
*
|
||||
* http://www.opensource.org/licenses/gpl-license.html
|
||||
* http://www.gnu.org/copyleft/gpl.html
|
||||
*/
|
||||
|
||||
#include <linux/init.h>
|
||||
#include <linux/platform_device.h>
|
||||
#include <linux/serial_8250.h>
|
||||
#include <linux/i2c.h>
|
||||
#include <linux/gpio.h>
|
||||
#include <linux/delay.h>
|
||||
#include <linux/io.h>
|
||||
#include <linux/interrupt.h>
|
||||
|
||||
#include <mach/eukrea-baseboards.h>
|
||||
#include <mach/common.h>
|
||||
#include <mach/hardware.h>
|
||||
#include <mach/iomux-mx51.h>
|
||||
|
||||
#include <asm/setup.h>
|
||||
#include <asm/mach-types.h>
|
||||
#include <asm/mach/arch.h>
|
||||
#include <asm/mach/time.h>
|
||||
|
||||
#include "devices-imx51.h"
|
||||
|
||||
#define CPUIMX51_USBH1_STP IMX_GPIO_NR(1, 27)
|
||||
#define CPUIMX51_QUARTA_GPIO IMX_GPIO_NR(3, 28)
|
||||
#define CPUIMX51_QUARTB_GPIO IMX_GPIO_NR(3, 25)
|
||||
#define CPUIMX51_QUARTC_GPIO IMX_GPIO_NR(3, 26)
|
||||
#define CPUIMX51_QUARTD_GPIO IMX_GPIO_NR(3, 27)
|
||||
#define CPUIMX51_QUART_XTAL 14745600
|
||||
#define CPUIMX51_QUART_REGSHIFT 17
|
||||
|
||||
/* USB_CTRL_1 */
|
||||
#define MX51_USB_CTRL_1_OFFSET 0x10
|
||||
#define MX51_USB_CTRL_UH1_EXT_CLK_EN (1 << 25)
|
||||
|
||||
#define MX51_USB_PLLDIV_12_MHZ 0x00
|
||||
#define MX51_USB_PLL_DIV_19_2_MHZ 0x01
|
||||
#define MX51_USB_PLL_DIV_24_MHZ 0x02
|
||||
|
||||
static struct plat_serial8250_port serial_platform_data[] = {
|
||||
{
|
||||
.mapbase = (unsigned long)(MX51_CS1_BASE_ADDR + 0x400000),
|
||||
.irq = IMX_GPIO_TO_IRQ(CPUIMX51_QUARTA_GPIO),
|
||||
.irqflags = IRQF_TRIGGER_HIGH,
|
||||
.uartclk = CPUIMX51_QUART_XTAL,
|
||||
.regshift = CPUIMX51_QUART_REGSHIFT,
|
||||
.iotype = UPIO_MEM,
|
||||
.flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_IOREMAP,
|
||||
}, {
|
||||
.mapbase = (unsigned long)(MX51_CS1_BASE_ADDR + 0x800000),
|
||||
.irq = IMX_GPIO_TO_IRQ(CPUIMX51_QUARTB_GPIO),
|
||||
.irqflags = IRQF_TRIGGER_HIGH,
|
||||
.uartclk = CPUIMX51_QUART_XTAL,
|
||||
.regshift = CPUIMX51_QUART_REGSHIFT,
|
||||
.iotype = UPIO_MEM,
|
||||
.flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_IOREMAP,
|
||||
}, {
|
||||
.mapbase = (unsigned long)(MX51_CS1_BASE_ADDR + 0x1000000),
|
||||
.irq = IMX_GPIO_TO_IRQ(CPUIMX51_QUARTC_GPIO),
|
||||
.irqflags = IRQF_TRIGGER_HIGH,
|
||||
.uartclk = CPUIMX51_QUART_XTAL,
|
||||
.regshift = CPUIMX51_QUART_REGSHIFT,
|
||||
.iotype = UPIO_MEM,
|
||||
.flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_IOREMAP,
|
||||
}, {
|
||||
.mapbase = (unsigned long)(MX51_CS1_BASE_ADDR + 0x2000000),
|
||||
.irq = IMX_GPIO_TO_IRQ(CPUIMX51_QUARTD_GPIO),
|
||||
.irqflags = IRQF_TRIGGER_HIGH,
|
||||
.uartclk = CPUIMX51_QUART_XTAL,
|
||||
.regshift = CPUIMX51_QUART_REGSHIFT,
|
||||
.iotype = UPIO_MEM,
|
||||
.flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_IOREMAP,
|
||||
}, {
|
||||
}
|
||||
};
|
||||
|
||||
static struct platform_device serial_device = {
|
||||
.name = "serial8250",
|
||||
.id = 0,
|
||||
.dev = {
|
||||
.platform_data = serial_platform_data,
|
||||
},
|
||||
};
|
||||
|
||||
static struct platform_device *devices[] __initdata = {
|
||||
&serial_device,
|
||||
};
|
||||
|
||||
static iomux_v3_cfg_t eukrea_cpuimx51_pads[] = {
|
||||
/* UART1 */
|
||||
MX51_PAD_UART1_RXD__UART1_RXD,
|
||||
MX51_PAD_UART1_TXD__UART1_TXD,
|
||||
MX51_PAD_UART1_RTS__UART1_RTS,
|
||||
MX51_PAD_UART1_CTS__UART1_CTS,
|
||||
|
||||
/* I2C2 */
|
||||
MX51_PAD_GPIO1_2__I2C2_SCL,
|
||||
MX51_PAD_GPIO1_3__I2C2_SDA,
|
||||
MX51_PAD_NANDF_D10__GPIO3_30,
|
||||
|
||||
/* QUART IRQ */
|
||||
MX51_PAD_NANDF_D15__GPIO3_25,
|
||||
MX51_PAD_NANDF_D14__GPIO3_26,
|
||||
MX51_PAD_NANDF_D13__GPIO3_27,
|
||||
MX51_PAD_NANDF_D12__GPIO3_28,
|
||||
|
||||
/* USB HOST1 */
|
||||
MX51_PAD_USBH1_CLK__USBH1_CLK,
|
||||
MX51_PAD_USBH1_DIR__USBH1_DIR,
|
||||
MX51_PAD_USBH1_NXT__USBH1_NXT,
|
||||
MX51_PAD_USBH1_DATA0__USBH1_DATA0,
|
||||
MX51_PAD_USBH1_DATA1__USBH1_DATA1,
|
||||
MX51_PAD_USBH1_DATA2__USBH1_DATA2,
|
||||
MX51_PAD_USBH1_DATA3__USBH1_DATA3,
|
||||
MX51_PAD_USBH1_DATA4__USBH1_DATA4,
|
||||
MX51_PAD_USBH1_DATA5__USBH1_DATA5,
|
||||
MX51_PAD_USBH1_DATA6__USBH1_DATA6,
|
||||
MX51_PAD_USBH1_DATA7__USBH1_DATA7,
|
||||
MX51_PAD_USBH1_STP__USBH1_STP,
|
||||
};
|
||||
|
||||
static const struct mxc_nand_platform_data
|
||||
eukrea_cpuimx51_nand_board_info __initconst = {
|
||||
.width = 1,
|
||||
.hw_ecc = 1,
|
||||
.flash_bbt = 1,
|
||||
};
|
||||
|
||||
static const struct imxuart_platform_data uart_pdata __initconst = {
|
||||
.flags = IMXUART_HAVE_RTSCTS,
|
||||
};
|
||||
|
||||
static const
|
||||
struct imxi2c_platform_data eukrea_cpuimx51_i2c_data __initconst = {
|
||||
.bitrate = 100000,
|
||||
};
|
||||
|
||||
static struct i2c_board_info eukrea_cpuimx51_i2c_devices[] = {
|
||||
{
|
||||
I2C_BOARD_INFO("pcf8563", 0x51),
|
||||
},
|
||||
};
|
||||
|
||||
/* This function is board specific as the bit mask for the plldiv will also
|
||||
be different for other Freescale SoCs, thus a common bitmask is not
|
||||
possible and cannot get place in /plat-mxc/ehci.c.*/
|
||||
static int initialize_otg_port(struct platform_device *pdev)
|
||||
{
|
||||
u32 v;
|
||||
void __iomem *usb_base;
|
||||
void __iomem *usbother_base;
|
||||
|
||||
usb_base = ioremap(MX51_USB_OTG_BASE_ADDR, SZ_4K);
|
||||
if (!usb_base)
|
||||
return -ENOMEM;
|
||||
usbother_base = usb_base + MX5_USBOTHER_REGS_OFFSET;
|
||||
|
||||
/* Set the PHY clock to 19.2MHz */
|
||||
v = __raw_readl(usbother_base + MXC_USB_PHY_CTR_FUNC2_OFFSET);
|
||||
v &= ~MX5_USB_UTMI_PHYCTRL1_PLLDIV_MASK;
|
||||
v |= MX51_USB_PLL_DIV_19_2_MHZ;
|
||||
__raw_writel(v, usbother_base + MXC_USB_PHY_CTR_FUNC2_OFFSET);
|
||||
iounmap(usb_base);
|
||||
|
||||
mdelay(10);
|
||||
|
||||
return mx51_initialize_usb_hw(0, MXC_EHCI_INTERNAL_PHY);
|
||||
}
|
||||
|
||||
static int initialize_usbh1_port(struct platform_device *pdev)
|
||||
{
|
||||
u32 v;
|
||||
void __iomem *usb_base;
|
||||
void __iomem *usbother_base;
|
||||
|
||||
usb_base = ioremap(MX51_USB_OTG_BASE_ADDR, SZ_4K);
|
||||
if (!usb_base)
|
||||
return -ENOMEM;
|
||||
usbother_base = usb_base + MX5_USBOTHER_REGS_OFFSET;
|
||||
|
||||
/* The clock for the USBH1 ULPI port will come externally from the PHY. */
|
||||
v = __raw_readl(usbother_base + MX51_USB_CTRL_1_OFFSET);
|
||||
__raw_writel(v | MX51_USB_CTRL_UH1_EXT_CLK_EN, usbother_base + MX51_USB_CTRL_1_OFFSET);
|
||||
iounmap(usb_base);
|
||||
|
||||
mdelay(10);
|
||||
|
||||
return mx51_initialize_usb_hw(1, MXC_EHCI_POWER_PINS_ENABLED |
|
||||
MXC_EHCI_ITC_NO_THRESHOLD);
|
||||
}
|
||||
|
||||
static const struct mxc_usbh_platform_data dr_utmi_config __initconst = {
|
||||
.init = initialize_otg_port,
|
||||
.portsc = MXC_EHCI_UTMI_16BIT,
|
||||
};
|
||||
|
||||
static const struct fsl_usb2_platform_data usb_pdata __initconst = {
|
||||
.operating_mode = FSL_USB2_DR_DEVICE,
|
||||
.phy_mode = FSL_USB2_PHY_UTMI_WIDE,
|
||||
};
|
||||
|
||||
static const struct mxc_usbh_platform_data usbh1_config __initconst = {
|
||||
.init = initialize_usbh1_port,
|
||||
.portsc = MXC_EHCI_MODE_ULPI,
|
||||
};
|
||||
|
||||
static int otg_mode_host;
|
||||
|
||||
static int __init eukrea_cpuimx51_otg_mode(char *options)
|
||||
{
|
||||
if (!strcmp(options, "host"))
|
||||
otg_mode_host = 1;
|
||||
else if (!strcmp(options, "device"))
|
||||
otg_mode_host = 0;
|
||||
else
|
||||
pr_info("otg_mode neither \"host\" nor \"device\". "
|
||||
"Defaulting to device\n");
|
||||
return 0;
|
||||
}
|
||||
__setup("otg_mode=", eukrea_cpuimx51_otg_mode);
|
||||
|
||||
/*
|
||||
* Board specific initialization.
|
||||
*/
|
||||
static void __init eukrea_cpuimx51_init(void)
|
||||
{
|
||||
imx51_soc_init();
|
||||
|
||||
mxc_iomux_v3_setup_multiple_pads(eukrea_cpuimx51_pads,
|
||||
ARRAY_SIZE(eukrea_cpuimx51_pads));
|
||||
|
||||
imx51_add_imx_uart(0, &uart_pdata);
|
||||
imx51_add_mxc_nand(&eukrea_cpuimx51_nand_board_info);
|
||||
|
||||
gpio_request(CPUIMX51_QUARTA_GPIO, "quarta_irq");
|
||||
gpio_direction_input(CPUIMX51_QUARTA_GPIO);
|
||||
gpio_free(CPUIMX51_QUARTA_GPIO);
|
||||
gpio_request(CPUIMX51_QUARTB_GPIO, "quartb_irq");
|
||||
gpio_direction_input(CPUIMX51_QUARTB_GPIO);
|
||||
gpio_free(CPUIMX51_QUARTB_GPIO);
|
||||
gpio_request(CPUIMX51_QUARTC_GPIO, "quartc_irq");
|
||||
gpio_direction_input(CPUIMX51_QUARTC_GPIO);
|
||||
gpio_free(CPUIMX51_QUARTC_GPIO);
|
||||
gpio_request(CPUIMX51_QUARTD_GPIO, "quartd_irq");
|
||||
gpio_direction_input(CPUIMX51_QUARTD_GPIO);
|
||||
gpio_free(CPUIMX51_QUARTD_GPIO);
|
||||
|
||||
imx51_add_fec(NULL);
|
||||
platform_add_devices(devices, ARRAY_SIZE(devices));
|
||||
|
||||
imx51_add_imx_i2c(1, &eukrea_cpuimx51_i2c_data);
|
||||
i2c_register_board_info(1, eukrea_cpuimx51_i2c_devices,
|
||||
ARRAY_SIZE(eukrea_cpuimx51_i2c_devices));
|
||||
|
||||
if (otg_mode_host)
|
||||
imx51_add_mxc_ehci_otg(&dr_utmi_config);
|
||||
else {
|
||||
initialize_otg_port(NULL);
|
||||
imx51_add_fsl_usb2_udc(&usb_pdata);
|
||||
}
|
||||
imx51_add_mxc_ehci_hs(1, &usbh1_config);
|
||||
|
||||
#ifdef CONFIG_MACH_EUKREA_MBIMX51_BASEBOARD
|
||||
eukrea_mbimx51_baseboard_init();
|
||||
#endif
|
||||
}
|
||||
|
||||
static void __init eukrea_cpuimx51_timer_init(void)
|
||||
{
|
||||
mx51_clocks_init(32768, 24000000, 22579200, 0);
|
||||
}
|
||||
|
||||
static struct sys_timer mxc_timer = {
|
||||
.init = eukrea_cpuimx51_timer_init,
|
||||
};
|
||||
|
||||
MACHINE_START(EUKREA_CPUIMX51, "Eukrea CPUIMX51 Module")
|
||||
/* Maintainer: Eric Bénard <eric@eukrea.com> */
|
||||
.atag_offset = 0x100,
|
||||
.map_io = mx51_map_io,
|
||||
.init_early = imx51_init_early,
|
||||
.init_irq = mx51_init_irq,
|
||||
.handle_irq = imx51_handle_irq,
|
||||
.timer = &mxc_timer,
|
||||
.init_machine = eukrea_cpuimx51_init,
|
||||
MACHINE_END
|
||||
338
arch/arm/mach-imx/mach-cpuimx51sd.c
Normal file
338
arch/arm/mach-imx/mach-cpuimx51sd.c
Normal file
|
|
@ -0,0 +1,338 @@
|
|||
/*
|
||||
*
|
||||
* Copyright (C) 2010 Eric Bénard <eric@eukrea.com>
|
||||
*
|
||||
* based on board-mx51_babbage.c which is
|
||||
* Copyright 2009 Freescale Semiconductor, Inc. All Rights Reserved.
|
||||
* Copyright (C) 2009-2010 Amit Kucheria <amit.kucheria@canonical.com>
|
||||
*
|
||||
* The code contained herein is licensed under the GNU General Public
|
||||
* License. You may obtain a copy of the GNU General Public License
|
||||
* Version 2 or later at the following locations:
|
||||
*
|
||||
* http://www.opensource.org/licenses/gpl-license.html
|
||||
* http://www.gnu.org/copyleft/gpl.html
|
||||
*/
|
||||
|
||||
#include <linux/init.h>
|
||||
#include <linux/platform_device.h>
|
||||
#include <linux/i2c.h>
|
||||
#include <linux/i2c/tsc2007.h>
|
||||
#include <linux/gpio.h>
|
||||
#include <linux/delay.h>
|
||||
#include <linux/io.h>
|
||||
#include <linux/interrupt.h>
|
||||
#include <linux/i2c-gpio.h>
|
||||
#include <linux/spi/spi.h>
|
||||
#include <linux/can/platform/mcp251x.h>
|
||||
|
||||
#include <mach/eukrea-baseboards.h>
|
||||
#include <mach/common.h>
|
||||
#include <mach/hardware.h>
|
||||
#include <mach/iomux-mx51.h>
|
||||
|
||||
#include <asm/setup.h>
|
||||
#include <asm/mach-types.h>
|
||||
#include <asm/mach/arch.h>
|
||||
#include <asm/mach/time.h>
|
||||
|
||||
#include "devices-imx51.h"
|
||||
#include "cpu_op-mx51.h"
|
||||
|
||||
#define USBH1_RST IMX_GPIO_NR(2, 28)
|
||||
#define ETH_RST IMX_GPIO_NR(2, 31)
|
||||
#define TSC2007_IRQGPIO IMX_GPIO_NR(3, 12)
|
||||
#define CAN_IRQGPIO IMX_GPIO_NR(1, 1)
|
||||
#define CAN_RST IMX_GPIO_NR(4, 15)
|
||||
#define CAN_NCS IMX_GPIO_NR(4, 24)
|
||||
#define CAN_RXOBF IMX_GPIO_NR(1, 4)
|
||||
#define CAN_RX1BF IMX_GPIO_NR(1, 6)
|
||||
#define CAN_TXORTS IMX_GPIO_NR(1, 7)
|
||||
#define CAN_TX1RTS IMX_GPIO_NR(1, 8)
|
||||
#define CAN_TX2RTS IMX_GPIO_NR(1, 9)
|
||||
#define I2C_SCL IMX_GPIO_NR(4, 16)
|
||||
#define I2C_SDA IMX_GPIO_NR(4, 17)
|
||||
|
||||
/* USB_CTRL_1 */
|
||||
#define MX51_USB_CTRL_1_OFFSET 0x10
|
||||
#define MX51_USB_CTRL_UH1_EXT_CLK_EN (1 << 25)
|
||||
|
||||
#define MX51_USB_PLLDIV_12_MHZ 0x00
|
||||
#define MX51_USB_PLL_DIV_19_2_MHZ 0x01
|
||||
#define MX51_USB_PLL_DIV_24_MHZ 0x02
|
||||
|
||||
static iomux_v3_cfg_t eukrea_cpuimx51sd_pads[] = {
|
||||
/* UART1 */
|
||||
MX51_PAD_UART1_RXD__UART1_RXD,
|
||||
MX51_PAD_UART1_TXD__UART1_TXD,
|
||||
MX51_PAD_UART1_RTS__UART1_RTS,
|
||||
MX51_PAD_UART1_CTS__UART1_CTS,
|
||||
|
||||
/* USB HOST1 */
|
||||
MX51_PAD_USBH1_CLK__USBH1_CLK,
|
||||
MX51_PAD_USBH1_DIR__USBH1_DIR,
|
||||
MX51_PAD_USBH1_NXT__USBH1_NXT,
|
||||
MX51_PAD_USBH1_DATA0__USBH1_DATA0,
|
||||
MX51_PAD_USBH1_DATA1__USBH1_DATA1,
|
||||
MX51_PAD_USBH1_DATA2__USBH1_DATA2,
|
||||
MX51_PAD_USBH1_DATA3__USBH1_DATA3,
|
||||
MX51_PAD_USBH1_DATA4__USBH1_DATA4,
|
||||
MX51_PAD_USBH1_DATA5__USBH1_DATA5,
|
||||
MX51_PAD_USBH1_DATA6__USBH1_DATA6,
|
||||
MX51_PAD_USBH1_DATA7__USBH1_DATA7,
|
||||
MX51_PAD_USBH1_STP__USBH1_STP,
|
||||
MX51_PAD_EIM_CS3__GPIO2_28, /* PHY nRESET */
|
||||
|
||||
/* FEC */
|
||||
MX51_PAD_EIM_DTACK__GPIO2_31, /* PHY nRESET */
|
||||
|
||||
/* HSI2C */
|
||||
MX51_PAD_I2C1_CLK__GPIO4_16,
|
||||
MX51_PAD_I2C1_DAT__GPIO4_17,
|
||||
|
||||
/* CAN */
|
||||
MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI,
|
||||
MX51_PAD_CSPI1_MISO__ECSPI1_MISO,
|
||||
MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK,
|
||||
MX51_PAD_CSPI1_SS0__GPIO4_24, /* nCS */
|
||||
MX51_PAD_CSI2_PIXCLK__GPIO4_15, /* nReset */
|
||||
MX51_PAD_GPIO1_1__GPIO1_1, /* IRQ */
|
||||
MX51_PAD_GPIO1_4__GPIO1_4, /* Control signals */
|
||||
MX51_PAD_GPIO1_6__GPIO1_6,
|
||||
MX51_PAD_GPIO1_7__GPIO1_7,
|
||||
MX51_PAD_GPIO1_8__GPIO1_8,
|
||||
MX51_PAD_GPIO1_9__GPIO1_9,
|
||||
|
||||
/* Touchscreen */
|
||||
/* IRQ */
|
||||
NEW_PAD_CTRL(MX51_PAD_GPIO_NAND__GPIO_NAND, PAD_CTL_PUS_22K_UP |
|
||||
PAD_CTL_PKE | PAD_CTL_SRE_FAST |
|
||||
PAD_CTL_DSE_HIGH | PAD_CTL_PUE | PAD_CTL_HYS),
|
||||
};
|
||||
|
||||
static const struct imxuart_platform_data uart_pdata __initconst = {
|
||||
.flags = IMXUART_HAVE_RTSCTS,
|
||||
};
|
||||
|
||||
static struct tsc2007_platform_data tsc2007_info = {
|
||||
.model = 2007,
|
||||
.x_plate_ohms = 180,
|
||||
};
|
||||
|
||||
static struct i2c_board_info eukrea_cpuimx51sd_i2c_devices[] = {
|
||||
{
|
||||
I2C_BOARD_INFO("pcf8563", 0x51),
|
||||
}, {
|
||||
I2C_BOARD_INFO("tsc2007", 0x49),
|
||||
.type = "tsc2007",
|
||||
.platform_data = &tsc2007_info,
|
||||
.irq = IMX_GPIO_TO_IRQ(TSC2007_IRQGPIO),
|
||||
},
|
||||
};
|
||||
|
||||
static const struct mxc_nand_platform_data
|
||||
eukrea_cpuimx51sd_nand_board_info __initconst = {
|
||||
.width = 1,
|
||||
.hw_ecc = 1,
|
||||
.flash_bbt = 1,
|
||||
};
|
||||
|
||||
/* This function is board specific as the bit mask for the plldiv will also
|
||||
be different for other Freescale SoCs, thus a common bitmask is not
|
||||
possible and cannot get place in /plat-mxc/ehci.c.*/
|
||||
static int initialize_otg_port(struct platform_device *pdev)
|
||||
{
|
||||
u32 v;
|
||||
void __iomem *usb_base;
|
||||
void __iomem *usbother_base;
|
||||
|
||||
usb_base = ioremap(MX51_USB_OTG_BASE_ADDR, SZ_4K);
|
||||
if (!usb_base)
|
||||
return -ENOMEM;
|
||||
usbother_base = usb_base + MX5_USBOTHER_REGS_OFFSET;
|
||||
|
||||
/* Set the PHY clock to 19.2MHz */
|
||||
v = __raw_readl(usbother_base + MXC_USB_PHY_CTR_FUNC2_OFFSET);
|
||||
v &= ~MX5_USB_UTMI_PHYCTRL1_PLLDIV_MASK;
|
||||
v |= MX51_USB_PLL_DIV_19_2_MHZ;
|
||||
__raw_writel(v, usbother_base + MXC_USB_PHY_CTR_FUNC2_OFFSET);
|
||||
iounmap(usb_base);
|
||||
|
||||
mdelay(10);
|
||||
|
||||
return mx51_initialize_usb_hw(0, MXC_EHCI_INTERNAL_PHY);
|
||||
}
|
||||
|
||||
static int initialize_usbh1_port(struct platform_device *pdev)
|
||||
{
|
||||
u32 v;
|
||||
void __iomem *usb_base;
|
||||
void __iomem *usbother_base;
|
||||
|
||||
usb_base = ioremap(MX51_USB_OTG_BASE_ADDR, SZ_4K);
|
||||
if (!usb_base)
|
||||
return -ENOMEM;
|
||||
usbother_base = usb_base + MX5_USBOTHER_REGS_OFFSET;
|
||||
|
||||
/* The clock for the USBH1 ULPI port will come from the PHY. */
|
||||
v = __raw_readl(usbother_base + MX51_USB_CTRL_1_OFFSET);
|
||||
__raw_writel(v | MX51_USB_CTRL_UH1_EXT_CLK_EN,
|
||||
usbother_base + MX51_USB_CTRL_1_OFFSET);
|
||||
iounmap(usb_base);
|
||||
|
||||
mdelay(10);
|
||||
|
||||
return mx51_initialize_usb_hw(1, MXC_EHCI_POWER_PINS_ENABLED |
|
||||
MXC_EHCI_ITC_NO_THRESHOLD);
|
||||
}
|
||||
|
||||
static const struct mxc_usbh_platform_data dr_utmi_config __initconst = {
|
||||
.init = initialize_otg_port,
|
||||
.portsc = MXC_EHCI_UTMI_16BIT,
|
||||
};
|
||||
|
||||
static const struct fsl_usb2_platform_data usb_pdata __initconst = {
|
||||
.operating_mode = FSL_USB2_DR_DEVICE,
|
||||
.phy_mode = FSL_USB2_PHY_UTMI_WIDE,
|
||||
};
|
||||
|
||||
static const struct mxc_usbh_platform_data usbh1_config __initconst = {
|
||||
.init = initialize_usbh1_port,
|
||||
.portsc = MXC_EHCI_MODE_ULPI,
|
||||
};
|
||||
|
||||
static int otg_mode_host;
|
||||
|
||||
static int __init eukrea_cpuimx51sd_otg_mode(char *options)
|
||||
{
|
||||
if (!strcmp(options, "host"))
|
||||
otg_mode_host = 1;
|
||||
else if (!strcmp(options, "device"))
|
||||
otg_mode_host = 0;
|
||||
else
|
||||
pr_info("otg_mode neither \"host\" nor \"device\". "
|
||||
"Defaulting to device\n");
|
||||
return 0;
|
||||
}
|
||||
__setup("otg_mode=", eukrea_cpuimx51sd_otg_mode);
|
||||
|
||||
static struct i2c_gpio_platform_data pdata = {
|
||||
.sda_pin = I2C_SDA,
|
||||
.sda_is_open_drain = 0,
|
||||
.scl_pin = I2C_SCL,
|
||||
.scl_is_open_drain = 0,
|
||||
.udelay = 2,
|
||||
};
|
||||
|
||||
static struct platform_device hsi2c_gpio_device = {
|
||||
.name = "i2c-gpio",
|
||||
.id = 0,
|
||||
.dev.platform_data = &pdata,
|
||||
};
|
||||
|
||||
static struct mcp251x_platform_data mcp251x_info = {
|
||||
.oscillator_frequency = 24E6,
|
||||
};
|
||||
|
||||
static struct spi_board_info cpuimx51sd_spi_device[] = {
|
||||
{
|
||||
.modalias = "mcp2515",
|
||||
.max_speed_hz = 10000000,
|
||||
.bus_num = 0,
|
||||
.mode = SPI_MODE_0,
|
||||
.chip_select = 0,
|
||||
.platform_data = &mcp251x_info,
|
||||
.irq = IMX_GPIO_TO_IRQ(CAN_IRQGPIO)
|
||||
},
|
||||
};
|
||||
|
||||
static int cpuimx51sd_spi1_cs[] = {
|
||||
CAN_NCS,
|
||||
};
|
||||
|
||||
static const struct spi_imx_master cpuimx51sd_ecspi1_pdata __initconst = {
|
||||
.chipselect = cpuimx51sd_spi1_cs,
|
||||
.num_chipselect = ARRAY_SIZE(cpuimx51sd_spi1_cs),
|
||||
};
|
||||
|
||||
static struct platform_device *platform_devices[] __initdata = {
|
||||
&hsi2c_gpio_device,
|
||||
};
|
||||
|
||||
static void __init eukrea_cpuimx51sd_init(void)
|
||||
{
|
||||
imx51_soc_init();
|
||||
|
||||
mxc_iomux_v3_setup_multiple_pads(eukrea_cpuimx51sd_pads,
|
||||
ARRAY_SIZE(eukrea_cpuimx51sd_pads));
|
||||
|
||||
#if defined(CONFIG_CPU_FREQ_IMX)
|
||||
get_cpu_op = mx51_get_cpu_op;
|
||||
#endif
|
||||
|
||||
imx51_add_imx_uart(0, &uart_pdata);
|
||||
imx51_add_mxc_nand(&eukrea_cpuimx51sd_nand_board_info);
|
||||
|
||||
gpio_request(ETH_RST, "eth_rst");
|
||||
gpio_set_value(ETH_RST, 1);
|
||||
imx51_add_fec(NULL);
|
||||
|
||||
gpio_request(CAN_IRQGPIO, "can_irq");
|
||||
gpio_direction_input(CAN_IRQGPIO);
|
||||
gpio_free(CAN_IRQGPIO);
|
||||
gpio_request(CAN_NCS, "can_ncs");
|
||||
gpio_direction_output(CAN_NCS, 1);
|
||||
gpio_free(CAN_NCS);
|
||||
gpio_request(CAN_RST, "can_rst");
|
||||
gpio_direction_output(CAN_RST, 0);
|
||||
msleep(20);
|
||||
gpio_set_value(CAN_RST, 1);
|
||||
imx51_add_ecspi(0, &cpuimx51sd_ecspi1_pdata);
|
||||
spi_register_board_info(cpuimx51sd_spi_device,
|
||||
ARRAY_SIZE(cpuimx51sd_spi_device));
|
||||
|
||||
gpio_request(TSC2007_IRQGPIO, "tsc2007_irq");
|
||||
gpio_direction_input(TSC2007_IRQGPIO);
|
||||
gpio_free(TSC2007_IRQGPIO);
|
||||
|
||||
i2c_register_board_info(0, eukrea_cpuimx51sd_i2c_devices,
|
||||
ARRAY_SIZE(eukrea_cpuimx51sd_i2c_devices));
|
||||
platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices));
|
||||
|
||||
if (otg_mode_host)
|
||||
imx51_add_mxc_ehci_otg(&dr_utmi_config);
|
||||
else {
|
||||
initialize_otg_port(NULL);
|
||||
imx51_add_fsl_usb2_udc(&usb_pdata);
|
||||
}
|
||||
|
||||
gpio_request(USBH1_RST, "usb_rst");
|
||||
gpio_direction_output(USBH1_RST, 0);
|
||||
msleep(20);
|
||||
gpio_set_value(USBH1_RST, 1);
|
||||
imx51_add_mxc_ehci_hs(1, &usbh1_config);
|
||||
|
||||
#ifdef CONFIG_MACH_EUKREA_MBIMXSD51_BASEBOARD
|
||||
eukrea_mbimxsd51_baseboard_init();
|
||||
#endif
|
||||
}
|
||||
|
||||
static void __init eukrea_cpuimx51sd_timer_init(void)
|
||||
{
|
||||
mx51_clocks_init(32768, 24000000, 22579200, 0);
|
||||
}
|
||||
|
||||
static struct sys_timer mxc_timer = {
|
||||
.init = eukrea_cpuimx51sd_timer_init,
|
||||
};
|
||||
|
||||
MACHINE_START(EUKREA_CPUIMX51SD, "Eukrea CPUIMX51SD")
|
||||
/* Maintainer: Eric Bénard <eric@eukrea.com> */
|
||||
.atag_offset = 0x100,
|
||||
.map_io = mx51_map_io,
|
||||
.init_early = imx51_init_early,
|
||||
.init_irq = mx51_init_irq,
|
||||
.handle_irq = imx51_handle_irq,
|
||||
.timer = &mxc_timer,
|
||||
.init_machine = eukrea_cpuimx51sd_init,
|
||||
MACHINE_END
|
||||
Some files were not shown because too many files have changed in this diff Show more
Loading…
Reference in a new issue