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msm: kgsl: Add apb_pclk to the clock list and increase max clock count

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KGSL needs to enable apb_pclk for QDSS register access.
Add apb_pclk to the clock list. Increment KGSL_MAX_CLKS
and MAX_GMU_CLKS to support apb_clk.

Change-Id: I9a98fa7ef09f98bdd0897a9cd1dd51b6468a5a51
Signed-off-by: Harshitha Sai Neelati <hsaine@codeaurora.org>
Signed-off-by: Kamal Agrawal <kamaagra@codeaurora.org>
This commit is contained in:
Kamal Agrawal 2020-12-14 14:55:51 +05:30
commit 7753178030
3 changed files with 7 additions and 6 deletions
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4
drivers/gpu/msm/kgsl_gmu.h
View file

@ -1,4 +1,4 @@
/* Copyright (c) 2017-2018, The Linux Foundation. All rights reserved.
/* Copyright (c) 2017-2018, 2020, The Linux Foundation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
@ -142,7 +142,7 @@ struct rpmh_votes_t {
struct gmu_bw_votes cnoc_votes;
};
#define MAX_GMU_CLKS 6
#define MAX_GMU_CLKS 7
#define DEFAULT_GMU_FREQ_IDX 1
/*

5
drivers/gpu/msm/kgsl_pwrctrl.c
View file

@ -1,4 +1,4 @@
/* Copyright (c) 2010-2019, The Linux Foundation. All rights reserved.
/* Copyright (c) 2010-2020, The Linux Foundation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
@ -61,7 +61,8 @@ static const char * const clocks[] = {
"rbcpr_clk",
"iref_clk",
"gmu_clk",
"ahb_clk"
"ahb_clk",
"apb_pclk",
};
static unsigned long ib_votes[KGSL_MAX_BUSLEVELS];

4
drivers/gpu/msm/kgsl_pwrctrl.h
View file

@ -1,4 +1,4 @@
/* Copyright (c) 2010-2019, The Linux Foundation. All rights reserved.
/* Copyright (c) 2010-2020, The Linux Foundation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
@ -25,7 +25,7 @@
#define KGSL_PWR_ON 0xFFFF
#define KGSL_MAX_CLKS 16
#define KGSL_MAX_CLKS 17
#define KGSL_MAX_REGULATORS 2
#define KGSL_MAX_PWRLEVELS 10