debugfs: Pass bool pointer to debugfs_create_bool()
Its a bit odd that debugfs_create_bool() takes 'u32 *' as an argument,
when all it needs is a boolean pointer.
It would be better to update this API to make it accept 'bool *'
instead, as that will make it more consistent and often more convenient.
Over that bool takes just a byte.
That required updates to all user sites as well, in the same commit
updating the API. regmap core was also using
debugfs_{read|write}_file_bool(), directly and variable types were
updated for that to be bool as well.
Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>
Acked-by: Mark Brown <broonie@kernel.org>
Acked-by: Charles Keepax <ckeepax@opensource.wolfsonmicro.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
This commit is contained in:
parent
6e58f752a6
commit
621a5f7ad9
33 changed files with 78 additions and 78 deletions
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@ -105,7 +105,7 @@ a variable of type size_t.
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Boolean values can be placed in debugfs with:
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struct dentry *debugfs_create_bool(const char *name, umode_t mode,
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struct dentry *parent, u32 *value);
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struct dentry *parent, bool *value);
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A read on the resulting file will yield either Y (for non-zero values) or
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N, followed by a newline. If written to, it will accept either upper- or
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@ -58,7 +58,7 @@ static u32 mdscr_read(void)
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* Allow root to disable self-hosted debug from userspace.
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* This is useful if you want to connect an external JTAG debugger.
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*/
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static u32 debug_enabled = 1;
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static bool debug_enabled = true;
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static int create_debug_debugfs_entry(void)
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{
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@ -69,7 +69,7 @@ fs_initcall(create_debug_debugfs_entry);
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static int __init early_debug_disable(char *buf)
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{
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debug_enabled = 0;
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debug_enabled = false;
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return 0;
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}
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@ -138,7 +138,7 @@ struct acpi_ec {
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unsigned long gpe;
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unsigned long command_addr;
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unsigned long data_addr;
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u32 global_lock;
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bool global_lock;
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unsigned long flags;
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unsigned long reference_count;
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struct mutex mutex;
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@ -122,9 +122,9 @@ struct regmap {
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unsigned int num_reg_defaults_raw;
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/* if set, only the cache is modified not the HW */
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u32 cache_only;
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bool cache_only;
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/* if set, only the HW is modified not the cache */
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u32 cache_bypass;
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bool cache_bypass;
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/* if set, remember to free reg_defaults_raw */
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bool cache_free;
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@ -132,7 +132,7 @@ struct regmap {
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const void *reg_defaults_raw;
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void *cache;
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/* if set, the cache contains newer data than the HW */
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u32 cache_dirty;
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bool cache_dirty;
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/* if set, the HW registers are known to match map->reg_defaults */
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bool no_sync_defaults;
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@ -355,9 +355,9 @@ static int regcache_lzo_sync(struct regmap *map, unsigned int min,
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if (ret > 0 && val == map->reg_defaults[ret].def)
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continue;
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map->cache_bypass = 1;
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map->cache_bypass = true;
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ret = _regmap_write(map, i, val);
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map->cache_bypass = 0;
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map->cache_bypass = false;
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if (ret)
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return ret;
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dev_dbg(map->dev, "Synced register %#x, value %#x\n",
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@ -54,11 +54,11 @@ static int regcache_hw_init(struct regmap *map)
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return -ENOMEM;
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if (!map->reg_defaults_raw) {
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u32 cache_bypass = map->cache_bypass;
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bool cache_bypass = map->cache_bypass;
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dev_warn(map->dev, "No cache defaults, reading back from HW\n");
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/* Bypass the cache access till data read from HW*/
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map->cache_bypass = 1;
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map->cache_bypass = true;
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tmp_buf = kmalloc(map->cache_size_raw, GFP_KERNEL);
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if (!tmp_buf) {
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ret = -ENOMEM;
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@ -285,9 +285,9 @@ static int regcache_default_sync(struct regmap *map, unsigned int min,
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if (!regcache_reg_needs_sync(map, reg, val))
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continue;
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map->cache_bypass = 1;
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map->cache_bypass = true;
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ret = _regmap_write(map, reg, val);
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map->cache_bypass = 0;
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map->cache_bypass = false;
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if (ret) {
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dev_err(map->dev, "Unable to sync register %#x. %d\n",
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reg, ret);
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@ -315,7 +315,7 @@ int regcache_sync(struct regmap *map)
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int ret = 0;
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unsigned int i;
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const char *name;
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unsigned int bypass;
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bool bypass;
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BUG_ON(!map->cache_ops);
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@ -333,7 +333,7 @@ int regcache_sync(struct regmap *map)
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map->async = true;
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/* Apply any patch first */
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map->cache_bypass = 1;
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map->cache_bypass = true;
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for (i = 0; i < map->patch_regs; i++) {
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ret = _regmap_write(map, map->patch[i].reg, map->patch[i].def);
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if (ret != 0) {
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@ -342,7 +342,7 @@ int regcache_sync(struct regmap *map)
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goto out;
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}
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}
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map->cache_bypass = 0;
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map->cache_bypass = false;
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if (map->cache_ops->sync)
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ret = map->cache_ops->sync(map, 0, map->max_register);
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@ -384,7 +384,7 @@ int regcache_sync_region(struct regmap *map, unsigned int min,
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{
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int ret = 0;
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const char *name;
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unsigned int bypass;
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bool bypass;
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BUG_ON(!map->cache_ops);
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@ -637,11 +637,11 @@ static int regcache_sync_block_single(struct regmap *map, void *block,
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if (!regcache_reg_needs_sync(map, regtmp, val))
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continue;
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map->cache_bypass = 1;
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map->cache_bypass = true;
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ret = _regmap_write(map, regtmp, val);
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map->cache_bypass = 0;
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map->cache_bypass = false;
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if (ret != 0) {
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dev_err(map->dev, "Unable to sync register %#x. %d\n",
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regtmp, ret);
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@ -668,14 +668,14 @@ static int regcache_sync_block_raw_flush(struct regmap *map, const void **data,
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dev_dbg(map->dev, "Writing %zu bytes for %d registers from 0x%x-0x%x\n",
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count * val_bytes, count, base, cur - map->reg_stride);
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map->cache_bypass = 1;
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map->cache_bypass = true;
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ret = _regmap_raw_write(map, base, *data, count * val_bytes);
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if (ret)
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dev_err(map->dev, "Unable to sync registers %#x-%#x. %d\n",
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base, cur - map->reg_stride, ret);
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map->cache_bypass = 0;
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map->cache_bypass = false;
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*data = NULL;
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@ -80,8 +80,8 @@ struct qca_data {
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spinlock_t hci_ibs_lock; /* HCI_IBS state lock */
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u8 tx_ibs_state; /* HCI_IBS transmit side power state*/
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u8 rx_ibs_state; /* HCI_IBS receive side power state */
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u32 tx_vote; /* Clock must be on for TX */
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u32 rx_vote; /* Clock must be on for RX */
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bool tx_vote; /* Clock must be on for TX */
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bool rx_vote; /* Clock must be on for RX */
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struct timer_list tx_idle_timer;
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u32 tx_idle_delay;
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struct timer_list wake_retrans_timer;
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@ -138,7 +138,7 @@ u16 amd_iommu_last_bdf; /* largest PCI device id we have
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to handle */
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LIST_HEAD(amd_iommu_unity_map); /* a list of required unity mappings
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we find in ACPI */
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u32 amd_iommu_unmap_flush; /* if true, flush on every unmap */
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bool amd_iommu_unmap_flush; /* if true, flush on every unmap */
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LIST_HEAD(amd_iommu_list); /* list of all AMD IOMMUs in the
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system */
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@ -674,7 +674,7 @@ extern unsigned long *amd_iommu_pd_alloc_bitmap;
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* If true, the addresses will be flushed on unmap time, not when
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* they are reused
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*/
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extern u32 amd_iommu_unmap_flush;
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extern bool amd_iommu_unmap_flush;
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/* Smallest max PASID supported by any IOMMU in the system */
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extern u32 amd_iommu_max_pasid;
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@ -528,7 +528,7 @@ struct mei_device {
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DECLARE_BITMAP(host_clients_map, MEI_CLIENTS_MAX);
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unsigned long me_client_index;
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u32 allow_fixed_address;
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bool allow_fixed_address;
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struct mei_cl wd_cl;
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enum mei_wd_states wd_state;
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@ -767,8 +767,8 @@ struct adapter {
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bool tid_release_task_busy;
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struct dentry *debugfs_root;
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u32 use_bd; /* Use SGE Back Door intfc for reading SGE Contexts */
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u32 trace_rss; /* 1 implies that different RSS flit per filter is
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bool use_bd; /* Use SGE Back Door intfc for reading SGE Contexts */
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bool trace_rss; /* 1 implies that different RSS flit per filter is
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* used per filter else if 0 default RSS flit is
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* used for all 4 filters.
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*/
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@ -680,7 +680,7 @@ struct ath10k {
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bool monitor_started;
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unsigned int filter_flags;
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unsigned long dev_flags;
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u32 dfs_block_radar_events;
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bool dfs_block_radar_events;
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/* protected by conf_mutex */
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bool radar_enabled;
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@ -1367,7 +1367,7 @@ struct ath5k_hw {
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u8 ah_retry_long;
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u8 ah_retry_short;
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u32 ah_use_32khz_clock;
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bool ah_use_32khz_clock;
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u8 ah_coverage_class;
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bool ah_ack_bitrate_high;
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@ -385,7 +385,7 @@ static void ath9k_hw_init_config(struct ath_hw *ah)
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ah->config.dma_beacon_response_time = 1;
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ah->config.sw_beacon_response_time = 6;
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ah->config.cwm_ignore_extcca = 0;
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ah->config.cwm_ignore_extcca = false;
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ah->config.analog_shiftreg = 1;
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ah->config.rx_intr_mitigation = true;
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@ -332,14 +332,14 @@ enum ath9k_hw_hang_checks {
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struct ath9k_ops_config {
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int dma_beacon_response_time;
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int sw_beacon_response_time;
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u32 cwm_ignore_extcca;
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bool cwm_ignore_extcca;
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u32 pcie_waen;
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u8 analog_shiftreg;
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u32 ofdm_trig_low;
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u32 ofdm_trig_high;
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u32 cck_trig_high;
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u32 cck_trig_low;
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u32 enable_paprd;
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bool enable_paprd;
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int serialize_regmode;
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bool rx_intr_mitigation;
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bool tx_intr_mitigation;
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@ -676,15 +676,15 @@ static void b43_add_dynamic_debug(struct b43_wldev *dev)
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e->dyn_debug_dentries[id] = d; \
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} while (0)
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add_dyn_dbg("debug_xmitpower", B43_DBG_XMITPOWER, 0);
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add_dyn_dbg("debug_dmaoverflow", B43_DBG_DMAOVERFLOW, 0);
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add_dyn_dbg("debug_dmaverbose", B43_DBG_DMAVERBOSE, 0);
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add_dyn_dbg("debug_pwork_fast", B43_DBG_PWORK_FAST, 0);
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add_dyn_dbg("debug_pwork_stop", B43_DBG_PWORK_STOP, 0);
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add_dyn_dbg("debug_lo", B43_DBG_LO, 0);
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add_dyn_dbg("debug_firmware", B43_DBG_FIRMWARE, 0);
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add_dyn_dbg("debug_keys", B43_DBG_KEYS, 0);
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add_dyn_dbg("debug_verbose_stats", B43_DBG_VERBOSESTATS, 0);
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add_dyn_dbg("debug_xmitpower", B43_DBG_XMITPOWER, false);
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add_dyn_dbg("debug_dmaoverflow", B43_DBG_DMAOVERFLOW, false);
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add_dyn_dbg("debug_dmaverbose", B43_DBG_DMAVERBOSE, false);
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add_dyn_dbg("debug_pwork_fast", B43_DBG_PWORK_FAST, false);
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add_dyn_dbg("debug_pwork_stop", B43_DBG_PWORK_STOP, false);
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add_dyn_dbg("debug_lo", B43_DBG_LO, false);
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add_dyn_dbg("debug_firmware", B43_DBG_FIRMWARE, false);
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add_dyn_dbg("debug_keys", B43_DBG_KEYS, false);
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add_dyn_dbg("debug_verbose_stats", B43_DBG_VERBOSESTATS, false);
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#undef add_dyn_dbg
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}
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@ -68,7 +68,7 @@ struct b43_dfsentry {
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u32 shm32read_addr_next;
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/* Enabled/Disabled list for the dynamic debugging features. */
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u32 dyn_debug[__B43_NR_DYNDBG];
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bool dyn_debug[__B43_NR_DYNDBG];
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/* Dentries for the dynamic debugging entries. */
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struct dentry *dyn_debug_dentries[__B43_NR_DYNDBG];
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};
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@ -369,11 +369,11 @@ static void b43legacy_add_dynamic_debug(struct b43legacy_wldev *dev)
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e->dyn_debug_dentries[id] = d; \
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} while (0)
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add_dyn_dbg("debug_xmitpower", B43legacy_DBG_XMITPOWER, 0);
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add_dyn_dbg("debug_dmaoverflow", B43legacy_DBG_DMAOVERFLOW, 0);
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add_dyn_dbg("debug_dmaverbose", B43legacy_DBG_DMAVERBOSE, 0);
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add_dyn_dbg("debug_pwork_fast", B43legacy_DBG_PWORK_FAST, 0);
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add_dyn_dbg("debug_pwork_stop", B43legacy_DBG_PWORK_STOP, 0);
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add_dyn_dbg("debug_xmitpower", B43legacy_DBG_XMITPOWER, false);
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add_dyn_dbg("debug_dmaoverflow", B43legacy_DBG_DMAOVERFLOW, false);
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add_dyn_dbg("debug_dmaverbose", B43legacy_DBG_DMAVERBOSE, false);
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add_dyn_dbg("debug_pwork_fast", B43legacy_DBG_PWORK_FAST, false);
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add_dyn_dbg("debug_pwork_stop", B43legacy_DBG_PWORK_STOP, false);
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#undef add_dyn_dbg
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}
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@ -47,7 +47,7 @@ struct b43legacy_dfsentry {
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struct b43legacy_txstatus_log txstatlog;
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/* Enabled/Disabled list for the dynamic debugging features. */
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u32 dyn_debug[__B43legacy_NR_DYNDBG];
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bool dyn_debug[__B43legacy_NR_DYNDBG];
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/* Dentries for the dynamic debugging entries. */
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struct dentry *dyn_debug_dentries[__B43legacy_NR_DYNDBG];
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};
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@ -1425,9 +1425,9 @@ struct il_priv {
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#endif /* CONFIG_IWLEGACY_DEBUGFS */
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struct work_struct txpower_work;
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u32 disable_sens_cal;
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u32 disable_chain_noise_cal;
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u32 disable_tx_power_cal;
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bool disable_sens_cal;
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bool disable_chain_noise_cal;
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bool disable_tx_power_cal;
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struct work_struct run_time_calib_work;
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struct timer_list stats_periodic;
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struct timer_list watchdog;
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