Merge remote-tracking branch 'common/android-4.9-q' into android13-4.9-sdm845
* common/android-4.9-q: Linux 4.9.335 v4l2: don't fall back to follow_pfn() if pin_user_pages_fast() fails proc: proc_skip_spaces() shouldn't think it is working on C strings proc: avoid integer type confusion in get_proc_long x86/ioremap: Fix page aligned size calculation in __ioremap_caller() Bluetooth: L2CAP: Fix accepting connection request for invalid SPSM x86/pm: Add enumeration check before spec MSRs save/restore setup x86/tsx: Add a feature bit for TSX control MSR support Revert "fbdev: fb_pm2fb: Avoid potential divide by zero error" tcp/udp: Fix memory leak in ipv6_renew_options(). iommu/vt-d: Fix PCI device refcount leak in dmar_dev_scope_init() pinctrl: single: Fix potential division by zero ASoC: ops: Fix bounds check for _sx controls arm64: errata: Fix KVM Spectre-v2 mitigation selection for Cortex-A57/A72 arm64: Fix panic() when Spectre-v2 causes Spectre-BHB to re-allocate KVM vectors nilfs2: fix NULL pointer dereference in nilfs_palloc_commit_free_entry() tools/vm/slabinfo-gnuplot: use "grep -E" instead of "egrep" btrfs: qgroup: fix sleep from invalid context bug in btrfs_qgroup_inherit() hwmon: (coretemp) fix pci device refcount leak in nv1a_ram_new() hwmon: (coretemp) Check for null before removing sysfs attrs net: ethernet: renesas: ravb: Fix promiscuous mode after system resumed packet: do not set TP_STATUS_CSUM_VALID on CHECKSUM_COMPLETE net: hsr: Fix potential use-after-free net/9p: Fix a potential socket leak in p9_socket_open net: net_netdev: Fix error handling in ntb_netdev_init_module() net: phy: fix null-ptr-deref while probe() failed qlcnic: fix sleep-in-atomic-context bugs caused by msleep can: cc770: cc770_isa_probe(): add missing free_cc770dev() can: sja1000_isa: sja1000_isa_probe(): add missing free_sja1000dev() net/mlx5: Fix uninitialized variable bug in outlen_write() hwmon: (ibmpex) Fix possible UAF when ibmpex_register_bmc() fails hwmon: (i5500_temp) fix missing pci_disable_device() iio: health: afe4404: Fix oob read in afe4404_[read|write]_raw iio: health: afe4403: Fix oob read in afe4403_read_raw drm/amdgpu: always register an MMU notifier for userptr net: usb: qmi_wwan: add Telit 0x103a composition tcp: configurable source port perturb table size platform/x86: asus-wmi: add missing pci_dev_put() in asus_wmi_set_xusb2pr() xen/platform-pci: add missing free_irq() in error path serial: 8250: 8250_omap: Avoid RS485 RTS glitch on ->set_termios() nilfs2: fix nilfs_sufile_mark_dirty() not set segment usage as dirty nios2: add FORCE for vmlinuz.gz kconfig: display recursive dependency resolution hint just once iio: core: Fix entry not deleted when iio_register_sw_trigger_type() fails iio: light: apds9960: fix wrong register for gesture gain s390/crashdump: fix TOD programmable field size net: thunderx: Fix the ACPI memory leak nfc: st-nci: fix memory leaks in EVT_TRANSACTION nfc: st-nci: fix incorrect validating logic in EVT_TRANSACTION NFC: nci: fix memory leak in nci_rx_data_packet() xfrm: Fix ignored return value in xfrm6_init() net/qla3xxx: fix potential memleak in ql3xxx_send() net/mlx4: Check retval of mlx4_bitmap_init ARM: mxs: fix memory leak in mxs_machine_init() 9p/fd: fix issue of list_del corruption in p9_fd_cancel() net: pch_gbe: fix potential memleak in pch_gbe_tx_queue() nfc/nci: fix race with opening and closing ARM: dts: at91: sam9g20ek: enable udc vbus gpio pinctrl bus: sunxi-rsb: Support atomic transfers af_key: Fix send_acquire race with pfkey_register MIPS: pic32: treat port as signed integer wifi: mac80211: Fix ack frame idr leak when mesh has no route audit: fix undefined behavior in bit shift for AUDIT_BIT wifi: mac80211_hwsim: fix debugfs attribute ps with rc table support Linux 4.9.334 ntfs: check overflow when iterating ATTR_RECORDs ntfs: fix out-of-bounds read in ntfs_attr_find() ntfs: fix use-after-free in ntfs_attr_find() mm: fs: initialize fsdata passed to write_begin/write_end interface 9p/trans_fd: always use O_NONBLOCK read/write gfs2: Switch from strlcpy to strscpy gfs2: Check sb_bsize_shift after reading superblock 9p: trans_fd/p9_conn_cancel: drop client lock earlier kcm: avoid potential race in kcm_tx_work tcp: cdg: allow tcp_cdg_release() to be called multiple times serial: 8250: Flush DMA Rx on RLSI nilfs2: fix use-after-free bug of ns_writer on remount misc/vmw_vmci: fix an infoleak in vmci_host_do_receive_datagram() mmc: core: properly select voltage range without power cycle serial: 8250_lpss: Configure DMA also w/o DMA filter serial: 8250: Fall back to non-DMA Rx if IIR_RDI occurs dm ioctl: fix misbehavior if list_versions races with module loading iio: pressure: ms5611: changed hardcoded SPI speed to value limited iio: trigger: sysfs: fix possible memory leak in iio_sysfs_trig_init() iio: adc: at91_adc: fix possible memory leak in at91_adc_allocate_trigger() usb: chipidea: fix deadlock in ci_otg_del_timer usb: add NO_LPM quirk for Realforce 87U Keyboard USB: serial: option: add Fibocom FM160 0x0111 composition USB: serial: option: add u-blox LARA-L6 modem USB: serial: option: add u-blox LARA-R6 00B modem USB: serial: option: remove old LARA-R6 PID USB: serial: option: add Sierra Wireless EM9191 ALSA: usb-audio: Drop snd_BUG_ON() from snd_usbmidi_output_open() ring_buffer: Do not deactivate non-existant pages ftrace: Optimize the allocation for mcount entries ftrace: Fix the possible incorrect kernel message cifs: Fix wrong return value checking when GETFLAGS net/x25: Fix skb leak in x25_lapb_receive_frame() xen/pcpu: fix possible memory leak in register_pcpu() net: caif: fix double disconnect client in chnl_net_open() mISDN: fix misuse of put_device() in mISDN_register_device() mISDN: fix possible memory leak in mISDN_dsp_element_register() pinctrl: devicetree: fix null pointer dereferencing in pinctrl_dt_to_map parport_pc: Avoid FIFO port location truncation ASoC: soc-utils: Remove __exit for snd_soc_util_exit() tty: n_gsm: fix sleep-in-atomic-context bug in gsm_control_send serial: 8250: omap: Flush PM QOS work on remove serial: 8250_omap: remove wait loop from Errata i202 workaround ASoC: core: Fix use-after-free in snd_soc_exit() Bluetooth: L2CAP: Fix l2cap_global_chan_by_psm drm/imx: imx-tve: Fix return type of imx_tve_connector_mode_valid x86/cpu: Restore AMD's DE_CFG MSR after resume dmaengine: at_hdmac: Check return code of dma_async_device_register dmaengine: at_hdmac: Fix impossible condition dmaengine: at_hdmac: Don't allow CPU to reorder channel enable dmaengine: at_hdmac: Fix completion of unissued descriptor in case of errors dmaengine: at_hdmac: Don't start transactions at tx_submit level dmaengine: at_hdmac: Fix at_lli struct definition cert host tools: Stop complaining about deprecated OpenSSL functions udf: Fix a slab-out-of-bounds write bug in udf_find_entry() btrfs: selftests: fix wrong error check in btrfs_free_dummy_root() platform/x86: hp_wmi: Fix rfkill causing soft blocked wifi nilfs2: fix deadlock in nilfs_count_free_blocks() ALSA: usb-audio: Add quirk entry for M-Audio Micro ALSA: hda: fix potential memleak in 'add_widget_node' net: macvlan: fix memory leaks of macvlan_common_newlink net: mv643xx_eth: disable napi when init rxq or txq failed in mv643xx_eth_open() ethernet: s2io: disable napi when start nic failed in s2io_card_up() net: cxgb3_main: disable napi when bind qsets failed in cxgb_up() drivers: net: xgene: disable napi when register irq failed in xgene_enet_open() dmaengine: mv_xor_v2: Fix a resource leak in mv_xor_v2_remove() tipc: fix the msg->req tlv len check in tipc_nl_compat_name_table_dump_header ipv6: addrlabel: fix infoleak when sending struct ifaddrlblmsg to network hamradio: fix issue of dev reference count leakage in bpq_device_event() net: lapbether: fix issue of dev reference count leakage in lapbeth_device_event() capabilities: fix undefined behavior in bit shift for CAP_TO_MASK net: fman: Unregister ethernet device on removal bnxt_en: fix potentially incorrect return value for ndo_rx_flow_steer net: gso: fix panic on frag_list with mixed head alloc types HID: hyperv: fix possible memory leak in mousevsc_probe() Linux 4.9.333 wifi: brcmfmac: Fix potential buffer overflow in brcmf_fweh_event_worker() KVM: x86: emulator: update the emulation mode after CR0 write KVM: x86: emulator: introduce emulator_recalc_and_set_mode KVM: x86: emulator: em_sysexit should update ctxt->mode KVM: x86: Mask off reserved bits in CPUID.80000008H ext4: fix warning in 'ext4_da_release_space' parisc: Export iosapic_serial_irq() symbol for serial port driver parisc: Make 8250_gsc driver dependend on CONFIG_PARISC ALSA: usb-audio: Add quirks for MacroSilicon MS2100/MS2106 devices btrfs: fix type of parameter generation in btrfs_get_dentry Bluetooth: L2CAP: Fix attempting to access uninitialized memory i2c: xiic: Add platform module alias media: dvb-frontends/drxk: initialize err to 0 media: s5p_cec: limit msg.len to CEC_MAX_MSG_SIZE net: mdio: fix undefined behavior in bit shift for __mdiobus_register Bluetooth: L2CAP: fix use-after-free in l2cap_conn_del() Bluetooth: L2CAP: Fix use-after-free caused by l2cap_reassemble_sdu btrfs: fix ulist leaks in error paths of qgroup self tests isdn: mISDN: netjet: fix wrong check of device registration mISDN: fix possible memory leak in mISDN_register_device() rose: Fix NULL pointer dereference in rose_send_frame() ipvs: use explicitly signed chars net: sched: Fix use after free in red_enqueue() ata: pata_legacy: fix pdc20230_set_piomode() net: fec: fix improper use of NETDEV_TX_BUSY nfc: nfcmrvl: Fix potential memory leak in nfcmrvl_i2c_nci_send() nfc: s3fwrn5: Fix potential memory leak in s3fwrn5_nci_send() nfs4: Fix kmemleak when allocate slot failed NFSv4.1: We must always send RECLAIM_COMPLETE after a reboot NFSv4.1: Handle RECLAIM_COMPLETE trunking errors Change-Id: Ie30850b718c1347e040c5ef46ee50f1b81fe4fc6
This commit is contained in:
Michael Bestas
commit
4f33fe186c
150 changed files with 822 additions and 400 deletions
2
Makefile
2
Makefile
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@ -1,6 +1,6 @@
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VERSION = 4
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PATCHLEVEL = 9
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SUBLEVEL = 332
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SUBLEVEL = 335
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EXTRAVERSION =
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NAME = Roaring Lionus
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@ -39,6 +39,13 @@
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};
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usb1 {
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pinctrl_usb1_vbus_gpio: usb1_vbus_gpio {
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atmel,pins =
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<AT91_PIOC 5 AT91_PERIPH_GPIO AT91_PINCTRL_DEGLITCH>; /* PC5 GPIO */
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};
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};
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mmc0_slot1 {
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pinctrl_board_mmc0_slot1: mmc0_slot1-board {
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atmel,pins =
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@ -72,6 +79,8 @@
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};
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usb1: gadget@fffa4000 {
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pinctrl-0 = <&pinctrl_usb1_vbus_gpio>;
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pinctrl-names = "default";
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atmel,vbus-gpio = <&pioC 5 GPIO_ACTIVE_HIGH>;
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status = "okay";
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};
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@ -393,8 +393,10 @@ static void __init mxs_machine_init(void)
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root = of_find_node_by_path("/");
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ret = of_property_read_string(root, "model", &soc_dev_attr->machine);
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if (ret)
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if (ret) {
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kfree(soc_dev_attr);
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return;
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}
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soc_dev_attr->family = "Freescale MXS Family";
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soc_dev_attr->soc_id = mxs_get_soc_id();
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@ -129,10 +129,12 @@ static void __install_bp_hardening_cb(bp_hardening_cb_t fn,
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__copy_hyp_vect_bpi(slot, hyp_vecs_start, hyp_vecs_end);
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}
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__this_cpu_write(bp_hardening_data.hyp_vectors_slot, slot);
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__this_cpu_write(bp_hardening_data.fn, fn);
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__this_cpu_write(bp_hardening_data.template_start, hyp_vecs_start);
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__hardenbp_enab = true;
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if (fn != __this_cpu_read(bp_hardening_data.fn)) {
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__this_cpu_write(bp_hardening_data.hyp_vectors_slot, slot);
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__this_cpu_write(bp_hardening_data.fn, fn);
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__this_cpu_write(bp_hardening_data.template_start, hyp_vecs_start);
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__hardenbp_enab = true;
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}
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spin_unlock(&bp_lock);
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}
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#else
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@ -856,8 +858,11 @@ static void kvm_setup_bhb_slot(const char *hyp_vecs_start)
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__copy_hyp_vect_bpi(slot, hyp_vecs_start, hyp_vecs_end);
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}
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__this_cpu_write(bp_hardening_data.hyp_vectors_slot, slot);
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__this_cpu_write(bp_hardening_data.template_start, hyp_vecs_start);
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if (hyp_vecs_start != __this_cpu_read(bp_hardening_data.template_start)) {
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__this_cpu_write(bp_hardening_data.hyp_vectors_slot, slot);
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__this_cpu_write(bp_hardening_data.template_start,
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hyp_vecs_start);
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}
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spin_unlock(&bp_lock);
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}
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#else
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@ -899,7 +904,13 @@ void spectre_bhb_enable_mitigation(const struct arm64_cpu_capabilities *entry)
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} else if (spectre_bhb_loop_affected(SCOPE_LOCAL_CPU)) {
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switch (spectre_bhb_loop_affected(SCOPE_SYSTEM)) {
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case 8:
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kvm_setup_bhb_slot(__spectre_bhb_loop_k8_start);
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/*
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* A57/A72-r0 will already have selected the
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* spectre-indirect vector, which is sufficient
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* for BHB too.
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*/
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if (!__this_cpu_read(bp_hardening_data.fn))
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kvm_setup_bhb_slot(__spectre_bhb_loop_k8_start);
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break;
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case 24:
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kvm_setup_bhb_slot(__spectre_bhb_loop_k24_start);
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@ -26,6 +26,6 @@ extern char *fw_getcmdline(void);
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extern void fw_meminit(void);
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extern char *fw_getenv(char *name);
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extern unsigned long fw_getenvl(char *name);
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extern void fw_init_early_console(char port);
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extern void fw_init_early_console(void);
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#endif /* __ASM_FW_H_ */
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@ -34,7 +34,7 @@
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#define U_BRG(x) (UART_BASE(x) + 0x40)
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static void __iomem *uart_base;
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static char console_port = -1;
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static int console_port = -1;
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static int __init configure_uart_pins(int port)
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{
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@ -54,7 +54,7 @@ static int __init configure_uart_pins(int port)
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return 0;
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}
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static void __init configure_uart(char port, int baud)
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static void __init configure_uart(int port, int baud)
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{
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u32 pbclk;
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@ -67,7 +67,7 @@ static void __init configure_uart(char port, int baud)
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uart_base + PIC32_SET(U_STA(port)));
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}
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static void __init setup_early_console(char port, int baud)
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static void __init setup_early_console(int port, int baud)
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{
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if (configure_uart_pins(port))
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return;
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@ -137,16 +137,15 @@ _out:
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return baud;
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}
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void __init fw_init_early_console(char port)
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void __init fw_init_early_console(void)
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{
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char *arch_cmdline = pic32_getcmdline();
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int baud = -1;
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int baud, port;
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uart_base = ioremap_nocache(PIC32_BASE_UART, 0xc00);
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baud = get_baud_from_cmdline(arch_cmdline);
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if (port == -1)
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port = get_port_from_cmdline(arch_cmdline);
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port = get_port_from_cmdline(arch_cmdline);
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if (port == -1)
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port = EARLY_CONSOLE_PORT;
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@ -68,7 +68,7 @@ void __init plat_mem_setup(void)
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strlcpy(arcs_cmdline, boot_command_line, COMMAND_LINE_SIZE);
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#ifdef CONFIG_EARLY_PRINTK
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fw_init_early_console(-1);
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fw_init_early_console();
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#endif
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pic32_config_init();
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}
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@ -20,7 +20,7 @@ $(obj)/vmlinux.bin: vmlinux FORCE
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$(obj)/vmlinux.gz: $(obj)/vmlinux.bin FORCE
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$(call if_changed,gzip)
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$(obj)/vmImage: $(obj)/vmlinux.gz
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$(obj)/vmImage: $(obj)/vmlinux.gz FORCE
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$(call if_changed,uimage)
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@$(kecho) 'Kernel: $@ is ready'
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@ -42,7 +42,7 @@ struct save_area {
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u64 fprs[16];
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u32 fpc;
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u32 prefix;
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u64 todpreg;
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u32 todpreg;
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u64 timer;
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u64 todcmp;
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u64 vxrs_low[16];
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@ -196,6 +196,7 @@
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#define X86_FEATURE_FENCE_SWAPGS_KERNEL ( 7*32+11) /* "" LFENCE in kernel entry SWAPGS path */
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#define X86_FEATURE_RETPOLINE ( 7*32+12) /* "" Generic Retpoline mitigation for Spectre variant 2 */
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#define X86_FEATURE_RETPOLINE_LFENCE ( 7*32+13) /* "" Use LFENCE for Spectre variant 2 */
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#define X86_FEATURE_MSR_TSX_CTRL ( 7*32+14) /* "" MSR IA32_TSX_CTRL (Intel) implemented */
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#define X86_FEATURE_MSR_SPEC_CTRL ( 7*32+16) /* "" MSR SPEC_CTRL is implemented */
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#define X86_FEATURE_SSBD ( 7*32+17) /* Speculative Store Bypass Disable */
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@ -364,6 +364,11 @@
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#define MSR_AMD64_OSVW_STATUS 0xc0010141
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#define MSR_AMD64_LS_CFG 0xc0011020
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#define MSR_AMD64_DC_CFG 0xc0011022
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#define MSR_AMD64_DE_CFG 0xc0011029
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#define MSR_AMD64_DE_CFG_LFENCE_SERIALIZE_BIT 1
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#define MSR_AMD64_DE_CFG_LFENCE_SERIALIZE BIT_ULL(MSR_AMD64_DE_CFG_LFENCE_SERIALIZE_BIT)
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#define MSR_AMD64_BU_CFG2 0xc001102a
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#define MSR_AMD64_IBSFETCHCTL 0xc0011030
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#define MSR_AMD64_IBSFETCHLINAD 0xc0011031
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@ -414,9 +419,6 @@
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#define FAM10H_MMIO_CONF_BASE_MASK 0xfffffffULL
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#define FAM10H_MMIO_CONF_BASE_SHIFT 20
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#define MSR_FAM10H_NODE_ID 0xc001100c
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#define MSR_F10H_DECFG 0xc0011029
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#define MSR_F10H_DECFG_LFENCE_SERIALIZE_BIT 1
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#define MSR_F10H_DECFG_LFENCE_SERIALIZE BIT_ULL(MSR_F10H_DECFG_LFENCE_SERIALIZE_BIT)
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/* K8 MSRs */
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#define MSR_K8_TOP_MEM1 0xc001001a
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@ -735,8 +735,6 @@ static void init_amd_gh(struct cpuinfo_x86 *c)
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set_cpu_bug(c, X86_BUG_AMD_TLB_MMATCH);
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}
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#define MSR_AMD64_DE_CFG 0xC0011029
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static void init_amd_ln(struct cpuinfo_x86 *c)
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{
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/*
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@ -898,16 +896,16 @@ static void init_amd(struct cpuinfo_x86 *c)
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* msr_set_bit() uses the safe accessors, too, even if the MSR
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* is not present.
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*/
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msr_set_bit(MSR_F10H_DECFG,
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MSR_F10H_DECFG_LFENCE_SERIALIZE_BIT);
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msr_set_bit(MSR_AMD64_DE_CFG,
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MSR_AMD64_DE_CFG_LFENCE_SERIALIZE_BIT);
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/*
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* Verify that the MSR write was successful (could be running
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* under a hypervisor) and only then assume that LFENCE is
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* serializing.
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*/
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ret = rdmsrl_safe(MSR_F10H_DECFG, &val);
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if (!ret && (val & MSR_F10H_DECFG_LFENCE_SERIALIZE)) {
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ret = rdmsrl_safe(MSR_AMD64_DE_CFG, &val);
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if (!ret && (val & MSR_AMD64_DE_CFG_LFENCE_SERIALIZE_BIT)) {
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/* A serializing LFENCE stops RDTSC speculation */
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set_cpu_cap(c, X86_FEATURE_LFENCE_RDTSC);
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} else {
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|
|
@ -55,24 +55,6 @@ void tsx_enable(void)
|
|||
wrmsrl(MSR_IA32_TSX_CTRL, tsx);
|
||||
}
|
||||
|
||||
static bool __init tsx_ctrl_is_supported(void)
|
||||
{
|
||||
u64 ia32_cap = x86_read_arch_cap_msr();
|
||||
|
||||
/*
|
||||
* TSX is controlled via MSR_IA32_TSX_CTRL. However, support for this
|
||||
* MSR is enumerated by ARCH_CAP_TSX_MSR bit in MSR_IA32_ARCH_CAPABILITIES.
|
||||
*
|
||||
* TSX control (aka MSR_IA32_TSX_CTRL) is only available after a
|
||||
* microcode update on CPUs that have their MSR_IA32_ARCH_CAPABILITIES
|
||||
* bit MDS_NO=1. CPUs with MDS_NO=0 are not planned to get
|
||||
* MSR_IA32_TSX_CTRL support even after a microcode update. Thus,
|
||||
* tsx= cmdline requests will do nothing on CPUs without
|
||||
* MSR_IA32_TSX_CTRL support.
|
||||
*/
|
||||
return !!(ia32_cap & ARCH_CAP_TSX_CTRL_MSR);
|
||||
}
|
||||
|
||||
static enum tsx_ctrl_states x86_get_tsx_auto_mode(void)
|
||||
{
|
||||
if (boot_cpu_has_bug(X86_BUG_TAA))
|
||||
|
|
@ -86,9 +68,22 @@ void __init tsx_init(void)
|
|||
char arg[5] = {};
|
||||
int ret;
|
||||
|
||||
if (!tsx_ctrl_is_supported())
|
||||
/*
|
||||
* TSX is controlled via MSR_IA32_TSX_CTRL. However, support for this
|
||||
* MSR is enumerated by ARCH_CAP_TSX_MSR bit in MSR_IA32_ARCH_CAPABILITIES.
|
||||
*
|
||||
* TSX control (aka MSR_IA32_TSX_CTRL) is only available after a
|
||||
* microcode update on CPUs that have their MSR_IA32_ARCH_CAPABILITIES
|
||||
* bit MDS_NO=1. CPUs with MDS_NO=0 are not planned to get
|
||||
* MSR_IA32_TSX_CTRL support even after a microcode update. Thus,
|
||||
* tsx= cmdline requests will do nothing on CPUs without
|
||||
* MSR_IA32_TSX_CTRL support.
|
||||
*/
|
||||
if (!(x86_read_arch_cap_msr() & ARCH_CAP_TSX_CTRL_MSR))
|
||||
return;
|
||||
|
||||
setup_force_cpu_cap(X86_FEATURE_MSR_TSX_CTRL);
|
||||
|
||||
ret = cmdline_find_option(boot_command_line, "tsx", arg, sizeof(arg));
|
||||
if (ret >= 0) {
|
||||
if (!strcmp(arg, "on")) {
|
||||
|
|
|
|||
|
|
@ -647,6 +647,7 @@ static inline int __do_cpuid_ent(struct kvm_cpuid_entry2 *entry, u32 function,
|
|||
g_phys_as = phys_as;
|
||||
|
||||
entry->eax = g_phys_as | (virt_as << 8);
|
||||
entry->ecx &= ~(GENMASK(31, 16) | GENMASK(11, 8));
|
||||
entry->edx = 0;
|
||||
/*
|
||||
* IBRS, IBPB and VIRT_SSBD aren't necessarily present in
|
||||
|
|
|
|||
|
|
@ -750,8 +750,7 @@ static int linearize(struct x86_emulate_ctxt *ctxt,
|
|||
ctxt->mode, linear);
|
||||
}
|
||||
|
||||
static inline int assign_eip(struct x86_emulate_ctxt *ctxt, ulong dst,
|
||||
enum x86emul_mode mode)
|
||||
static inline int assign_eip(struct x86_emulate_ctxt *ctxt, ulong dst)
|
||||
{
|
||||
ulong linear;
|
||||
int rc;
|
||||
|
|
@ -761,41 +760,71 @@ static inline int assign_eip(struct x86_emulate_ctxt *ctxt, ulong dst,
|
|||
|
||||
if (ctxt->op_bytes != sizeof(unsigned long))
|
||||
addr.ea = dst & ((1UL << (ctxt->op_bytes << 3)) - 1);
|
||||
rc = __linearize(ctxt, addr, &max_size, 1, false, true, mode, &linear);
|
||||
rc = __linearize(ctxt, addr, &max_size, 1, false, true, ctxt->mode, &linear);
|
||||
if (rc == X86EMUL_CONTINUE)
|
||||
ctxt->_eip = addr.ea;
|
||||
return rc;
|
||||
}
|
||||
|
||||
static inline int assign_eip_near(struct x86_emulate_ctxt *ctxt, ulong dst)
|
||||
static inline int emulator_recalc_and_set_mode(struct x86_emulate_ctxt *ctxt)
|
||||
{
|
||||
return assign_eip(ctxt, dst, ctxt->mode);
|
||||
u64 efer;
|
||||
struct desc_struct cs;
|
||||
u16 selector;
|
||||
u32 base3;
|
||||
|
||||
ctxt->ops->get_msr(ctxt, MSR_EFER, &efer);
|
||||
|
||||
if (!(ctxt->ops->get_cr(ctxt, 0) & X86_CR0_PE)) {
|
||||
/* Real mode. cpu must not have long mode active */
|
||||
if (efer & EFER_LMA)
|
||||
return X86EMUL_UNHANDLEABLE;
|
||||
ctxt->mode = X86EMUL_MODE_REAL;
|
||||
return X86EMUL_CONTINUE;
|
||||
}
|
||||
|
||||
if (ctxt->eflags & X86_EFLAGS_VM) {
|
||||
/* Protected/VM86 mode. cpu must not have long mode active */
|
||||
if (efer & EFER_LMA)
|
||||
return X86EMUL_UNHANDLEABLE;
|
||||
ctxt->mode = X86EMUL_MODE_VM86;
|
||||
return X86EMUL_CONTINUE;
|
||||
}
|
||||
|
||||
if (!ctxt->ops->get_segment(ctxt, &selector, &cs, &base3, VCPU_SREG_CS))
|
||||
return X86EMUL_UNHANDLEABLE;
|
||||
|
||||
if (efer & EFER_LMA) {
|
||||
if (cs.l) {
|
||||
/* Proper long mode */
|
||||
ctxt->mode = X86EMUL_MODE_PROT64;
|
||||
} else if (cs.d) {
|
||||
/* 32 bit compatibility mode*/
|
||||
ctxt->mode = X86EMUL_MODE_PROT32;
|
||||
} else {
|
||||
ctxt->mode = X86EMUL_MODE_PROT16;
|
||||
}
|
||||
} else {
|
||||
/* Legacy 32 bit / 16 bit mode */
|
||||
ctxt->mode = cs.d ? X86EMUL_MODE_PROT32 : X86EMUL_MODE_PROT16;
|
||||
}
|
||||
|
||||
return X86EMUL_CONTINUE;
|
||||
}
|
||||
|
||||
static int assign_eip_far(struct x86_emulate_ctxt *ctxt, ulong dst,
|
||||
const struct desc_struct *cs_desc)
|
||||
static inline int assign_eip_near(struct x86_emulate_ctxt *ctxt, ulong dst)
|
||||
{
|
||||
enum x86emul_mode mode = ctxt->mode;
|
||||
int rc;
|
||||
return assign_eip(ctxt, dst);
|
||||
}
|
||||
|
||||
#ifdef CONFIG_X86_64
|
||||
if (ctxt->mode >= X86EMUL_MODE_PROT16) {
|
||||
if (cs_desc->l) {
|
||||
u64 efer = 0;
|
||||
static int assign_eip_far(struct x86_emulate_ctxt *ctxt, ulong dst)
|
||||
{
|
||||
int rc = emulator_recalc_and_set_mode(ctxt);
|
||||
|
||||
ctxt->ops->get_msr(ctxt, MSR_EFER, &efer);
|
||||
if (efer & EFER_LMA)
|
||||
mode = X86EMUL_MODE_PROT64;
|
||||
} else
|
||||
mode = X86EMUL_MODE_PROT32; /* temporary value */
|
||||
}
|
||||
#endif
|
||||
if (mode == X86EMUL_MODE_PROT16 || mode == X86EMUL_MODE_PROT32)
|
||||
mode = cs_desc->d ? X86EMUL_MODE_PROT32 : X86EMUL_MODE_PROT16;
|
||||
rc = assign_eip(ctxt, dst, mode);
|
||||
if (rc == X86EMUL_CONTINUE)
|
||||
ctxt->mode = mode;
|
||||
return rc;
|
||||
if (rc != X86EMUL_CONTINUE)
|
||||
return rc;
|
||||
|
||||
return assign_eip(ctxt, dst);
|
||||
}
|
||||
|
||||
static inline int jmp_rel(struct x86_emulate_ctxt *ctxt, int rel)
|
||||
|
|
@ -2197,7 +2226,7 @@ static int em_jmp_far(struct x86_emulate_ctxt *ctxt)
|
|||
if (rc != X86EMUL_CONTINUE)
|
||||
return rc;
|
||||
|
||||
rc = assign_eip_far(ctxt, ctxt->src.val, &new_desc);
|
||||
rc = assign_eip_far(ctxt, ctxt->src.val);
|
||||
/* Error handling is not implemented. */
|
||||
if (rc != X86EMUL_CONTINUE)
|
||||
return X86EMUL_UNHANDLEABLE;
|
||||
|
|
@ -2278,7 +2307,7 @@ static int em_ret_far(struct x86_emulate_ctxt *ctxt)
|
|||
&new_desc);
|
||||
if (rc != X86EMUL_CONTINUE)
|
||||
return rc;
|
||||
rc = assign_eip_far(ctxt, eip, &new_desc);
|
||||
rc = assign_eip_far(ctxt, eip);
|
||||
/* Error handling is not implemented. */
|
||||
if (rc != X86EMUL_CONTINUE)
|
||||
return X86EMUL_UNHANDLEABLE;
|
||||
|
|
@ -2881,6 +2910,7 @@ static int em_sysexit(struct x86_emulate_ctxt *ctxt)
|
|||
ops->set_segment(ctxt, ss_sel, &ss, 0, VCPU_SREG_SS);
|
||||
|
||||
ctxt->_eip = rdx;
|
||||
ctxt->mode = usermode;
|
||||
*reg_write(ctxt, VCPU_REGS_RSP) = rcx;
|
||||
|
||||
return X86EMUL_CONTINUE;
|
||||
|
|
@ -3466,7 +3496,7 @@ static int em_call_far(struct x86_emulate_ctxt *ctxt)
|
|||
if (rc != X86EMUL_CONTINUE)
|
||||
return rc;
|
||||
|
||||
rc = assign_eip_far(ctxt, ctxt->src.val, &new_desc);
|
||||
rc = assign_eip_far(ctxt, ctxt->src.val);
|
||||
if (rc != X86EMUL_CONTINUE)
|
||||
goto fail;
|
||||
|
||||
|
|
@ -3613,11 +3643,25 @@ static int em_movbe(struct x86_emulate_ctxt *ctxt)
|
|||
|
||||
static int em_cr_write(struct x86_emulate_ctxt *ctxt)
|
||||
{
|
||||
if (ctxt->ops->set_cr(ctxt, ctxt->modrm_reg, ctxt->src.val))
|
||||
int cr_num = ctxt->modrm_reg;
|
||||
int r;
|
||||
|
||||
if (ctxt->ops->set_cr(ctxt, cr_num, ctxt->src.val))
|
||||
return emulate_gp(ctxt, 0);
|
||||
|
||||
/* Disable writeback. */
|
||||
ctxt->dst.type = OP_NONE;
|
||||
|
||||
if (cr_num == 0) {
|
||||
/*
|
||||
* CR0 write might have updated CR0.PE and/or CR0.PG
|
||||
* which can affect the cpu's execution mode.
|
||||
*/
|
||||
r = emulator_recalc_and_set_mode(ctxt);
|
||||
if (r != X86EMUL_CONTINUE)
|
||||
return r;
|
||||
}
|
||||
|
||||
return X86EMUL_CONTINUE;
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -3528,9 +3528,9 @@ static int svm_get_msr_feature(struct kvm_msr_entry *msr)
|
|||
msr->data = 0;
|
||||
|
||||
switch (msr->index) {
|
||||
case MSR_F10H_DECFG:
|
||||
if (boot_cpu_has(X86_FEATURE_LFENCE_RDTSC))
|
||||
msr->data |= MSR_F10H_DECFG_LFENCE_SERIALIZE;
|
||||
case MSR_AMD64_DE_CFG:
|
||||
if (cpu_feature_enabled(X86_FEATURE_LFENCE_RDTSC))
|
||||
msr->data |= MSR_AMD64_DE_CFG_LFENCE_SERIALIZE;
|
||||
break;
|
||||
default:
|
||||
return 1;
|
||||
|
|
@ -3638,7 +3638,7 @@ static int svm_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
|
|||
msr_info->data = 0x1E;
|
||||
}
|
||||
break;
|
||||
case MSR_F10H_DECFG:
|
||||
case MSR_AMD64_DE_CFG:
|
||||
msr_info->data = svm->msr_decfg;
|
||||
break;
|
||||
default:
|
||||
|
|
@ -3829,7 +3829,7 @@ static int svm_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
|
|||
case MSR_VM_IGNNE:
|
||||
vcpu_unimpl(vcpu, "unimplemented wrmsr: 0x%x data 0x%llx\n", ecx, data);
|
||||
break;
|
||||
case MSR_F10H_DECFG: {
|
||||
case MSR_AMD64_DE_CFG: {
|
||||
struct kvm_msr_entry msr_entry;
|
||||
|
||||
msr_entry.index = msr->index;
|
||||
|
|
|
|||
|
|
@ -1026,7 +1026,7 @@ static unsigned num_emulated_msrs;
|
|||
* can be used by a hypervisor to validate requested CPU features.
|
||||
*/
|
||||
static u32 msr_based_features[] = {
|
||||
MSR_F10H_DECFG,
|
||||
MSR_AMD64_DE_CFG,
|
||||
MSR_IA32_UCODE_REV,
|
||||
MSR_IA32_ARCH_CAPABILITIES,
|
||||
};
|
||||
|
|
|
|||
|
|
@ -126,9 +126,15 @@ static void __iomem *__ioremap_caller(resource_size_t phys_addr,
|
|||
* Mappings have to be page-aligned
|
||||
*/
|
||||
offset = phys_addr & ~PAGE_MASK;
|
||||
phys_addr &= PHYSICAL_PAGE_MASK;
|
||||
phys_addr &= PAGE_MASK;
|
||||
size = PAGE_ALIGN(last_addr+1) - phys_addr;
|
||||
|
||||
/*
|
||||
* Mask out any bits not part of the actual physical
|
||||
* address, like memory encryption bits.
|
||||
*/
|
||||
phys_addr &= PHYSICAL_PAGE_MASK;
|
||||
|
||||
retval = reserve_memtype(phys_addr, (u64)phys_addr + size,
|
||||
pcm, &new_pcm);
|
||||
if (retval) {
|
||||
|
|
|
|||
|
|
@ -520,15 +520,23 @@ static int pm_cpu_check(const struct x86_cpu_id *c)
|
|||
|
||||
static void pm_save_spec_msr(void)
|
||||
{
|
||||
u32 spec_msr_id[] = {
|
||||
MSR_IA32_SPEC_CTRL,
|
||||
MSR_IA32_TSX_CTRL,
|
||||
MSR_TSX_FORCE_ABORT,
|
||||
MSR_IA32_MCU_OPT_CTRL,
|
||||
MSR_AMD64_LS_CFG,
|
||||
struct msr_enumeration {
|
||||
u32 msr_no;
|
||||
u32 feature;
|
||||
} msr_enum[] = {
|
||||
{ MSR_IA32_SPEC_CTRL, X86_FEATURE_MSR_SPEC_CTRL },
|
||||
{ MSR_IA32_TSX_CTRL, X86_FEATURE_MSR_TSX_CTRL },
|
||||
{ MSR_TSX_FORCE_ABORT, X86_FEATURE_TSX_FORCE_ABORT },
|
||||
{ MSR_IA32_MCU_OPT_CTRL, X86_FEATURE_SRBDS_CTRL },
|
||||
{ MSR_AMD64_LS_CFG, X86_FEATURE_LS_CFG_SSBD },
|
||||
{ MSR_AMD64_DE_CFG, X86_FEATURE_LFENCE_RDTSC },
|
||||
};
|
||||
int i;
|
||||
|
||||
msr_build_context(spec_msr_id, ARRAY_SIZE(spec_msr_id));
|
||||
for (i = 0; i < ARRAY_SIZE(msr_enum); i++) {
|
||||
if (boot_cpu_has(msr_enum[i].feature))
|
||||
msr_build_context(&msr_enum[i].msr_no, 1);
|
||||
}
|
||||
}
|
||||
|
||||
static int pm_check_save_msr(void)
|
||||
|
|
|
|||
|
|
@ -292,9 +292,10 @@ static void pdc20230_set_piomode(struct ata_port *ap, struct ata_device *adev)
|
|||
outb(inb(0x1F4) & 0x07, 0x1F4);
|
||||
|
||||
rt = inb(0x1F3);
|
||||
rt &= 0x07 << (3 * adev->devno);
|
||||
rt &= ~(0x07 << (3 * !adev->devno));
|
||||
if (pio)
|
||||
rt |= (1 + 3 * pio) << (3 * adev->devno);
|
||||
rt |= (1 + 3 * pio) << (3 * !adev->devno);
|
||||
outb(rt, 0x1F3);
|
||||
|
||||
udelay(100);
|
||||
outb(inb(0x1F2) | 0x01, 0x1F2);
|
||||
|
|
|
|||
Some files were not shown because too many files have changed in this diff Show more
Loading…
Reference in a new issue