Merge android-4.9.169 (1ef64da) into msm-4.9
* refs/heads/tmp-1ef64da : Linux 4.9.169 PCI: Add function 1 DMA alias quirk for Marvell 9170 SATA controller xtensa: fix return_address sched/fair: Do not re-read ->h_load_next during hierarchical load calculation xen: Prevent buffer overflow in privcmd ioctl parisc: Use cr16 interval timers unconditionally on qemu arm64: futex: Fix FUTEX_WAKE_OP atomic ops with non-zero result value ARM: dts: at91: Fix typo in ISC_D0 on PC9 virtio: Honour 'may_reduce_num' in vring_create_virtqueue genirq: Respect IRQCHIP_SKIP_SET_WAKE in irq_chip_set_wake_parent() block: do not leak memory in bio_copy_user_iov() Btrfs: do not allow trimming when a fs is mounted with the nologreplay option ASoC: fsl_esai: fix channel swap issue when stream starts include/linux/bitrev.h: fix constant bitrev parisc: Detect QEMU earlier in boot process ALSA: seq: Fix OOB-reads from strlcpy ip6_tunnel: Match to ARPHRD_TUNNEL6 for dev type net: ethtool: not call vzalloc for zero sized memory request netns: provide pure entropy for net_hash_mix() net/mlx5e: Add a lock on tir list bnxt_en: Improve RX consumer index validity check. bnxt_en: Reset device on RX buffer errors. vrf: check accept_source_route on the original netdevice tcp: Ensure DCTCP reacts to losses sctp: initialize _pad of sockaddr_in before copying to user memory qmi_wwan: add Olicard 600 openvswitch: fix flow actions reallocation net: rds: force to destroy connection if t_sock is NULL in rds_tcp_kill_sock(). kcm: switch order of device registration to fix a crash ipv6: sit: reset ip header pointer in ipip6_rcv ipv6: Fix dangling pointer when ipv6 fragment tty: ldisc: add sysctl to prevent autoloading of ldiscs tty: mark Siemens R3964 line discipline as BROKEN arm64: kaslr: Reserve size of ARM64_MEMSTART_ALIGN in linear region powerpc/security: Fix spectre_v2 reporting powerpc/fsl: Fix the flush of branch predictor. powerpc/fsl: Fixed warning: orphan section `__btb_flush_fixup' powerpc/fsl: Update Spectre v2 reporting powerpc/fsl: Enable runtime patching if nospectre_v2 boot arg is used powerpc/fsl: Flush branch predictor when entering KVM powerpc/fsl: Flush the branch predictor at each kernel entry (32 bit) powerpc/fsl: Flush the branch predictor at each kernel entry (64bit) powerpc/fsl: Add nospectre_v2 command line argument powerpc/fsl: Emulate SPRN_BUCSR register powerpc/fsl: Fix spectre_v2 mitigations reporting powerpc/fsl: Add macro to flush the branch predictor powerpc/fsl: Add infrastructure to fixup branch predictor flush powerpc/powernv: Query firmware for count cache flush settings powerpc/pseries: Query hypervisor for count cache flush settings powerpc/64s: Add support for software count cache flush powerpc/64s: Add new security feature flags for count cache flush powerpc/asm: Add a patch_site macro & helpers for patching instructions powerpc/fsl: Sanitize the syscall table for NXP PowerPC 32 bit platforms powerpc/fsl: Add barrier_nospec implementation for NXP PowerPC Book3E powerpc/64: Make meltdown reporting Book3S 64 specific powerpc/64: Call setup_barrier_nospec() from setup_arch() powerpc/64: Add CONFIG_PPC_BARRIER_NOSPEC powerpc/64: Make stf barrier PPC_BOOK3S_64 specific. powerpc/64: Disable the speculation barrier from the command line powerpc64s: Show ori31 availability in spectre_v1 sysfs file not v2 powerpc/64s: Enhance the information in cpu_show_spectre_v1() powerpc/64: Use barrier_nospec in syscall entry powerpc: Use barrier_nospec in copy_from_user() powerpc/64s: Enable barrier_nospec based on firmware settings powerpc/64s: Patch barrier_nospec in modules powerpc: Avoid code patching freed init sections powerpc/64s: Add support for ori barrier_nospec patching powerpc/64s: Add barrier_nospec powerpc: Fix invalid use of register expressions lib/string.c: implement a basic bcmp x86/vdso: Drop implicit common-page-size linker flag x86: vdso: Use $LD instead of $CC to link kbuild: clang: choose GCC_TOOLCHAIN_DIR not on LD powerpc/tm: Limit TM code inside PPC_TRANSACTIONAL_MEM x86/power: Make restore_processor_context() sane x86/power/32: Move SYSENTER MSR restoration to fix_processor_context() x86/power/64: Use struct desc_ptr for the IDT in struct saved_context x86/power: Fix some ordering bugs in __restore_processor_context() ANDROID: Makefile: Add '-fsplit-lto-unit' to cfi-clang-flags Conflicts: drivers/tty/Kconfig Change-Id: Ic2f7a4f7bd94d8345c34293bf933b2ed13680155 Signed-off-by: jianzhou <jianzhou@codeaurora.org>
This commit is contained in:
jianzhou
commit
45728c3f55
83 changed files with 1140 additions and 293 deletions
12
Makefile
12
Makefile
|
|
@ -1,6 +1,6 @@
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VERSION = 4
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PATCHLEVEL = 9
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SUBLEVEL = 168
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SUBLEVEL = 169
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EXTRAVERSION =
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NAME = Roaring Lionus
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@ -511,12 +511,8 @@ endif
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ifeq ($(cc-name),clang)
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ifneq ($(CROSS_COMPILE),)
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CLANG_TRIPLE ?= $(CROSS_COMPILE)
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CLANG_FLAGS := --target=$(notdir $(CLANG_TRIPLE:%-=%))
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ifeq ($(shell $(srctree)/scripts/clang-android.sh $(CC) $(CLANG_FLAGS)), y)
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$(error "Clang with Android --target detected. Did you specify CLANG_TRIPLE?")
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endif
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GCC_TOOLCHAIN_DIR := $(dir $(shell which $(LD)))
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CLANG_FLAGS := --target=$(notdir $(CROSS_COMPILE:%-=%))
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GCC_TOOLCHAIN_DIR := $(dir $(shell which $(CROSS_COMPILE)elfedit))
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CLANG_FLAGS += --prefix=$(GCC_TOOLCHAIN_DIR)
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GCC_TOOLCHAIN := $(realpath $(GCC_TOOLCHAIN_DIR)/..)
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endif
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@ -720,7 +716,7 @@ export LDFINAL_vmlinux LDFLAGS_FINAL_vmlinux
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endif
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ifdef CONFIG_CFI_CLANG
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cfi-clang-flags += -fsanitize=cfi
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cfi-clang-flags += -fsanitize=cfi $(call cc-option, -fsplit-lto-unit)
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DISABLE_CFI_CLANG := -fno-sanitize=cfi
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ifdef CONFIG_MODULES
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cfi-clang-flags += -fsanitize-cfi-cross-dso
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@ -517,7 +517,7 @@
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#define PIN_PC9__GPIO PINMUX_PIN(PIN_PC9, 0, 0)
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#define PIN_PC9__FIQ PINMUX_PIN(PIN_PC9, 1, 3)
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#define PIN_PC9__GTSUCOMP PINMUX_PIN(PIN_PC9, 2, 1)
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#define PIN_PC9__ISC_D0 PINMUX_PIN(PIN_PC9, 2, 1)
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#define PIN_PC9__ISC_D0 PINMUX_PIN(PIN_PC9, 3, 1)
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#define PIN_PC9__TIOA4 PINMUX_PIN(PIN_PC9, 4, 2)
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#define PIN_PC10 74
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#define PIN_PC10__GPIO PINMUX_PIN(PIN_PC10, 0, 0)
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14
arch/arm64/include/asm/futex.h
Normal file → Executable file
14
arch/arm64/include/asm/futex.h
Normal file → Executable file
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@ -30,8 +30,8 @@ do { \
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" prfm pstl1strm, %2\n" \
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"1: ldxr %w1, %2\n" \
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insn "\n" \
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"2: stlxr %w3, %w0, %2\n" \
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" cbnz %w3, 1b\n" \
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"2: stlxr %w0, %w3, %2\n" \
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" cbnz %w0, 1b\n" \
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" dmb ish\n" \
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"3:\n" \
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" .pushsection .fixup,\"ax\"\n" \
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@ -56,23 +56,23 @@ arch_futex_atomic_op_inuser(int op, int oparg, int *oval, u32 __user *uaddr)
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switch (op) {
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case FUTEX_OP_SET:
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__futex_atomic_op("mov %w0, %w4",
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__futex_atomic_op("mov %w3, %w4",
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ret, oldval, uaddr, tmp, oparg);
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break;
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case FUTEX_OP_ADD:
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__futex_atomic_op("add %w0, %w1, %w4",
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__futex_atomic_op("add %w3, %w1, %w4",
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ret, oldval, uaddr, tmp, oparg);
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break;
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case FUTEX_OP_OR:
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__futex_atomic_op("orr %w0, %w1, %w4",
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__futex_atomic_op("orr %w3, %w1, %w4",
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ret, oldval, uaddr, tmp, oparg);
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break;
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case FUTEX_OP_ANDN:
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__futex_atomic_op("and %w0, %w1, %w4",
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__futex_atomic_op("and %w3, %w1, %w4",
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ret, oldval, uaddr, tmp, ~oparg);
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break;
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case FUTEX_OP_XOR:
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__futex_atomic_op("eor %w0, %w1, %w4",
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__futex_atomic_op("eor %w3, %w1, %w4",
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ret, oldval, uaddr, tmp, oparg);
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break;
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default:
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@ -323,6 +323,8 @@ extern int _parisc_requires_coherency;
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#define parisc_requires_coherency() (0)
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#endif
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extern int running_on_qemu;
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#endif /* __ASSEMBLY__ */
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#endif /* __ASM_PARISC_PROCESSOR_H */
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@ -206,12 +206,6 @@ void __cpuidle arch_cpu_idle(void)
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static int __init parisc_idle_init(void)
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{
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const char *marker;
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/* check QEMU/SeaBIOS marker in PAGE0 */
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marker = (char *) &PAGE0->pad0;
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running_on_qemu = (memcmp(marker, "SeaBIOS", 8) == 0);
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if (!running_on_qemu)
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cpu_idle_poll_ctrl(1);
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@ -403,6 +403,9 @@ void start_parisc(void)
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int ret, cpunum;
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struct pdc_coproc_cfg coproc_cfg;
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/* check QEMU/SeaBIOS marker in PAGE0 */
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running_on_qemu = (memcmp(&PAGE0->pad0, "SeaBIOS", 8) == 0);
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cpunum = smp_processor_id();
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set_firmware_width_unlocked();
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@ -299,7 +299,7 @@ static int __init init_cr16_clocksource(void)
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* The cr16 interval timers are not syncronized across CPUs, so mark
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* them unstable and lower rating on SMP systems.
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*/
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if (num_online_cpus() > 1) {
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if (num_online_cpus() > 1 && !running_on_qemu) {
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clocksource_cr16.flags = CLOCK_SOURCE_UNSTABLE;
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clocksource_cr16.rating = 0;
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}
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@ -129,7 +129,7 @@ config PPC
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select ARCH_HAS_GCOV_PROFILE_ALL
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select GENERIC_SMP_IDLE_THREAD
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select GENERIC_CMOS_UPDATE
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select GENERIC_CPU_VULNERABILITIES if PPC_BOOK3S_64
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select GENERIC_CPU_VULNERABILITIES if PPC_BARRIER_NOSPEC
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select GENERIC_TIME_VSYSCALL_OLD
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select GENERIC_CLOCKEVENTS
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select GENERIC_CLOCKEVENTS_BROADCAST if SMP
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@ -165,6 +165,11 @@ config PPC
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select HAVE_ARCH_HARDENED_USERCOPY
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select HAVE_KERNEL_GZIP
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config PPC_BARRIER_NOSPEC
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bool
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default y
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depends on PPC_BOOK3S_64 || PPC_FSL_BOOK3E
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config GENERIC_CSUM
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def_bool CPU_LITTLE_ENDIAN
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@ -121,4 +121,10 @@ extern s64 __ashrdi3(s64, int);
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extern int __cmpdi2(s64, s64);
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extern int __ucmpdi2(u64, u64);
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/* Patch sites */
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extern s32 patch__call_flush_count_cache;
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extern s32 patch__flush_count_cache_return;
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extern long flush_count_cache;
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#endif /* _ASM_POWERPC_ASM_PROTOTYPES_H */
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@ -77,6 +77,27 @@ do { \
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#define smp_mb__before_spinlock() smp_mb()
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#ifdef CONFIG_PPC_BOOK3S_64
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#define NOSPEC_BARRIER_SLOT nop
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#elif defined(CONFIG_PPC_FSL_BOOK3E)
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#define NOSPEC_BARRIER_SLOT nop; nop
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#endif
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#ifdef CONFIG_PPC_BARRIER_NOSPEC
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/*
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* Prevent execution of subsequent instructions until preceding branches have
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* been fully resolved and are no longer executing speculatively.
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*/
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#define barrier_nospec_asm NOSPEC_BARRIER_FIXUP_SECTION; NOSPEC_BARRIER_SLOT
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// This also acts as a compiler barrier due to the memory clobber.
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#define barrier_nospec() asm (stringify_in_c(barrier_nospec_asm) ::: "memory")
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#else /* !CONFIG_PPC_BARRIER_NOSPEC */
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#define barrier_nospec_asm
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#define barrier_nospec()
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#endif /* CONFIG_PPC_BARRIER_NOSPEC */
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#include <asm-generic/barrier.h>
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#endif /* _ASM_POWERPC_BARRIER_H */
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18
arch/powerpc/include/asm/code-patching-asm.h
Normal file
18
arch/powerpc/include/asm/code-patching-asm.h
Normal file
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@ -0,0 +1,18 @@
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/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Copyright 2018, Michael Ellerman, IBM Corporation.
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*/
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#ifndef _ASM_POWERPC_CODE_PATCHING_ASM_H
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#define _ASM_POWERPC_CODE_PATCHING_ASM_H
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/* Define a "site" that can be patched */
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.macro patch_site label name
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.pushsection ".rodata"
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.balign 4
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.global \name
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\name:
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.4byte \label - .
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.popsection
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.endm
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#endif /* _ASM_POWERPC_CODE_PATCHING_ASM_H */
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@ -28,6 +28,8 @@ unsigned int create_cond_branch(const unsigned int *addr,
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unsigned long target, int flags);
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int patch_branch(unsigned int *addr, unsigned long target, int flags);
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int patch_instruction(unsigned int *addr, unsigned int instr);
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int patch_instruction_site(s32 *addr, unsigned int instr);
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int patch_branch_site(s32 *site, unsigned long target, int flags);
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int instr_is_relative_branch(unsigned int instr);
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int instr_is_relative_link_branch(unsigned int instr);
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@ -213,6 +213,25 @@ void setup_feature_keys(void);
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FTR_ENTRY_OFFSET 951b-952b; \
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.popsection;
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#define NOSPEC_BARRIER_FIXUP_SECTION \
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953: \
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.pushsection __barrier_nospec_fixup,"a"; \
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.align 2; \
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954: \
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FTR_ENTRY_OFFSET 953b-954b; \
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.popsection;
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#define START_BTB_FLUSH_SECTION \
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955: \
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#define END_BTB_FLUSH_SECTION \
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956: \
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.pushsection __btb_flush_fixup,"a"; \
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.align 2; \
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957: \
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FTR_ENTRY_OFFSET 955b-957b; \
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FTR_ENTRY_OFFSET 956b-957b; \
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.popsection;
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#ifndef __ASSEMBLY__
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@ -220,6 +239,8 @@ extern long stf_barrier_fallback;
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extern long __start___stf_entry_barrier_fixup, __stop___stf_entry_barrier_fixup;
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extern long __start___stf_exit_barrier_fixup, __stop___stf_exit_barrier_fixup;
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extern long __start___rfi_flush_fixup, __stop___rfi_flush_fixup;
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extern long __start___barrier_nospec_fixup, __stop___barrier_nospec_fixup;
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extern long __start__btb_flush_fixup, __stop__btb_flush_fixup;
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#endif
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|
|
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|
@ -316,10 +316,12 @@
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#define H_CPU_CHAR_BRANCH_HINTS_HONORED (1ull << 58) // IBM bit 5
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#define H_CPU_CHAR_THREAD_RECONFIG_CTRL (1ull << 57) // IBM bit 6
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#define H_CPU_CHAR_COUNT_CACHE_DISABLED (1ull << 56) // IBM bit 7
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#define H_CPU_CHAR_BCCTR_FLUSH_ASSIST (1ull << 54) // IBM bit 9
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#define H_CPU_BEHAV_FAVOUR_SECURITY (1ull << 63) // IBM bit 0
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#define H_CPU_BEHAV_L1D_FLUSH_PR (1ull << 62) // IBM bit 1
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#define H_CPU_BEHAV_BNDS_CHK_SPEC_BAR (1ull << 61) // IBM bit 2
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#define H_CPU_BEHAV_FLUSH_COUNT_CACHE (1ull << 58) // IBM bit 5
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
#include <linux/types.h>
|
||||
|
|
|
|||
|
|
@ -437,7 +437,7 @@ END_FTR_SECTION_IFCLR(CPU_FTR_601)
|
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.machine push ; \
|
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.machine "power4" ; \
|
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lis scratch,0x60000000@h; \
|
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dcbt r0,scratch,0b01010; \
|
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dcbt 0,scratch,0b01010; \
|
||||
.machine pop
|
||||
|
||||
/*
|
||||
|
|
@ -780,4 +780,25 @@ END_FTR_SECTION_IFCLR(CPU_FTR_601)
|
|||
.long 0x2400004c /* rfid */
|
||||
#endif /* !CONFIG_PPC_BOOK3E */
|
||||
#endif /* __ASSEMBLY__ */
|
||||
|
||||
/*
|
||||
* Helper macro for exception table entries
|
||||
*/
|
||||
#define EX_TABLE(_fault, _target) \
|
||||
stringify_in_c(.section __ex_table,"a";)\
|
||||
stringify_in_c(.balign 4;) \
|
||||
stringify_in_c(.long (_fault) - . ;) \
|
||||
stringify_in_c(.long (_target) - . ;) \
|
||||
stringify_in_c(.previous)
|
||||
|
||||
#ifdef CONFIG_PPC_FSL_BOOK3E
|
||||
#define BTB_FLUSH(reg) \
|
||||
lis reg,BUCSR_INIT@h; \
|
||||
ori reg,reg,BUCSR_INIT@l; \
|
||||
mtspr SPRN_BUCSR,reg; \
|
||||
isync;
|
||||
#else
|
||||
#define BTB_FLUSH(reg)
|
||||
#endif /* CONFIG_PPC_FSL_BOOK3E */
|
||||
|
||||
#endif /* _ASM_POWERPC_PPC_ASM_H */
|
||||
|
|
|
|||
|
|
@ -22,6 +22,7 @@ enum stf_barrier_type {
|
|||
|
||||
void setup_stf_barrier(void);
|
||||
void do_stf_barrier_fixups(enum stf_barrier_type types);
|
||||
void setup_count_cache_flush(void);
|
||||
|
||||
static inline void security_ftr_set(unsigned long feature)
|
||||
{
|
||||
|
|
@ -59,6 +60,9 @@ static inline bool security_ftr_enabled(unsigned long feature)
|
|||
// Indirect branch prediction cache disabled
|
||||
#define SEC_FTR_COUNT_CACHE_DISABLED 0x0000000000000020ull
|
||||
|
||||
// bcctr 2,0,0 triggers a hardware assisted count cache flush
|
||||
#define SEC_FTR_BCCTR_FLUSH_ASSIST 0x0000000000000800ull
|
||||
|
||||
|
||||
// Features indicating need for Spectre/Meltdown mitigations
|
||||
|
||||
|
|
@ -74,6 +78,9 @@ static inline bool security_ftr_enabled(unsigned long feature)
|
|||
// Firmware configuration indicates user favours security over performance
|
||||
#define SEC_FTR_FAVOUR_SECURITY 0x0000000000000200ull
|
||||
|
||||
// Software required to flush count cache on context switch
|
||||
#define SEC_FTR_FLUSH_COUNT_CACHE 0x0000000000000400ull
|
||||
|
||||
|
||||
// Features enabled by default
|
||||
#define SEC_FTR_DEFAULT \
|
||||
|
|
|
|||
|
|
@ -8,6 +8,7 @@ extern void ppc_printk_progress(char *s, unsigned short hex);
|
|||
|
||||
extern unsigned int rtas_data;
|
||||
extern unsigned long long memory_limit;
|
||||
extern bool init_mem_is_free;
|
||||
extern unsigned long klimit;
|
||||
extern void *zalloc_maybe_bootmem(size_t size, gfp_t mask);
|
||||
|
||||
|
|
@ -50,6 +51,26 @@ enum l1d_flush_type {
|
|||
|
||||
void setup_rfi_flush(enum l1d_flush_type, bool enable);
|
||||
void do_rfi_flush_fixups(enum l1d_flush_type types);
|
||||
#ifdef CONFIG_PPC_BARRIER_NOSPEC
|
||||
void setup_barrier_nospec(void);
|
||||
#else
|
||||
static inline void setup_barrier_nospec(void) { };
|
||||
#endif
|
||||
void do_barrier_nospec_fixups(bool enable);
|
||||
extern bool barrier_nospec_enabled;
|
||||
|
||||
#ifdef CONFIG_PPC_BARRIER_NOSPEC
|
||||
void do_barrier_nospec_fixups_range(bool enable, void *start, void *end);
|
||||
#else
|
||||
static inline void do_barrier_nospec_fixups_range(bool enable, void *start, void *end) { };
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_PPC_FSL_BOOK3E
|
||||
void setup_spectre_v2(void);
|
||||
#else
|
||||
static inline void setup_spectre_v2(void) {};
|
||||
#endif
|
||||
void do_btb_flush_fixups(void);
|
||||
|
||||
#endif /* !__ASSEMBLY__ */
|
||||
|
||||
|
|
|
|||
|
|
@ -269,6 +269,7 @@ do { \
|
|||
__chk_user_ptr(ptr); \
|
||||
if (!is_kernel_addr((unsigned long)__gu_addr)) \
|
||||
might_fault(); \
|
||||
barrier_nospec(); \
|
||||
__get_user_size(__gu_val, __gu_addr, (size), __gu_err); \
|
||||
(x) = (__typeof__(*(ptr)))__gu_val; \
|
||||
__gu_err; \
|
||||
|
|
@ -280,8 +281,10 @@ do { \
|
|||
unsigned long __gu_val = 0; \
|
||||
__typeof__(*(ptr)) __user *__gu_addr = (ptr); \
|
||||
might_fault(); \
|
||||
if (access_ok(VERIFY_READ, __gu_addr, (size))) \
|
||||
if (access_ok(VERIFY_READ, __gu_addr, (size))) { \
|
||||
barrier_nospec(); \
|
||||
__get_user_size(__gu_val, __gu_addr, (size), __gu_err); \
|
||||
} \
|
||||
(x) = (__force __typeof__(*(ptr)))__gu_val; \
|
||||
__gu_err; \
|
||||
})
|
||||
|
|
@ -292,6 +295,7 @@ do { \
|
|||
unsigned long __gu_val; \
|
||||
__typeof__(*(ptr)) __user *__gu_addr = (ptr); \
|
||||
__chk_user_ptr(ptr); \
|
||||
barrier_nospec(); \
|
||||
__get_user_size(__gu_val, __gu_addr, (size), __gu_err); \
|
||||
(x) = (__force __typeof__(*(ptr)))__gu_val; \
|
||||
__gu_err; \
|
||||
|
|
@ -348,15 +352,19 @@ static inline unsigned long __copy_from_user_inatomic(void *to,
|
|||
|
||||
switch (n) {
|
||||
case 1:
|
||||
barrier_nospec();
|
||||
__get_user_size(*(u8 *)to, from, 1, ret);
|
||||
break;
|
||||
case 2:
|
||||
barrier_nospec();
|
||||
__get_user_size(*(u16 *)to, from, 2, ret);
|
||||
break;
|
||||
case 4:
|
||||
barrier_nospec();
|
||||
__get_user_size(*(u32 *)to, from, 4, ret);
|
||||
break;
|
||||
case 8:
|
||||
barrier_nospec();
|
||||
__get_user_size(*(u64 *)to, from, 8, ret);
|
||||
break;
|
||||
}
|
||||
|
|
@ -366,6 +374,7 @@ static inline unsigned long __copy_from_user_inatomic(void *to,
|
|||
|
||||
check_object_size(to, n, false);
|
||||
|
||||
barrier_nospec();
|
||||
return __copy_tofrom_user((__force void __user *)to, from, n);
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -44,9 +44,10 @@ obj-$(CONFIG_PPC64) += setup_64.o sys_ppc32.o \
|
|||
obj-$(CONFIG_VDSO32) += vdso32/
|
||||
obj-$(CONFIG_HAVE_HW_BREAKPOINT) += hw_breakpoint.o
|
||||
obj-$(CONFIG_PPC_BOOK3S_64) += cpu_setup_ppc970.o cpu_setup_pa6t.o
|
||||
obj-$(CONFIG_PPC_BOOK3S_64) += cpu_setup_power.o security.o
|
||||
obj-$(CONFIG_PPC_BOOK3S_64) += cpu_setup_power.o
|
||||
obj-$(CONFIG_PPC_BOOK3S_64) += mce.o mce_power.o
|
||||
obj-$(CONFIG_PPC_BOOK3E_64) += exceptions-64e.o idle_book3e.o
|
||||
obj-$(CONFIG_PPC_BARRIER_NOSPEC) += security.o
|
||||
obj-$(CONFIG_PPC64) += vdso64/
|
||||
obj-$(CONFIG_ALTIVEC) += vecemu.o
|
||||
obj-$(CONFIG_PPC_970_NAP) += idle_power4.o
|
||||
|
|
|
|||
|
|
@ -34,6 +34,7 @@
|
|||
#include <asm/ftrace.h>
|
||||
#include <asm/ptrace.h>
|
||||
#include <asm/export.h>
|
||||
#include <asm/barrier.h>
|
||||
|
||||
/*
|
||||
* MSR_KERNEL is > 0x10000 on 4xx/Book-E since it include MSR_CE.
|
||||
|
|
@ -347,6 +348,15 @@ syscall_dotrace_cont:
|
|||
ori r10,r10,sys_call_table@l
|
||||
slwi r0,r0,2
|
||||
bge- 66f
|
||||
|
||||
barrier_nospec_asm
|
||||
/*
|
||||
* Prevent the load of the handler below (based on the user-passed
|
||||
* system call number) being speculatively executed until the test
|
||||
* against NR_syscalls and branch to .66f above has
|
||||
* committed.
|
||||
*/
|
||||
|
||||
lwzx r10,r10,r0 /* Fetch system call handler [ptr] */
|
||||
mtlr r10
|
||||
addi r9,r1,STACK_FRAME_OVERHEAD
|
||||
|
|
|
|||
Some files were not shown because too many files have changed in this diff Show more
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Reference in a new issue