Char/Misc driver patches for 4.1-rc1
Here's the big char/misc driver patchset for 4.1-rc1. Lots of different driver subsystem updates here, nothing major, full details are in the shortlog below. All of this has been in linux-next for a while. Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> -----BEGIN PGP SIGNATURE----- Version: GnuPG v2 iEYEABECAAYFAlU2IMEACgkQMUfUDdst+yloDQCfbyIRL23WVAn9ckQse/y8gbjB OT4AoKTJbwndDP9Kb/lrj2tjd9QjNVrC =xhen -----END PGP SIGNATURE----- Merge tag 'char-misc-4.1-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/char-misc Pull char/misc driver updates from Greg KH: "Here's the big char/misc driver patchset for 4.1-rc1. Lots of different driver subsystem updates here, nothing major, full details are in the shortlog. All of this has been in linux-next for a while" * tag 'char-misc-4.1-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/char-misc: (133 commits) mei: trace: remove unused TRACE_SYSTEM_STRING DTS: ARM: OMAP3-N900: Add lis3lv02d support Documentation: DT: lis302: update wakeup binding lis3lv02d: DT: add wakeup unit 2 and wakeup threshold lis3lv02d: DT: use s32 to support negative values Drivers: hv: hv_balloon: correctly handle num_pages>INT_MAX case Drivers: hv: hv_balloon: correctly handle val.freeram<num_pages case mei: replace check for connection instead of transitioning mei: use mei_cl_is_connected consistently mei: fix mei_poll operation hv_vmbus: Add gradually increased delay for retries in vmbus_post_msg() Drivers: hv: hv_balloon: survive ballooning request with num_pages=0 Drivers: hv: hv_balloon: eliminate jumps in piecewiese linear floor function Drivers: hv: hv_balloon: do not online pages in offline blocks hv: remove the per-channel workqueue hv: don't schedule new works in vmbus_onoffer()/vmbus_onoffer_rescind() hv: run non-blocking message handlers in the dispatch tasklet coresight: moving to new "hwtracing" directory coresight-tmc: Adding a status interface to sysfs coresight: remove the unnecessary configuration coresight-default-sink ...
This commit is contained in:
Linus Torvalds
commit
1fc149933f
119 changed files with 4033 additions and 1482 deletions
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@ -61,7 +61,6 @@ Example:
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compatible = "arm,coresight-etb10", "arm,primecell";
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reg = <0 0x20010000 0 0x1000>;
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coresight-default-sink;
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clocks = <&oscclk6a>;
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clock-names = "apb_pclk";
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port {
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18
Documentation/devicetree/bindings/extcon/extcon-usb-gpio.txt
Normal file
18
Documentation/devicetree/bindings/extcon/extcon-usb-gpio.txt
Normal file
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@ -0,0 +1,18 @@
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USB GPIO Extcon device
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This is a virtual device used to generate USB cable states from the USB ID pin
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connected to a GPIO pin.
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Required properties:
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- compatible: Should be "linux,extcon-usb-gpio"
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- id-gpio: gpio for USB ID pin. See gpio binding.
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Example: Examples of extcon-usb-gpio node in dra7-evm.dts as listed below:
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extcon_usb1 {
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compatible = "linux,extcon-usb-gpio";
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id-gpio = <&gpio6 1 GPIO_ACTIVE_HIGH>;
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}
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&omap_dwc3_1 {
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extcon = <&extcon_usb1>;
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};
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@ -0,0 +1,75 @@
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* Ingenic JZ4780 NAND/external memory controller (NEMC)
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This file documents the device tree bindings for the NEMC external memory
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controller in Ingenic JZ4780
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Required properties:
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- compatible: Should be set to one of:
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"ingenic,jz4780-nemc" (JZ4780)
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- reg: Should specify the NEMC controller registers location and length.
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- clocks: Clock for the NEMC controller.
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- #address-cells: Must be set to 2.
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- #size-cells: Must be set to 1.
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- ranges: A set of ranges for each bank describing the physical memory layout.
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Each should specify the following 4 integer values:
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<cs number> 0 <physical address of mapping> <size of mapping>
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Each child of the NEMC node describes a device connected to the NEMC.
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Required child node properties:
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- reg: Should contain at least one register specifier, given in the following
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format:
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<cs number> <offset> <size>
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Multiple registers can be specified across multiple banks. This is needed,
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for example, for packaged NAND devices with multiple dies. Such devices
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should be grouped into a single node.
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Optional child node properties:
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- ingenic,nemc-bus-width: Specifies the bus width in bits. Defaults to 8 bits.
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- ingenic,nemc-tAS: Address setup time in nanoseconds.
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- ingenic,nemc-tAH: Address hold time in nanoseconds.
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- ingenic,nemc-tBP: Burst pitch time in nanoseconds.
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- ingenic,nemc-tAW: Access wait time in nanoseconds.
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- ingenic,nemc-tSTRV: Static memory recovery time in nanoseconds.
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If a child node references multiple banks in its "reg" property, the same value
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for all optional parameters will be configured for all banks. If any optional
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parameters are omitted, they will be left unchanged from whatever they are
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configured to when the NEMC device is probed (which may be the reset value as
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given in the hardware reference manual, or a value configured by the boot
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loader).
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Example (NEMC node with a NAND child device attached at CS1):
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nemc: nemc@13410000 {
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compatible = "ingenic,jz4780-nemc";
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reg = <0x13410000 0x10000>;
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#address-cells = <2>;
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#size-cells = <1>;
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ranges = <1 0 0x1b000000 0x1000000
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2 0 0x1a000000 0x1000000
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3 0 0x19000000 0x1000000
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4 0 0x18000000 0x1000000
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5 0 0x17000000 0x1000000
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6 0 0x16000000 0x1000000>;
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clocks = <&cgu JZ4780_CLK_NEMC>;
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nand: nand@1 {
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compatible = "ingenic,jz4780-nand";
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reg = <1 0 0x1000000>;
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ingenic,nemc-tAS = <10>;
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ingenic,nemc-tAH = <5>;
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ingenic,nemc-tBP = <10>;
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ingenic,nemc-tAW = <15>;
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ingenic,nemc-tSTRV = <100>;
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...
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};
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};
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@ -46,11 +46,18 @@ Optional properties for all bus drivers:
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interrupt 2
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- st,wakeup-{x,y,z}-{lo,hi}: set wakeup condition on x/y/z axis for
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upper/lower limit
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- st,wakeup-threshold: set wakeup threshold
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- st,wakeup2-{x,y,z}-{lo,hi}: set wakeup condition on x/y/z axis for
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upper/lower limit for second wakeup
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engine.
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- st,wakeup2-threshold: set wakeup threshold for second wakeup
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engine.
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- st,highpass-cutoff-hz=: 1, 2, 4 or 8 for 1Hz, 2Hz, 4Hz or 8Hz of
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highpass cut-off frequency
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- st,hipass{1,2}-disable: disable highpass 1/2.
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- st,default-rate=: set the default rate
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- st,axis-{x,y,z}=: set the axis to map to the three coordinates
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- st,axis-{x,y,z}=: set the axis to map to the three coordinates.
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Negative values can be used for inverted axis.
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- st,{min,max}-limit-{x,y,z} set the min/max limits for x/y/z axis
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(used by self-test)
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@ -1,6 +1,6 @@
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Qualcomm SPMI Controller (PMIC Arbiter)
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The SPMI PMIC Arbiter is found on the Snapdragon 800 Series. It is an SPMI
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The SPMI PMIC Arbiter is found on Snapdragon chipsets. It is an SPMI
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controller with wrapping arbitration logic to allow for multiple on-chip
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devices to control a single SPMI master.
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@ -19,6 +19,10 @@ Required properties:
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"core" - core registers
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"intr" - interrupt controller registers
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"cnfg" - configuration registers
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Registers used only for V2 PMIC Arbiter:
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"chnls" - tx-channel per virtual slave registers.
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"obsrvr" - rx-channel (called observer) per virtual slave registers.
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- reg : address + size pairs describing the PMIC arb register sets; order must
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correspond with the order of entries in reg-names
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- #address-cells : must be set to 2
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@ -276,6 +276,7 @@ IOMAP
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devm_ioport_unmap()
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devm_ioremap()
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devm_ioremap_nocache()
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devm_ioremap_wc()
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devm_ioremap_resource() : checks resource, requests memory region, ioremaps
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devm_iounmap()
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pcim_iomap()
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@ -14,7 +14,7 @@ document is concerned with the latter.
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HW assisted tracing is becoming increasingly useful when dealing with systems
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that have many SoCs and other components like GPU and DMA engines. ARM has
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developed a HW assisted tracing solution by means of different components, each
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being added to a design at systhesis time to cater to specific tracing needs.
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being added to a design at synthesis time to cater to specific tracing needs.
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Compoments are generally categorised as source, link and sinks and are
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(usually) discovered using the AMBA bus.
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@ -958,7 +958,7 @@ ARM/CORESIGHT FRAMEWORK AND DRIVERS
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M: Mathieu Poirier <mathieu.poirier@linaro.org>
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L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
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S: Maintained
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F: drivers/coresight/*
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F: drivers/hwtracing/coresight/*
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F: Documentation/trace/coresight.txt
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F: Documentation/devicetree/bindings/arm/coresight.txt
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F: Documentation/ABI/testing/sysfs-bus-coresight-devices-*
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@ -1828,7 +1828,7 @@ S: Supported
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F: drivers/spi/spi-atmel.*
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ATMEL SSC DRIVER
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M: Bo Shen <voice.shen@atmel.com>
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M: Nicolas Ferre <nicolas.ferre@atmel.com>
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L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
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S: Supported
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F: drivers/misc/atmel-ssc.c
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@ -1610,59 +1610,6 @@ config DEBUG_SET_MODULE_RONX
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against certain classes of kernel exploits.
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If in doubt, say "N".
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menuconfig CORESIGHT
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bool "CoreSight Tracing Support"
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select ARM_AMBA
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help
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This framework provides a kernel interface for the CoreSight debug
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and trace drivers to register themselves with. It's intended to build
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a topological view of the CoreSight components based on a DT
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specification and configure the right serie of components when a
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trace source gets enabled.
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source "drivers/hwtracing/coresight/Kconfig"
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if CORESIGHT
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config CORESIGHT_LINKS_AND_SINKS
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bool "CoreSight Link and Sink drivers"
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help
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This enables support for CoreSight link and sink drivers that are
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responsible for transporting and collecting the trace data
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respectively. Link and sinks are dynamically aggregated with a trace
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entity at run time to form a complete trace path.
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config CORESIGHT_LINK_AND_SINK_TMC
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bool "Coresight generic TMC driver"
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depends on CORESIGHT_LINKS_AND_SINKS
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help
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This enables support for the Trace Memory Controller driver. Depending
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on its configuration the device can act as a link (embedded trace router
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- ETR) or sink (embedded trace FIFO). The driver complies with the
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generic implementation of the component without special enhancement or
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added features.
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config CORESIGHT_SINK_TPIU
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bool "Coresight generic TPIU driver"
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depends on CORESIGHT_LINKS_AND_SINKS
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help
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This enables support for the Trace Port Interface Unit driver, responsible
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for bridging the gap between the on-chip coresight components and a trace
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port collection engine, typically connected to an external host for use
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case capturing more traces than the on-board coresight memory can handle.
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config CORESIGHT_SINK_ETBV10
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bool "Coresight ETBv1.0 driver"
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depends on CORESIGHT_LINKS_AND_SINKS
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help
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This enables support for the Embedded Trace Buffer version 1.0 driver
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that complies with the generic implementation of the component without
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special enhancement or added features.
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config CORESIGHT_SOURCE_ETM3X
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bool "CoreSight Embedded Trace Macrocell 3.x driver"
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select CORESIGHT_LINKS_AND_SINKS
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help
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This driver provides support for processor ETM3.x and PTM1.x modules,
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which allows tracing the instructions that a processor is executing
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This is primarily useful for instruction level tracing. Depending
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the ETM version data tracing may also be available.
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endif
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endmenu
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@ -275,7 +275,6 @@
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compatible = "arm,coresight-etb10", "arm,primecell";
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reg = <0 0xe3c42000 0 0x1000>;
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coresight-default-sink;
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clocks = <&clk_375m>;
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clock-names = "apb_pclk";
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port {
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|
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@ -150,7 +150,6 @@
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compatible = "arm,coresight-etb10", "arm,primecell";
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reg = <0x5401b000 0x1000>;
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coresight-default-sink;
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clocks = <&emu_src_ck>;
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clock-names = "apb_pclk";
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port {
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|
|
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@ -145,7 +145,6 @@
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compatible = "arm,coresight-etb10", "arm,primecell";
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reg = <0x5401b000 0x1000>;
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coresight-default-sink;
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clocks = <&emu_src_ck>;
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clock-names = "apb_pclk";
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port {
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|
|
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@ -609,6 +609,58 @@
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pinctrl-0 = <&i2c3_pins>;
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clock-frequency = <400000>;
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lis302dl: lis3lv02d@1d {
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compatible = "st,lis3lv02d";
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reg = <0x1d>;
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Vdd-supply = <&vaux1>;
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Vdd_IO-supply = <&vio>;
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interrupt-parent = <&gpio6>;
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interrupts = <21 20>; /* 181 and 180 */
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/* click flags */
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st,click-single-x;
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st,click-single-y;
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st,click-single-z;
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/* Limits are 0.5g * value */
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st,click-threshold-x = <8>;
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st,click-threshold-y = <8>;
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st,click-threshold-z = <10>;
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/* Click must be longer than time limit */
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st,click-time-limit = <9>;
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|
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/* Kind of debounce filter */
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st,click-latency = <50>;
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/* Interrupt line 2 for click detection */
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st,irq2-click;
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|
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st,wakeup-x-hi;
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st,wakeup-y-hi;
|
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st,wakeup-threshold = <(800/18)>; /* millig-value / 18 to get HW values */
|
||||
|
||||
st,wakeup2-z-hi;
|
||||
st,wakeup2-threshold = <(900/18)>; /* millig-value / 18 to get HW values */
|
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|
||||
st,hipass1-disable;
|
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st,hipass2-disable;
|
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|
||||
st,axis-x = <1>; /* LIS3_DEV_X */
|
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st,axis-y = <(-2)>; /* LIS3_INV_DEV_Y */
|
||||
st,axis-z = <(-3)>; /* LIS3_INV_DEV_Z */
|
||||
|
||||
st,min-limit-x = <(-32)>;
|
||||
st,min-limit-y = <3>;
|
||||
st,min-limit-z = <3>;
|
||||
|
||||
st,max-limit-x = <(-3)>;
|
||||
st,max-limit-y = <32>;
|
||||
st,max-limit-z = <32>;
|
||||
};
|
||||
};
|
||||
|
||||
&mmc1 {
|
||||
|
|
|
|||
|
|
@ -362,7 +362,6 @@
|
|||
compatible = "arm,coresight-etb10", "arm,primecell";
|
||||
reg = <0 0x20010000 0 0x1000>;
|
||||
|
||||
coresight-default-sink;
|
||||
clocks = <&oscclk6a>;
|
||||
clock-names = "apb_pclk";
|
||||
port {
|
||||
|
|
|
|||
|
|
@ -89,4 +89,6 @@ config DEBUG_ALIGN_RODATA
|
|||
|
||||
If in doubt, say N
|
||||
|
||||
source "drivers/hwtracing/coresight/Kconfig"
|
||||
|
||||
endmenu
|
||||
|
|
|
|||
|
|
@ -67,6 +67,7 @@ static inline void __iomem *ioremap(unsigned long offset, unsigned long size)
|
|||
|
||||
extern void iounmap(volatile void __iomem *addr);
|
||||
#define ioremap_nocache(off,size) ioremap(off,size)
|
||||
#define ioremap_wc ioremap_nocache
|
||||
|
||||
/*
|
||||
* IO bus memory addresses are also 1:1 with the physical address
|
||||
|
|
|
|||
|
|
@ -225,6 +225,8 @@
|
|||
#define HV_STATUS_INVALID_HYPERCALL_CODE 2
|
||||
#define HV_STATUS_INVALID_HYPERCALL_INPUT 3
|
||||
#define HV_STATUS_INVALID_ALIGNMENT 4
|
||||
#define HV_STATUS_INSUFFICIENT_MEMORY 11
|
||||
#define HV_STATUS_INVALID_CONNECTION_ID 18
|
||||
#define HV_STATUS_INSUFFICIENT_BUFFERS 19
|
||||
|
||||
typedef struct _HV_REFERENCE_TSC_PAGE {
|
||||
|
|
|
|||
|
|
@ -163,5 +163,5 @@ obj-$(CONFIG_POWERCAP) += powercap/
|
|||
obj-$(CONFIG_MCB) += mcb/
|
||||
obj-$(CONFIG_RAS) += ras/
|
||||
obj-$(CONFIG_THUNDERBOLT) += thunderbolt/
|
||||
obj-$(CONFIG_CORESIGHT) += coresight/
|
||||
obj-$(CONFIG_CORESIGHT) += hwtracing/coresight/
|
||||
obj-$(CONFIG_ANDROID) += android/
|
||||
|
|
|
|||
|
|
@ -300,11 +300,14 @@ static const struct file_operations rng_chrdev_ops = {
|
|||
.llseek = noop_llseek,
|
||||
};
|
||||
|
||||
static const struct attribute_group *rng_dev_groups[];
|
||||
|
||||
static struct miscdevice rng_miscdev = {
|
||||
.minor = RNG_MISCDEV_MINOR,
|
||||
.name = RNG_MODULE_NAME,
|
||||
.nodename = "hwrng",
|
||||
.fops = &rng_chrdev_ops,
|
||||
.groups = rng_dev_groups,
|
||||
};
|
||||
|
||||
|
||||
|
|
@ -377,37 +380,22 @@ static DEVICE_ATTR(rng_available, S_IRUGO,
|
|||
hwrng_attr_available_show,
|
||||
NULL);
|
||||
|
||||
static struct attribute *rng_dev_attrs[] = {
|
||||
&dev_attr_rng_current.attr,
|
||||
&dev_attr_rng_available.attr,
|
||||
NULL
|
||||
};
|
||||
|
||||
ATTRIBUTE_GROUPS(rng_dev);
|
||||
|
||||
static void __exit unregister_miscdev(void)
|
||||
{
|
||||
device_remove_file(rng_miscdev.this_device, &dev_attr_rng_available);
|
||||
device_remove_file(rng_miscdev.this_device, &dev_attr_rng_current);
|
||||
misc_deregister(&rng_miscdev);
|
||||
}
|
||||
|
||||
static int __init register_miscdev(void)
|
||||
{
|
||||
int err;
|
||||
|
||||
err = misc_register(&rng_miscdev);
|
||||
if (err)
|
||||
goto out;
|
||||
err = device_create_file(rng_miscdev.this_device,
|
||||
&dev_attr_rng_current);
|
||||
if (err)
|
||||
goto err_misc_dereg;
|
||||
err = device_create_file(rng_miscdev.this_device,
|
||||
&dev_attr_rng_available);
|
||||
if (err)
|
||||
goto err_remove_current;
|
||||
out:
|
||||
return err;
|
||||
|
||||
err_remove_current:
|
||||
device_remove_file(rng_miscdev.this_device, &dev_attr_rng_current);
|
||||
err_misc_dereg:
|
||||
misc_deregister(&rng_miscdev);
|
||||
goto out;
|
||||
return misc_register(&rng_miscdev);
|
||||
}
|
||||
|
||||
static int hwrng_fillfn(void *unused)
|
||||
|
|
|
|||
|
|
@ -133,7 +133,7 @@ static int rng_remove(struct platform_device *dev)
|
|||
return 0;
|
||||
}
|
||||
|
||||
static struct of_device_id rng_match[] = {
|
||||
static const struct of_device_id rng_match[] = {
|
||||
{ .compatible = "1682m-rng", },
|
||||
{ .compatible = "pasemi,pwrficient-rng", },
|
||||
{ },
|
||||
|
|
|
|||
Some files were not shown because too many files have changed in this diff Show more
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Reference in a new issue