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ARC updates for 4.7-rc1

Browse source 
- Support for EZChip (now Mellanox) NPS-400 Network processor based on ARC700
     http://www.mellanox.com/related-docs/prod_npu/PB_NPS-400.pdf
 - NPS interrupt controller and clocksource drivers
 - ARC timers probed off DT
 - ARC iqrchips switching to linear domain (upgrade from legacy domains)
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Merge tag 'arc-4.7-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/vgupta/arc

Pull ARC updates from Vineet Gupta:
 "We have a relatively big changeset for ARC for 4.7.

  The highlight is support for EZChip (now Mellanox) NPS-400 network
  processor, a 400-Gb throughput C-programmable packet processor based
  on ARC700 cores from Synopsys. See

        http://www.mellanox.com/related-docs/prod_npu/PB_NPS-400.pdf

  Also present are irqchip and clocksource drivers for NPS as agreed
  with respective maintainers to go via ARC tree due to an soc header
  dependency.  I have the needed ACKs from Jason, Marc, Daniel.  You
  might run into a trivial merge conflict in drivers/irqchip/*

  This EZChip platform support required some deep changes in ARC
  architecture code and also opportunity to cleanup past sins (legacy
  irq domains, missing irq domain lookup, hard coded timer irqs...)

  Summary:

   - Support for EZChip (now Mellanox) NPS-400 Network processor based
     on ARC700

   - NPS interrupt controller and clocksource drivers

   - ARC timers probed off DT

   - ARC iqrchips switching to linear domain (upgrade from legacy
     domains)"

* tag 'arc-4.7-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/vgupta/arc: (37 commits)
  arc: axs103_smp: Fix CPU frequency to 100MHz for dual-core
  arc: axs10x: Add DT bindings for I2S PLL Clock
  ARC: pae: STRICT_MM_TYPECHECKS was broken
  ARC: Add eznps platform to Kconfig and Makefile
  ARC: [plat-eznps] Use dedicated COMMAND_LINE_SIZE
  ARC: [plat-eznps] Use dedicated cpu_relax()
  ARC: [plat-eznps] Use dedicated identity auxiliary register.
  ARC: [plat-eznps] Use dedicated SMP barriers
  ARC: [plat-eznps] Use dedicated atomic/bitops/cmpxchg
  ARC: [plat-eznps] Use dedicated user stack top
  ARC: [plat-eznps] Add eznps platform
  ARC: [plat-eznps] Add eznps board defconfig and dts
  ARC: Mark secondary cpu online only after all HW setup is done
  ARC: rwlock: disable interrupts in !LLSC variant
  ARC: Make vmalloc size configurable
  ARC: clean out UAPI byteorder.h clean off Kconfig symbol
  irqchip: add nps Internal and external irqchips
  clocksource: Add NPS400 timers driver
  soc: Support for EZchip SoC
  Documentation: Add EZchip vendor to binding list
  ...
This commit is contained in:
Linus Torvalds 2016-05-19 09:46:18 -07:00
commit 0efacbbaee
70 changed files with 2334 additions and 284 deletions
Download patch file Download diff file Expand all files Collapse all files

7
Documentation/devicetree/bindings/arc/eznps.txt Normal file
View file

@ -0,0 +1,7 @@
EZchip NPS Network Processor Platforms Device Tree Bindings
---------------------------------------------------------------------------
Appliance main board with NPS400 ASIC.
Required root node properties:
- compatible = "ezchip,arc-nps";

17
Documentation/devicetree/bindings/interrupt-controller/ezchip,nps400-ic.txt Normal file
View file

@ -0,0 +1,17 @@
EZchip NPS Interrupt Controller
Required properties:
- compatible : should be "ezchip,nps400-ic"
- interrupt-controller : Identifies the node as an interrupt controller
- #interrupt-cells : Specifies the number of cells needed to encode an
interrupt source. The value shall be 1.
Example:
intc: interrupt-controller {
compatible = "ezchip,nps400-ic";
interrupt-controller;
#interrupt-cells = <1>;
};

15
Documentation/devicetree/bindings/timer/ezchip,nps400-timer.txt Normal file
View file

@ -0,0 +1,15 @@
NPS Network Processor
Required properties:
- compatible : should be "ezchip,nps400-timer"
Clocks required for compatible = "ezchip,nps400-timer":
- clocks : Must contain a single entry describing the clock input
Example:
timer {
compatible = "ezchip,nps400-timer";
clocks = <&sysclk>;
};

31
Documentation/devicetree/bindings/timer/snps,arc-timer.txt Normal file
View file

@ -0,0 +1,31 @@
Synopsys ARC Local Timer with Interrupt Capabilities
- Found on all ARC CPUs (ARC700/ARCHS)
- Can be optionally programmed to interrupt on Limit
- Two idential copies TIMER0 and TIMER1 exist in ARC cores and historically
TIMER0 used as clockevent provider (true for all ARC cores)
TIMER1 used for clocksource (mandatory for ARC700, optional for ARC HS)
Required properties:
- compatible : should be "snps,arc-timer"
- interrupts : single Interrupt going into parent intc
(16 for ARCHS cores, 3 for ARC700 cores)
- clocks : phandle to the source clock
Optional properties:
- interrupt-parent : phandle to parent intc
Example:
timer0 {
compatible = "snps,arc-timer";
interrupts = <3>;
interrupt-parent = <&core_intc>;
clocks = <&core_clk>;
};
timer1 {
compatible = "snps,arc-timer";
clocks = <&core_clk>;
};

14
Documentation/devicetree/bindings/timer/snps,archs-gfrc.txt Normal file
View file

@ -0,0 +1,14 @@
Synopsys ARC Free Running 64-bit Global Timer for ARC HS CPUs
- clocksource provider for SMP SoC
Required properties:
- compatible : should be "snps,archs-gfrc"
- clocks : phandle to the source clock
Example:
gfrc {
compatible = "snps,archs-gfrc";
clocks = <&core_clk>;
};

14
Documentation/devicetree/bindings/timer/snps,archs-rtc.txt Normal file
View file

@ -0,0 +1,14 @@
Synopsys ARC Free Running 64-bit Local Timer for ARC HS CPUs
- clocksource provider for UP SoC
Required properties:
- compatible : should be "snps,archs-rtc"
- clocks : phandle to the source clock
Example:
rtc {
compatible = "snps,arc-rtc";
clocks = <&core_clk>;
};

1
Documentation/devicetree/bindings/vendor-prefixes.txt
View file

@ -88,6 +88,7 @@ eukrea Eukréa Electromatique
everest Everest Semiconductor Co. Ltd.
everspin Everspin Technologies, Inc.
excito Excito
ezchip EZchip Semiconductor
fcs Fairchild Semiconductor
firefly Firefly
focaltech FocalTech Systems Co.,Ltd

6
MAINTAINERS
View file

@ -4444,6 +4444,12 @@ S: Maintained
F: drivers/video/fbdev/exynos/exynos_mipi*
F: include/video/exynos_mipi*
EZchip NPS platform support
M: Noam Camus <noamc@ezchip.com>
S: Supported
F: arch/arc/plat-eznps
F: arch/arc/boot/dts/eznps.dts
F71805F HARDWARE MONITORING DRIVER
M: Jean Delvare <jdelvare@suse.com>
L: linux-hwmon@vger.kernel.org

16
arch/arc/Kconfig
View file

@ -10,8 +10,9 @@ config ARC
def_bool y
select ARCH_SUPPORTS_ATOMIC_RMW if ARC_HAS_LLSC
select BUILDTIME_EXTABLE_SORT
select COMMON_CLK
select CLKSRC_OF
select CLONE_BACKWARDS
select COMMON_CLK
select GENERIC_ATOMIC64
select GENERIC_CLOCKEVENTS
select GENERIC_FIND_FIRST_BIT
@ -30,6 +31,7 @@ config ARC
select HAVE_MOD_ARCH_SPECIFIC if ARC_DW2_UNWIND
select HAVE_OPROFILE
select HAVE_PERF_EVENTS
select HANDLE_DOMAIN_IRQ
select IRQ_DOMAIN
select MODULES_USE_ELF_RELA
select NO_BOOTMEM
@ -95,6 +97,7 @@ source "arch/arc/plat-sim/Kconfig"
source "arch/arc/plat-tb10x/Kconfig"
source "arch/arc/plat-axs10x/Kconfig"
#New platform adds here
source "arch/arc/plat-eznps/Kconfig"
endmenu
@ -490,6 +493,17 @@ config ARCH_DMA_ADDR_T_64BIT
config ARC_PLAT_NEEDS_PHYS_TO_DMA
bool
config ARC_KVADDR_SIZE
int "Kernel Virtaul Address Space size (MB)"
range 0 512
default "256"
help
The kernel address space is carved out of 256MB of translated address
space for catering to vmalloc, modules, pkmap, fixmap. This however may
not suffice vmalloc requirements of a 4K CPU EZChip system. So allow
this to be stretched to 512 MB (by extending into the reserved
kernel-user gutter)
config ARC_CURR_IN_REG
bool "Dedicate Register r25 for current_task pointer"
default y

5
arch/arc/Makefile
View file

@ -115,6 +115,11 @@ core-y += arch/arc/boot/dts/
core-$(CONFIG_ARC_PLAT_SIM) += arch/arc/plat-sim/
core-$(CONFIG_ARC_PLAT_TB10X) += arch/arc/plat-tb10x/
core-$(CONFIG_ARC_PLAT_AXS10X) += arch/arc/plat-axs10x/
core-$(CONFIG_ARC_PLAT_EZNPS) += arch/arc/plat-eznps/
ifdef CONFIG_ARC_PLAT_EZNPS
KBUILD_CPPFLAGS += -I$(srctree)/arch/arc/plat-eznps/include
endif
drivers-$(CONFIG_OPROFILE) += arch/arc/oprofile/

14
arch/arc/boot/dts/abilis_tb10x.dtsi
View file

@ -35,6 +35,20 @@
};
};
/* TIMER0 with interrupt for clockevent */
timer0 {
compatible = "snps,arc-timer";
interrupts = <3>;
interrupt-parent = <&intc>;
clocks = <&cpu_clk>;
};
/* TIMER1 for free running clocksource */
timer1 {
compatible = "snps,arc-timer";
clocks = <&cpu_clk>;
};
soc100 {
#address-cells = <1>;
#size-cells = <1>;

14
arch/arc/boot/dts/axc001.dtsi
View file

@ -11,6 +11,8 @@
* Note that this file only supports the 770D CPU
*/
/include/ "skeleton.dtsi"
/ {
compatible = "snps,arc";
clock-frequency = <750000000>; /* 750 MHZ */
@ -24,7 +26,13 @@
ranges = <0x00000000 0xf0000000 0x10000000>;
cpu_intc: arc700-intc@cpu {
core_clk: core_clk {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <750000000>;
};
core_intc: arc700-intc@cpu {
compatible = "snps,arc700-intc";
interrupt-controller;
#interrupt-cells = <1>;
@ -48,7 +56,7 @@
reg = <0>;
interrupt-controller;
#interrupt-cells = <2>;
interrupt-parent = <&cpu_intc>;
interrupt-parent = <&core_intc>;
interrupts = <15>;
};
};
@ -86,7 +94,7 @@
compatible = "snps,dw-apb-ictl";
reg = < 0xe0012000 0x200 >;
interrupt-controller;
interrupt-parent = <&cpu_intc>;
interrupt-parent = <&core_intc>;
interrupts = < 7 >;
};

16
arch/arc/boot/dts/axc003.dtsi
View file

@ -10,6 +10,8 @@
* Device tree for AXC003 CPU card: HS38x UP configuration
*/
/include/ "skeleton_hs.dtsi"
/ {
compatible = "snps,arc";
clock-frequency = <90000000>;
@ -23,7 +25,13 @@
ranges = <0x00000000 0xf0000000 0x10000000>;
cpu_intc: archs-intc@cpu {
core_clk: core_clk {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <90000000>;
};
core_intc: archs-intc@cpu {
compatible = "snps,archs-intc";
interrupt-controller;
#interrupt-cells = <1>;
@ -47,7 +55,7 @@
reg = <0>;
interrupt-controller;
#interrupt-cells = <2>;
interrupt-parent = <&cpu_intc>;
interrupt-parent = <&core_intc>;
interrupts = <25>;
};
};
@ -66,7 +74,7 @@
arcpct0: pct {
compatible = "snps,archs-pct";
#interrupt-cells = <1>;
interrupt-parent = <&cpu_intc>;
interrupt-parent = <&core_intc>;
interrupts = <20>;
};
};
@ -89,7 +97,7 @@
compatible = "snps,dw-apb-ictl";
reg = < 0xe0012000 0x200 >;
interrupt-controller;
interrupt-parent = <&cpu_intc>;
interrupt-parent = <&core_intc>;
interrupts = < 24 >;
};

14
arch/arc/boot/dts/axc003_idu.dtsi
View file

@ -10,6 +10,8 @@
* Device tree for AXC003 CPU card: HS38x2 (Dual Core) with IDU intc
*/
/include/ "skeleton_hs_idu.dtsi"
/ {
compatible = "snps,arc";
clock-frequency = <90000000>;
@ -23,7 +25,13 @@
ranges = <0x00000000 0xf0000000 0x10000000>;
cpu_intc: archs-intc@cpu {
core_clk: core_clk {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <100000000>;
};
core_intc: archs-intc@cpu {
compatible = "snps,archs-intc";
interrupt-controller;
#interrupt-cells = <1>;
@ -32,7 +40,7 @@
idu_intc: idu-interrupt-controller {
compatible = "snps,archs-idu-intc";
interrupt-controller;
interrupt-parent = <&cpu_intc>;
interrupt-parent = <&core_intc>;
/*
* <hwirq distribution>
@ -89,7 +97,7 @@
arcpct0: pct {
compatible = "snps,archs-pct";
#interrupt-cells = <1>;
interrupt-parent = <&cpu_intc>;
interrupt-parent = <&core_intc>;
interrupts = <20>;
};
};

13
arch/arc/boot/dts/axs10x_mb.dtsi
View file

@ -16,7 +16,20 @@
ranges = <0x00000000 0xe0000000 0x10000000>;
interrupt-parent = <&mb_intc>;
i2sclk: i2sclk@100a0 {
compatible = "snps,axs10x-i2s-pll-clock";
reg = <0x100a0 0x10>;
clocks = <&i2spll_clk>;
#clock-cells = <0>;
};
clocks {
i2spll_clk: i2spll_clk {
compatible = "fixed-clock";
clock-frequency = <27000000>;
#clock-cells = <0>;
};
i2cclk: i2cclk {
compatible = "fixed-clock";
clock-frequency = <50000000>;

96
arch/arc/boot/dts/eznps.dts Normal file
View file

@ -0,0 +1,96 @@
/*
* Copyright(c) 2015 EZchip Technologies.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
* version 2, as published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* The full GNU General Public License is included in this distribution in
* the file called "COPYING".
*/
/dts-v1/;
/ {
compatible = "ezchip,arc-nps";
clock-frequency = <83333333>; /* 83.333333 MHZ */
#address-cells = <1>;
#size-cells = <1>;
interrupt-parent = <&intc>;
present-cpus = "0-1,16-17";
possible-cpus = "0-4095";
aliases {
ethernet0 = &gmac0;
};
chosen {
bootargs = "earlycon=uart8250,mmio32be,0xf7209000,115200n8 console=ttyS0,115200n8";
};
memory {
device_type = "memory";
reg = <0x80000000 0x20000000>; /* 512M */
};
clocks {
sysclk: sysclk {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <83333333>;
};
};
soc {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
/* child and parent address space 1:1 mapped */
ranges;
intc: interrupt-controller {
compatible = "ezchip,nps400-ic";
interrupt-controller;
#interrupt-cells = <1>;
};
timer0: timer_clkevt {
compatible = "snps,arc-timer";
interrupts = <3>;
clocks = <&sysclk>;
};
timer1: timer_clksrc {
compatible = "ezchip,nps400-timer";
clocks = <&sysclk>;
clock-names="sysclk";
};
uart@f7209000 {
compatible = "snps,dw-apb-uart";
device_type = "serial";
reg = <0xf7209000 0x100>;
interrupts = <6>;
clocks = <&sysclk>;
clock-names="baudclk";
baud = <115200>;
reg-shift = <2>;
reg-io-width = <4>;
native-endian;
};
gmac0: ethernet@f7470000 {
compatible = "ezchip,nps-mgt-enet";
reg = <0xf7470000 0x1940>;
interrupts = <7>;
/* Filled in by U-Boot */
mac-address = [ 00 C0 00 F0 04 03 ];
};
};
};

10
arch/arc/boot/dts/nsim_700.dts
View file

@ -14,7 +14,7 @@
clock-frequency = <80000000>; /* 80 MHZ */
#address-cells = <1>;
#size-cells = <1>;
interrupt-parent = <&intc>;
interrupt-parent = <&core_intc>;
chosen {
bootargs = "earlycon=arc_uart,mmio32,0xc0fc1000,115200n8 console=ttyARC0,115200n8";
@ -32,7 +32,13 @@
/* child and parent address space 1:1 mapped */
ranges;
intc: interrupt-controller {
core_clk: core_clk {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <80000000>;
};
core_intc: interrupt-controller {
compatible = "snps,arc700-intc";
interrupt-controller;
#interrupt-cells = <1>;

8
arch/arc/boot/dts/nsim_hs.dts
View file

@ -7,7 +7,7 @@
*/
/dts-v1/;
/include/ "skeleton.dtsi"
/include/ "skeleton_hs.dtsi"
/ {
compatible = "snps,nsim_hs";
@ -39,6 +39,12 @@
bus addr, parent bus addr, size */
ranges = <0x80000000 0x0 0x80000000 0x80000000>;
core_clk: core_clk {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <80000000>;
};
core_intc: core-interrupt-controller {
compatible = "snps,archs-intc";
interrupt-controller;

8
arch/arc/boot/dts/nsim_hs_idu.dts
View file

@ -7,7 +7,7 @@
*/
/dts-v1/;
/include/ "skeleton.dtsi"
/include/ "skeleton_hs_idu.dtsi"
/ {
compatible = "snps,nsim_hs";
@ -29,6 +29,12 @@
/* child and parent address space 1:1 mapped */
ranges;
core_clk: core_clk {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <80000000>;
};
core_intc: core-interrupt-controller {
compatible = "snps,archs-intc";
interrupt-controller;

10
arch/arc/boot/dts/nsimosci.dts
View file

@ -14,7 +14,7 @@
clock-frequency = <20000000>; /* 20 MHZ */
#address-cells = <1>;
#size-cells = <1>;
interrupt-parent = <&intc>;
interrupt-parent = <&core_intc>;
chosen {
/* this is for console on PGU */
@ -35,7 +35,13 @@
/* child and parent address space 1:1 mapped */
ranges;
intc: interrupt-controller {
core_clk: core_clk {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <20000000>;
};
core_intc: interrupt-controller {
compatible = "snps,arc700-intc";
interrupt-controller;
#interrupt-cells = <1>;

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